mv_otg.c 22 KB

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  1. /*
  2. * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
  3. * Author: Chao Xie <chao.xie@marvell.com>
  4. * Neil Zhang <zhangwm@marvell.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/io.h>
  15. #include <linux/uaccess.h>
  16. #include <linux/device.h>
  17. #include <linux/proc_fs.h>
  18. #include <linux/clk.h>
  19. #include <linux/workqueue.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/usb.h>
  22. #include <linux/usb/ch9.h>
  23. #include <linux/usb/otg.h>
  24. #include <linux/usb/gadget.h>
  25. #include <linux/usb/hcd.h>
  26. #include <linux/platform_data/mv_usb.h>
  27. #include "mv_otg.h"
  28. #define DRIVER_DESC "Marvell USB OTG transceiver driver"
  29. #define DRIVER_VERSION "Jan 20, 2010"
  30. MODULE_DESCRIPTION(DRIVER_DESC);
  31. MODULE_VERSION(DRIVER_VERSION);
  32. MODULE_LICENSE("GPL");
  33. static const char driver_name[] = "mv-otg";
  34. static char *state_string[] = {
  35. "undefined",
  36. "b_idle",
  37. "b_srp_init",
  38. "b_peripheral",
  39. "b_wait_acon",
  40. "b_host",
  41. "a_idle",
  42. "a_wait_vrise",
  43. "a_wait_bcon",
  44. "a_host",
  45. "a_suspend",
  46. "a_peripheral",
  47. "a_wait_vfall",
  48. "a_vbus_err"
  49. };
  50. static int mv_otg_set_vbus(struct otg_transceiver *otg, bool on)
  51. {
  52. struct mv_otg *mvotg = container_of(otg, struct mv_otg, otg);
  53. if (mvotg->pdata->set_vbus == NULL)
  54. return -ENODEV;
  55. return mvotg->pdata->set_vbus(on);
  56. }
  57. static int mv_otg_set_host(struct otg_transceiver *otg,
  58. struct usb_bus *host)
  59. {
  60. otg->host = host;
  61. return 0;
  62. }
  63. static int mv_otg_set_peripheral(struct otg_transceiver *otg,
  64. struct usb_gadget *gadget)
  65. {
  66. otg->gadget = gadget;
  67. return 0;
  68. }
  69. static void mv_otg_run_state_machine(struct mv_otg *mvotg,
  70. unsigned long delay)
  71. {
  72. dev_dbg(&mvotg->pdev->dev, "transceiver is updated\n");
  73. if (!mvotg->qwork)
  74. return;
  75. queue_delayed_work(mvotg->qwork, &mvotg->work, delay);
  76. }
  77. static void mv_otg_timer_await_bcon(unsigned long data)
  78. {
  79. struct mv_otg *mvotg = (struct mv_otg *) data;
  80. mvotg->otg_ctrl.a_wait_bcon_timeout = 1;
  81. dev_info(&mvotg->pdev->dev, "B Device No Response!\n");
  82. if (spin_trylock(&mvotg->wq_lock)) {
  83. mv_otg_run_state_machine(mvotg, 0);
  84. spin_unlock(&mvotg->wq_lock);
  85. }
  86. }
  87. static int mv_otg_cancel_timer(struct mv_otg *mvotg, unsigned int id)
  88. {
  89. struct timer_list *timer;
  90. if (id >= OTG_TIMER_NUM)
  91. return -EINVAL;
  92. timer = &mvotg->otg_ctrl.timer[id];
  93. if (timer_pending(timer))
  94. del_timer(timer);
  95. return 0;
  96. }
  97. static int mv_otg_set_timer(struct mv_otg *mvotg, unsigned int id,
  98. unsigned long interval,
  99. void (*callback) (unsigned long))
  100. {
  101. struct timer_list *timer;
  102. if (id >= OTG_TIMER_NUM)
  103. return -EINVAL;
  104. timer = &mvotg->otg_ctrl.timer[id];
  105. if (timer_pending(timer)) {
  106. dev_err(&mvotg->pdev->dev, "Timer%d is already running\n", id);
  107. return -EBUSY;
  108. }
  109. init_timer(timer);
  110. timer->data = (unsigned long) mvotg;
  111. timer->function = callback;
  112. timer->expires = jiffies + interval;
  113. add_timer(timer);
  114. return 0;
  115. }
  116. static int mv_otg_reset(struct mv_otg *mvotg)
  117. {
  118. unsigned int loops;
  119. u32 tmp;
  120. /* Stop the controller */
  121. tmp = readl(&mvotg->op_regs->usbcmd);
  122. tmp &= ~USBCMD_RUN_STOP;
  123. writel(tmp, &mvotg->op_regs->usbcmd);
  124. /* Reset the controller to get default values */
  125. writel(USBCMD_CTRL_RESET, &mvotg->op_regs->usbcmd);
  126. loops = 500;
  127. while (readl(&mvotg->op_regs->usbcmd) & USBCMD_CTRL_RESET) {
  128. if (loops == 0) {
  129. dev_err(&mvotg->pdev->dev,
  130. "Wait for RESET completed TIMEOUT\n");
  131. return -ETIMEDOUT;
  132. }
  133. loops--;
  134. udelay(20);
  135. }
  136. writel(0x0, &mvotg->op_regs->usbintr);
  137. tmp = readl(&mvotg->op_regs->usbsts);
  138. writel(tmp, &mvotg->op_regs->usbsts);
  139. return 0;
  140. }
  141. static void mv_otg_init_irq(struct mv_otg *mvotg)
  142. {
  143. u32 otgsc;
  144. mvotg->irq_en = OTGSC_INTR_A_SESSION_VALID
  145. | OTGSC_INTR_A_VBUS_VALID;
  146. mvotg->irq_status = OTGSC_INTSTS_A_SESSION_VALID
  147. | OTGSC_INTSTS_A_VBUS_VALID;
  148. if (mvotg->pdata->vbus == NULL) {
  149. mvotg->irq_en |= OTGSC_INTR_B_SESSION_VALID
  150. | OTGSC_INTR_B_SESSION_END;
  151. mvotg->irq_status |= OTGSC_INTSTS_B_SESSION_VALID
  152. | OTGSC_INTSTS_B_SESSION_END;
  153. }
  154. if (mvotg->pdata->id == NULL) {
  155. mvotg->irq_en |= OTGSC_INTR_USB_ID;
  156. mvotg->irq_status |= OTGSC_INTSTS_USB_ID;
  157. }
  158. otgsc = readl(&mvotg->op_regs->otgsc);
  159. otgsc |= mvotg->irq_en;
  160. writel(otgsc, &mvotg->op_regs->otgsc);
  161. }
  162. static void mv_otg_start_host(struct mv_otg *mvotg, int on)
  163. {
  164. struct otg_transceiver *otg = &mvotg->otg;
  165. struct usb_hcd *hcd;
  166. if (!otg->host)
  167. return;
  168. dev_info(&mvotg->pdev->dev, "%s host\n", on ? "start" : "stop");
  169. hcd = bus_to_hcd(otg->host);
  170. if (on)
  171. usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
  172. else
  173. usb_remove_hcd(hcd);
  174. }
  175. static void mv_otg_start_periphrals(struct mv_otg *mvotg, int on)
  176. {
  177. struct otg_transceiver *otg = &mvotg->otg;
  178. if (!otg->gadget)
  179. return;
  180. dev_info(otg->dev, "gadget %s\n", on ? "on" : "off");
  181. if (on)
  182. usb_gadget_vbus_connect(otg->gadget);
  183. else
  184. usb_gadget_vbus_disconnect(otg->gadget);
  185. }
  186. static void otg_clock_enable(struct mv_otg *mvotg)
  187. {
  188. unsigned int i;
  189. for (i = 0; i < mvotg->clknum; i++)
  190. clk_enable(mvotg->clk[i]);
  191. }
  192. static void otg_clock_disable(struct mv_otg *mvotg)
  193. {
  194. unsigned int i;
  195. for (i = 0; i < mvotg->clknum; i++)
  196. clk_disable(mvotg->clk[i]);
  197. }
  198. static int mv_otg_enable_internal(struct mv_otg *mvotg)
  199. {
  200. int retval = 0;
  201. if (mvotg->active)
  202. return 0;
  203. dev_dbg(&mvotg->pdev->dev, "otg enabled\n");
  204. otg_clock_enable(mvotg);
  205. if (mvotg->pdata->phy_init) {
  206. retval = mvotg->pdata->phy_init(mvotg->phy_regs);
  207. if (retval) {
  208. dev_err(&mvotg->pdev->dev,
  209. "init phy error %d\n", retval);
  210. otg_clock_disable(mvotg);
  211. return retval;
  212. }
  213. }
  214. mvotg->active = 1;
  215. return 0;
  216. }
  217. static int mv_otg_enable(struct mv_otg *mvotg)
  218. {
  219. if (mvotg->clock_gating)
  220. return mv_otg_enable_internal(mvotg);
  221. return 0;
  222. }
  223. static void mv_otg_disable_internal(struct mv_otg *mvotg)
  224. {
  225. if (mvotg->active) {
  226. dev_dbg(&mvotg->pdev->dev, "otg disabled\n");
  227. if (mvotg->pdata->phy_deinit)
  228. mvotg->pdata->phy_deinit(mvotg->phy_regs);
  229. otg_clock_disable(mvotg);
  230. mvotg->active = 0;
  231. }
  232. }
  233. static void mv_otg_disable(struct mv_otg *mvotg)
  234. {
  235. if (mvotg->clock_gating)
  236. mv_otg_disable_internal(mvotg);
  237. }
  238. static void mv_otg_update_inputs(struct mv_otg *mvotg)
  239. {
  240. struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
  241. u32 otgsc;
  242. otgsc = readl(&mvotg->op_regs->otgsc);
  243. if (mvotg->pdata->vbus) {
  244. if (mvotg->pdata->vbus->poll() == VBUS_HIGH) {
  245. otg_ctrl->b_sess_vld = 1;
  246. otg_ctrl->b_sess_end = 0;
  247. } else {
  248. otg_ctrl->b_sess_vld = 0;
  249. otg_ctrl->b_sess_end = 1;
  250. }
  251. } else {
  252. otg_ctrl->b_sess_vld = !!(otgsc & OTGSC_STS_B_SESSION_VALID);
  253. otg_ctrl->b_sess_end = !!(otgsc & OTGSC_STS_B_SESSION_END);
  254. }
  255. if (mvotg->pdata->id)
  256. otg_ctrl->id = !!mvotg->pdata->id->poll();
  257. else
  258. otg_ctrl->id = !!(otgsc & OTGSC_STS_USB_ID);
  259. if (mvotg->pdata->otg_force_a_bus_req && !otg_ctrl->id)
  260. otg_ctrl->a_bus_req = 1;
  261. otg_ctrl->a_sess_vld = !!(otgsc & OTGSC_STS_A_SESSION_VALID);
  262. otg_ctrl->a_vbus_vld = !!(otgsc & OTGSC_STS_A_VBUS_VALID);
  263. dev_dbg(&mvotg->pdev->dev, "%s: ", __func__);
  264. dev_dbg(&mvotg->pdev->dev, "id %d\n", otg_ctrl->id);
  265. dev_dbg(&mvotg->pdev->dev, "b_sess_vld %d\n", otg_ctrl->b_sess_vld);
  266. dev_dbg(&mvotg->pdev->dev, "b_sess_end %d\n", otg_ctrl->b_sess_end);
  267. dev_dbg(&mvotg->pdev->dev, "a_vbus_vld %d\n", otg_ctrl->a_vbus_vld);
  268. dev_dbg(&mvotg->pdev->dev, "a_sess_vld %d\n", otg_ctrl->a_sess_vld);
  269. }
  270. static void mv_otg_update_state(struct mv_otg *mvotg)
  271. {
  272. struct mv_otg_ctrl *otg_ctrl = &mvotg->otg_ctrl;
  273. struct otg_transceiver *otg = &mvotg->otg;
  274. int old_state = otg->state;
  275. switch (old_state) {
  276. case OTG_STATE_UNDEFINED:
  277. otg->state = OTG_STATE_B_IDLE;
  278. /* FALL THROUGH */
  279. case OTG_STATE_B_IDLE:
  280. if (otg_ctrl->id == 0)
  281. otg->state = OTG_STATE_A_IDLE;
  282. else if (otg_ctrl->b_sess_vld)
  283. otg->state = OTG_STATE_B_PERIPHERAL;
  284. break;
  285. case OTG_STATE_B_PERIPHERAL:
  286. if (!otg_ctrl->b_sess_vld || otg_ctrl->id == 0)
  287. otg->state = OTG_STATE_B_IDLE;
  288. break;
  289. case OTG_STATE_A_IDLE:
  290. if (otg_ctrl->id)
  291. otg->state = OTG_STATE_B_IDLE;
  292. else if (!(otg_ctrl->a_bus_drop) &&
  293. (otg_ctrl->a_bus_req || otg_ctrl->a_srp_det))
  294. otg->state = OTG_STATE_A_WAIT_VRISE;
  295. break;
  296. case OTG_STATE_A_WAIT_VRISE:
  297. if (otg_ctrl->a_vbus_vld)
  298. otg->state = OTG_STATE_A_WAIT_BCON;
  299. break;
  300. case OTG_STATE_A_WAIT_BCON:
  301. if (otg_ctrl->id || otg_ctrl->a_bus_drop
  302. || otg_ctrl->a_wait_bcon_timeout) {
  303. mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
  304. mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
  305. otg->state = OTG_STATE_A_WAIT_VFALL;
  306. otg_ctrl->a_bus_req = 0;
  307. } else if (!otg_ctrl->a_vbus_vld) {
  308. mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
  309. mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
  310. otg->state = OTG_STATE_A_VBUS_ERR;
  311. } else if (otg_ctrl->b_conn) {
  312. mv_otg_cancel_timer(mvotg, A_WAIT_BCON_TIMER);
  313. mvotg->otg_ctrl.a_wait_bcon_timeout = 0;
  314. otg->state = OTG_STATE_A_HOST;
  315. }
  316. break;
  317. case OTG_STATE_A_HOST:
  318. if (otg_ctrl->id || !otg_ctrl->b_conn
  319. || otg_ctrl->a_bus_drop)
  320. otg->state = OTG_STATE_A_WAIT_BCON;
  321. else if (!otg_ctrl->a_vbus_vld)
  322. otg->state = OTG_STATE_A_VBUS_ERR;
  323. break;
  324. case OTG_STATE_A_WAIT_VFALL:
  325. if (otg_ctrl->id
  326. || (!otg_ctrl->b_conn && otg_ctrl->a_sess_vld)
  327. || otg_ctrl->a_bus_req)
  328. otg->state = OTG_STATE_A_IDLE;
  329. break;
  330. case OTG_STATE_A_VBUS_ERR:
  331. if (otg_ctrl->id || otg_ctrl->a_clr_err
  332. || otg_ctrl->a_bus_drop) {
  333. otg_ctrl->a_clr_err = 0;
  334. otg->state = OTG_STATE_A_WAIT_VFALL;
  335. }
  336. break;
  337. default:
  338. break;
  339. }
  340. }
  341. static void mv_otg_work(struct work_struct *work)
  342. {
  343. struct mv_otg *mvotg;
  344. struct otg_transceiver *otg;
  345. int old_state;
  346. mvotg = container_of((struct delayed_work *)work, struct mv_otg, work);
  347. run:
  348. /* work queue is single thread, or we need spin_lock to protect */
  349. otg = &mvotg->otg;
  350. old_state = otg->state;
  351. if (!mvotg->active)
  352. return;
  353. mv_otg_update_inputs(mvotg);
  354. mv_otg_update_state(mvotg);
  355. if (old_state != otg->state) {
  356. dev_info(&mvotg->pdev->dev, "change from state %s to %s\n",
  357. state_string[old_state],
  358. state_string[otg->state]);
  359. switch (otg->state) {
  360. case OTG_STATE_B_IDLE:
  361. mvotg->otg.default_a = 0;
  362. if (old_state == OTG_STATE_B_PERIPHERAL)
  363. mv_otg_start_periphrals(mvotg, 0);
  364. mv_otg_reset(mvotg);
  365. mv_otg_disable(mvotg);
  366. break;
  367. case OTG_STATE_B_PERIPHERAL:
  368. mv_otg_enable(mvotg);
  369. mv_otg_start_periphrals(mvotg, 1);
  370. break;
  371. case OTG_STATE_A_IDLE:
  372. mvotg->otg.default_a = 1;
  373. mv_otg_enable(mvotg);
  374. if (old_state == OTG_STATE_A_WAIT_VFALL)
  375. mv_otg_start_host(mvotg, 0);
  376. mv_otg_reset(mvotg);
  377. break;
  378. case OTG_STATE_A_WAIT_VRISE:
  379. mv_otg_set_vbus(&mvotg->otg, 1);
  380. break;
  381. case OTG_STATE_A_WAIT_BCON:
  382. if (old_state != OTG_STATE_A_HOST)
  383. mv_otg_start_host(mvotg, 1);
  384. mv_otg_set_timer(mvotg, A_WAIT_BCON_TIMER,
  385. T_A_WAIT_BCON,
  386. mv_otg_timer_await_bcon);
  387. /*
  388. * Now, we directly enter A_HOST. So set b_conn = 1
  389. * here. In fact, it need host driver to notify us.
  390. */
  391. mvotg->otg_ctrl.b_conn = 1;
  392. break;
  393. case OTG_STATE_A_HOST:
  394. break;
  395. case OTG_STATE_A_WAIT_VFALL:
  396. /*
  397. * Now, we has exited A_HOST. So set b_conn = 0
  398. * here. In fact, it need host driver to notify us.
  399. */
  400. mvotg->otg_ctrl.b_conn = 0;
  401. mv_otg_set_vbus(&mvotg->otg, 0);
  402. break;
  403. case OTG_STATE_A_VBUS_ERR:
  404. break;
  405. default:
  406. break;
  407. }
  408. goto run;
  409. }
  410. }
  411. static irqreturn_t mv_otg_irq(int irq, void *dev)
  412. {
  413. struct mv_otg *mvotg = dev;
  414. u32 otgsc;
  415. otgsc = readl(&mvotg->op_regs->otgsc);
  416. writel(otgsc, &mvotg->op_regs->otgsc);
  417. /*
  418. * if we have vbus, then the vbus detection for B-device
  419. * will be done by mv_otg_inputs_irq().
  420. */
  421. if (mvotg->pdata->vbus)
  422. if ((otgsc & OTGSC_STS_USB_ID) &&
  423. !(otgsc & OTGSC_INTSTS_USB_ID))
  424. return IRQ_NONE;
  425. if ((otgsc & mvotg->irq_status) == 0)
  426. return IRQ_NONE;
  427. mv_otg_run_state_machine(mvotg, 0);
  428. return IRQ_HANDLED;
  429. }
  430. static irqreturn_t mv_otg_inputs_irq(int irq, void *dev)
  431. {
  432. struct mv_otg *mvotg = dev;
  433. /* The clock may disabled at this time */
  434. if (!mvotg->active) {
  435. mv_otg_enable(mvotg);
  436. mv_otg_init_irq(mvotg);
  437. }
  438. mv_otg_run_state_machine(mvotg, 0);
  439. return IRQ_HANDLED;
  440. }
  441. static ssize_t
  442. get_a_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
  443. {
  444. struct mv_otg *mvotg = dev_get_drvdata(dev);
  445. return scnprintf(buf, PAGE_SIZE, "%d\n",
  446. mvotg->otg_ctrl.a_bus_req);
  447. }
  448. static ssize_t
  449. set_a_bus_req(struct device *dev, struct device_attribute *attr,
  450. const char *buf, size_t count)
  451. {
  452. struct mv_otg *mvotg = dev_get_drvdata(dev);
  453. if (count > 2)
  454. return -1;
  455. /* We will use this interface to change to A device */
  456. if (mvotg->otg.state != OTG_STATE_B_IDLE
  457. && mvotg->otg.state != OTG_STATE_A_IDLE)
  458. return -1;
  459. /* The clock may disabled and we need to set irq for ID detected */
  460. mv_otg_enable(mvotg);
  461. mv_otg_init_irq(mvotg);
  462. if (buf[0] == '1') {
  463. mvotg->otg_ctrl.a_bus_req = 1;
  464. mvotg->otg_ctrl.a_bus_drop = 0;
  465. dev_dbg(&mvotg->pdev->dev,
  466. "User request: a_bus_req = 1\n");
  467. if (spin_trylock(&mvotg->wq_lock)) {
  468. mv_otg_run_state_machine(mvotg, 0);
  469. spin_unlock(&mvotg->wq_lock);
  470. }
  471. }
  472. return count;
  473. }
  474. static DEVICE_ATTR(a_bus_req, S_IRUGO | S_IWUSR, get_a_bus_req,
  475. set_a_bus_req);
  476. static ssize_t
  477. set_a_clr_err(struct device *dev, struct device_attribute *attr,
  478. const char *buf, size_t count)
  479. {
  480. struct mv_otg *mvotg = dev_get_drvdata(dev);
  481. if (!mvotg->otg.default_a)
  482. return -1;
  483. if (count > 2)
  484. return -1;
  485. if (buf[0] == '1') {
  486. mvotg->otg_ctrl.a_clr_err = 1;
  487. dev_dbg(&mvotg->pdev->dev,
  488. "User request: a_clr_err = 1\n");
  489. }
  490. if (spin_trylock(&mvotg->wq_lock)) {
  491. mv_otg_run_state_machine(mvotg, 0);
  492. spin_unlock(&mvotg->wq_lock);
  493. }
  494. return count;
  495. }
  496. static DEVICE_ATTR(a_clr_err, S_IWUSR, NULL, set_a_clr_err);
  497. static ssize_t
  498. get_a_bus_drop(struct device *dev, struct device_attribute *attr,
  499. char *buf)
  500. {
  501. struct mv_otg *mvotg = dev_get_drvdata(dev);
  502. return scnprintf(buf, PAGE_SIZE, "%d\n",
  503. mvotg->otg_ctrl.a_bus_drop);
  504. }
  505. static ssize_t
  506. set_a_bus_drop(struct device *dev, struct device_attribute *attr,
  507. const char *buf, size_t count)
  508. {
  509. struct mv_otg *mvotg = dev_get_drvdata(dev);
  510. if (!mvotg->otg.default_a)
  511. return -1;
  512. if (count > 2)
  513. return -1;
  514. if (buf[0] == '0') {
  515. mvotg->otg_ctrl.a_bus_drop = 0;
  516. dev_dbg(&mvotg->pdev->dev,
  517. "User request: a_bus_drop = 0\n");
  518. } else if (buf[0] == '1') {
  519. mvotg->otg_ctrl.a_bus_drop = 1;
  520. mvotg->otg_ctrl.a_bus_req = 0;
  521. dev_dbg(&mvotg->pdev->dev,
  522. "User request: a_bus_drop = 1\n");
  523. dev_dbg(&mvotg->pdev->dev,
  524. "User request: and a_bus_req = 0\n");
  525. }
  526. if (spin_trylock(&mvotg->wq_lock)) {
  527. mv_otg_run_state_machine(mvotg, 0);
  528. spin_unlock(&mvotg->wq_lock);
  529. }
  530. return count;
  531. }
  532. static DEVICE_ATTR(a_bus_drop, S_IRUGO | S_IWUSR,
  533. get_a_bus_drop, set_a_bus_drop);
  534. static struct attribute *inputs_attrs[] = {
  535. &dev_attr_a_bus_req.attr,
  536. &dev_attr_a_clr_err.attr,
  537. &dev_attr_a_bus_drop.attr,
  538. NULL,
  539. };
  540. static struct attribute_group inputs_attr_group = {
  541. .name = "inputs",
  542. .attrs = inputs_attrs,
  543. };
  544. int mv_otg_remove(struct platform_device *pdev)
  545. {
  546. struct mv_otg *mvotg = platform_get_drvdata(pdev);
  547. int clk_i;
  548. sysfs_remove_group(&mvotg->pdev->dev.kobj, &inputs_attr_group);
  549. if (mvotg->irq)
  550. free_irq(mvotg->irq, mvotg);
  551. if (mvotg->pdata->vbus)
  552. free_irq(mvotg->pdata->vbus->irq, mvotg);
  553. if (mvotg->pdata->id)
  554. free_irq(mvotg->pdata->id->irq, mvotg);
  555. if (mvotg->qwork) {
  556. flush_workqueue(mvotg->qwork);
  557. destroy_workqueue(mvotg->qwork);
  558. }
  559. mv_otg_disable(mvotg);
  560. if (mvotg->cap_regs)
  561. iounmap(mvotg->cap_regs);
  562. if (mvotg->phy_regs)
  563. iounmap(mvotg->phy_regs);
  564. for (clk_i = 0; clk_i <= mvotg->clknum; clk_i++)
  565. clk_put(mvotg->clk[clk_i]);
  566. otg_set_transceiver(NULL);
  567. platform_set_drvdata(pdev, NULL);
  568. kfree(mvotg);
  569. return 0;
  570. }
  571. static int mv_otg_probe(struct platform_device *pdev)
  572. {
  573. struct mv_usb_platform_data *pdata = pdev->dev.platform_data;
  574. struct mv_otg *mvotg;
  575. struct resource *r;
  576. int retval = 0, clk_i, i;
  577. size_t size;
  578. if (pdata == NULL) {
  579. dev_err(&pdev->dev, "failed to get platform data\n");
  580. return -ENODEV;
  581. }
  582. size = sizeof(*mvotg) + sizeof(struct clk *) * pdata->clknum;
  583. mvotg = kzalloc(size, GFP_KERNEL);
  584. if (!mvotg) {
  585. dev_err(&pdev->dev, "failed to allocate memory!\n");
  586. return -ENOMEM;
  587. }
  588. platform_set_drvdata(pdev, mvotg);
  589. mvotg->pdev = pdev;
  590. mvotg->pdata = pdata;
  591. mvotg->clknum = pdata->clknum;
  592. for (clk_i = 0; clk_i < mvotg->clknum; clk_i++) {
  593. mvotg->clk[clk_i] = clk_get(&pdev->dev, pdata->clkname[clk_i]);
  594. if (IS_ERR(mvotg->clk[clk_i])) {
  595. retval = PTR_ERR(mvotg->clk[clk_i]);
  596. goto err_put_clk;
  597. }
  598. }
  599. mvotg->qwork = create_singlethread_workqueue("mv_otg_queue");
  600. if (!mvotg->qwork) {
  601. dev_dbg(&pdev->dev, "cannot create workqueue for OTG\n");
  602. retval = -ENOMEM;
  603. goto err_put_clk;
  604. }
  605. INIT_DELAYED_WORK(&mvotg->work, mv_otg_work);
  606. /* OTG common part */
  607. mvotg->pdev = pdev;
  608. mvotg->otg.dev = &pdev->dev;
  609. mvotg->otg.label = driver_name;
  610. mvotg->otg.set_host = mv_otg_set_host;
  611. mvotg->otg.set_peripheral = mv_otg_set_peripheral;
  612. mvotg->otg.set_vbus = mv_otg_set_vbus;
  613. mvotg->otg.state = OTG_STATE_UNDEFINED;
  614. for (i = 0; i < OTG_TIMER_NUM; i++)
  615. init_timer(&mvotg->otg_ctrl.timer[i]);
  616. r = platform_get_resource_byname(mvotg->pdev,
  617. IORESOURCE_MEM, "phyregs");
  618. if (r == NULL) {
  619. dev_err(&pdev->dev, "no phy I/O memory resource defined\n");
  620. retval = -ENODEV;
  621. goto err_destroy_workqueue;
  622. }
  623. mvotg->phy_regs = ioremap(r->start, resource_size(r));
  624. if (mvotg->phy_regs == NULL) {
  625. dev_err(&pdev->dev, "failed to map phy I/O memory\n");
  626. retval = -EFAULT;
  627. goto err_destroy_workqueue;
  628. }
  629. r = platform_get_resource_byname(mvotg->pdev,
  630. IORESOURCE_MEM, "capregs");
  631. if (r == NULL) {
  632. dev_err(&pdev->dev, "no I/O memory resource defined\n");
  633. retval = -ENODEV;
  634. goto err_unmap_phyreg;
  635. }
  636. mvotg->cap_regs = ioremap(r->start, resource_size(r));
  637. if (mvotg->cap_regs == NULL) {
  638. dev_err(&pdev->dev, "failed to map I/O memory\n");
  639. retval = -EFAULT;
  640. goto err_unmap_phyreg;
  641. }
  642. /* we will acces controller register, so enable the udc controller */
  643. retval = mv_otg_enable_internal(mvotg);
  644. if (retval) {
  645. dev_err(&pdev->dev, "mv otg enable error %d\n", retval);
  646. goto err_unmap_capreg;
  647. }
  648. mvotg->op_regs =
  649. (struct mv_otg_regs __iomem *) ((unsigned long) mvotg->cap_regs
  650. + (readl(mvotg->cap_regs) & CAPLENGTH_MASK));
  651. if (pdata->id) {
  652. retval = request_threaded_irq(pdata->id->irq, NULL,
  653. mv_otg_inputs_irq,
  654. IRQF_ONESHOT, "id", mvotg);
  655. if (retval) {
  656. dev_info(&pdev->dev,
  657. "Failed to request irq for ID\n");
  658. pdata->id = NULL;
  659. }
  660. }
  661. if (pdata->vbus) {
  662. mvotg->clock_gating = 1;
  663. retval = request_threaded_irq(pdata->vbus->irq, NULL,
  664. mv_otg_inputs_irq,
  665. IRQF_ONESHOT, "vbus", mvotg);
  666. if (retval) {
  667. dev_info(&pdev->dev,
  668. "Failed to request irq for VBUS, "
  669. "disable clock gating\n");
  670. mvotg->clock_gating = 0;
  671. pdata->vbus = NULL;
  672. }
  673. }
  674. if (pdata->disable_otg_clock_gating)
  675. mvotg->clock_gating = 0;
  676. mv_otg_reset(mvotg);
  677. mv_otg_init_irq(mvotg);
  678. r = platform_get_resource(mvotg->pdev, IORESOURCE_IRQ, 0);
  679. if (r == NULL) {
  680. dev_err(&pdev->dev, "no IRQ resource defined\n");
  681. retval = -ENODEV;
  682. goto err_disable_clk;
  683. }
  684. mvotg->irq = r->start;
  685. if (request_irq(mvotg->irq, mv_otg_irq, IRQF_SHARED,
  686. driver_name, mvotg)) {
  687. dev_err(&pdev->dev, "Request irq %d for OTG failed\n",
  688. mvotg->irq);
  689. mvotg->irq = 0;
  690. retval = -ENODEV;
  691. goto err_disable_clk;
  692. }
  693. retval = otg_set_transceiver(&mvotg->otg);
  694. if (retval < 0) {
  695. dev_err(&pdev->dev, "can't register transceiver, %d\n",
  696. retval);
  697. goto err_free_irq;
  698. }
  699. retval = sysfs_create_group(&pdev->dev.kobj, &inputs_attr_group);
  700. if (retval < 0) {
  701. dev_dbg(&pdev->dev,
  702. "Can't register sysfs attr group: %d\n", retval);
  703. goto err_set_transceiver;
  704. }
  705. spin_lock_init(&mvotg->wq_lock);
  706. if (spin_trylock(&mvotg->wq_lock)) {
  707. mv_otg_run_state_machine(mvotg, 2 * HZ);
  708. spin_unlock(&mvotg->wq_lock);
  709. }
  710. dev_info(&pdev->dev,
  711. "successful probe OTG device %s clock gating.\n",
  712. mvotg->clock_gating ? "with" : "without");
  713. return 0;
  714. err_set_transceiver:
  715. otg_set_transceiver(NULL);
  716. err_free_irq:
  717. free_irq(mvotg->irq, mvotg);
  718. err_disable_clk:
  719. if (pdata->vbus)
  720. free_irq(pdata->vbus->irq, mvotg);
  721. if (pdata->id)
  722. free_irq(pdata->id->irq, mvotg);
  723. mv_otg_disable_internal(mvotg);
  724. err_unmap_capreg:
  725. iounmap(mvotg->cap_regs);
  726. err_unmap_phyreg:
  727. iounmap(mvotg->phy_regs);
  728. err_destroy_workqueue:
  729. flush_workqueue(mvotg->qwork);
  730. destroy_workqueue(mvotg->qwork);
  731. err_put_clk:
  732. for (clk_i--; clk_i >= 0; clk_i--)
  733. clk_put(mvotg->clk[clk_i]);
  734. platform_set_drvdata(pdev, NULL);
  735. kfree(mvotg);
  736. return retval;
  737. }
  738. #ifdef CONFIG_PM
  739. static int mv_otg_suspend(struct platform_device *pdev, pm_message_t state)
  740. {
  741. struct mv_otg *mvotg = platform_get_drvdata(pdev);
  742. if (mvotg->otg.state != OTG_STATE_B_IDLE) {
  743. dev_info(&pdev->dev,
  744. "OTG state is not B_IDLE, it is %d!\n",
  745. mvotg->otg.state);
  746. return -EAGAIN;
  747. }
  748. if (!mvotg->clock_gating)
  749. mv_otg_disable_internal(mvotg);
  750. return 0;
  751. }
  752. static int mv_otg_resume(struct platform_device *pdev)
  753. {
  754. struct mv_otg *mvotg = platform_get_drvdata(pdev);
  755. u32 otgsc;
  756. if (!mvotg->clock_gating) {
  757. mv_otg_enable_internal(mvotg);
  758. otgsc = readl(&mvotg->op_regs->otgsc);
  759. otgsc |= mvotg->irq_en;
  760. writel(otgsc, &mvotg->op_regs->otgsc);
  761. if (spin_trylock(&mvotg->wq_lock)) {
  762. mv_otg_run_state_machine(mvotg, 0);
  763. spin_unlock(&mvotg->wq_lock);
  764. }
  765. }
  766. return 0;
  767. }
  768. #endif
  769. static struct platform_driver mv_otg_driver = {
  770. .probe = mv_otg_probe,
  771. .remove = __exit_p(mv_otg_remove),
  772. .driver = {
  773. .owner = THIS_MODULE,
  774. .name = driver_name,
  775. },
  776. #ifdef CONFIG_PM
  777. .suspend = mv_otg_suspend,
  778. .resume = mv_otg_resume,
  779. #endif
  780. };
  781. static int __init mv_otg_init(void)
  782. {
  783. return platform_driver_register(&mv_otg_driver);
  784. }
  785. static void __exit mv_otg_exit(void)
  786. {
  787. platform_driver_unregister(&mv_otg_driver);
  788. }
  789. module_init(mv_otg_init);
  790. module_exit(mv_otg_exit);