r8a66597-udc.c 50 KB

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  1. /*
  2. * R8A66597 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2009 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/delay.h>
  15. #include <linux/io.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/clk.h>
  18. #include <linux/err.h>
  19. #include <linux/slab.h>
  20. #include <linux/dma-mapping.h>
  21. #include <linux/usb/ch9.h>
  22. #include <linux/usb/gadget.h>
  23. #include "r8a66597-udc.h"
  24. #define DRIVER_VERSION "2011-09-26"
  25. static const char udc_name[] = "r8a66597_udc";
  26. static const char *r8a66597_ep_name[] = {
  27. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7",
  28. "ep8", "ep9",
  29. };
  30. static void init_controller(struct r8a66597 *r8a66597);
  31. static void disable_controller(struct r8a66597 *r8a66597);
  32. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req);
  33. static void irq_packet_write(struct r8a66597_ep *ep,
  34. struct r8a66597_request *req);
  35. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  36. gfp_t gfp_flags);
  37. static void transfer_complete(struct r8a66597_ep *ep,
  38. struct r8a66597_request *req, int status);
  39. /*-------------------------------------------------------------------------*/
  40. static inline u16 get_usb_speed(struct r8a66597 *r8a66597)
  41. {
  42. return r8a66597_read(r8a66597, DVSTCTR0) & RHST;
  43. }
  44. static void enable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  45. unsigned long reg)
  46. {
  47. u16 tmp;
  48. tmp = r8a66597_read(r8a66597, INTENB0);
  49. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  50. INTENB0);
  51. r8a66597_bset(r8a66597, (1 << pipenum), reg);
  52. r8a66597_write(r8a66597, tmp, INTENB0);
  53. }
  54. static void disable_pipe_irq(struct r8a66597 *r8a66597, u16 pipenum,
  55. unsigned long reg)
  56. {
  57. u16 tmp;
  58. tmp = r8a66597_read(r8a66597, INTENB0);
  59. r8a66597_bclr(r8a66597, BEMPE | NRDYE | BRDYE,
  60. INTENB0);
  61. r8a66597_bclr(r8a66597, (1 << pipenum), reg);
  62. r8a66597_write(r8a66597, tmp, INTENB0);
  63. }
  64. static void r8a66597_usb_connect(struct r8a66597 *r8a66597)
  65. {
  66. r8a66597_bset(r8a66597, CTRE, INTENB0);
  67. r8a66597_bset(r8a66597, BEMPE | BRDYE, INTENB0);
  68. r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
  69. }
  70. static void r8a66597_usb_disconnect(struct r8a66597 *r8a66597)
  71. __releases(r8a66597->lock)
  72. __acquires(r8a66597->lock)
  73. {
  74. r8a66597_bclr(r8a66597, CTRE, INTENB0);
  75. r8a66597_bclr(r8a66597, BEMPE | BRDYE, INTENB0);
  76. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  77. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  78. spin_unlock(&r8a66597->lock);
  79. r8a66597->driver->disconnect(&r8a66597->gadget);
  80. spin_lock(&r8a66597->lock);
  81. disable_controller(r8a66597);
  82. init_controller(r8a66597);
  83. r8a66597_bset(r8a66597, VBSE, INTENB0);
  84. INIT_LIST_HEAD(&r8a66597->ep[0].queue);
  85. }
  86. static inline u16 control_reg_get_pid(struct r8a66597 *r8a66597, u16 pipenum)
  87. {
  88. u16 pid = 0;
  89. unsigned long offset;
  90. if (pipenum == 0) {
  91. pid = r8a66597_read(r8a66597, DCPCTR) & PID;
  92. } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  93. offset = get_pipectr_addr(pipenum);
  94. pid = r8a66597_read(r8a66597, offset) & PID;
  95. } else {
  96. dev_err(r8a66597_to_dev(r8a66597), "unexpect pipe num (%d)\n",
  97. pipenum);
  98. }
  99. return pid;
  100. }
  101. static inline void control_reg_set_pid(struct r8a66597 *r8a66597, u16 pipenum,
  102. u16 pid)
  103. {
  104. unsigned long offset;
  105. if (pipenum == 0) {
  106. r8a66597_mdfy(r8a66597, pid, PID, DCPCTR);
  107. } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  108. offset = get_pipectr_addr(pipenum);
  109. r8a66597_mdfy(r8a66597, pid, PID, offset);
  110. } else {
  111. dev_err(r8a66597_to_dev(r8a66597), "unexpect pipe num (%d)\n",
  112. pipenum);
  113. }
  114. }
  115. static inline void pipe_start(struct r8a66597 *r8a66597, u16 pipenum)
  116. {
  117. control_reg_set_pid(r8a66597, pipenum, PID_BUF);
  118. }
  119. static inline void pipe_stop(struct r8a66597 *r8a66597, u16 pipenum)
  120. {
  121. control_reg_set_pid(r8a66597, pipenum, PID_NAK);
  122. }
  123. static inline void pipe_stall(struct r8a66597 *r8a66597, u16 pipenum)
  124. {
  125. control_reg_set_pid(r8a66597, pipenum, PID_STALL);
  126. }
  127. static inline u16 control_reg_get(struct r8a66597 *r8a66597, u16 pipenum)
  128. {
  129. u16 ret = 0;
  130. unsigned long offset;
  131. if (pipenum == 0) {
  132. ret = r8a66597_read(r8a66597, DCPCTR);
  133. } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  134. offset = get_pipectr_addr(pipenum);
  135. ret = r8a66597_read(r8a66597, offset);
  136. } else {
  137. dev_err(r8a66597_to_dev(r8a66597), "unexpect pipe num (%d)\n",
  138. pipenum);
  139. }
  140. return ret;
  141. }
  142. static inline void control_reg_sqclr(struct r8a66597 *r8a66597, u16 pipenum)
  143. {
  144. unsigned long offset;
  145. pipe_stop(r8a66597, pipenum);
  146. if (pipenum == 0) {
  147. r8a66597_bset(r8a66597, SQCLR, DCPCTR);
  148. } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  149. offset = get_pipectr_addr(pipenum);
  150. r8a66597_bset(r8a66597, SQCLR, offset);
  151. } else {
  152. dev_err(r8a66597_to_dev(r8a66597), "unexpect pipe num (%d)\n",
  153. pipenum);
  154. }
  155. }
  156. static void control_reg_sqset(struct r8a66597 *r8a66597, u16 pipenum)
  157. {
  158. unsigned long offset;
  159. pipe_stop(r8a66597, pipenum);
  160. if (pipenum == 0) {
  161. r8a66597_bset(r8a66597, SQSET, DCPCTR);
  162. } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  163. offset = get_pipectr_addr(pipenum);
  164. r8a66597_bset(r8a66597, SQSET, offset);
  165. } else {
  166. dev_err(r8a66597_to_dev(r8a66597),
  167. "unexpect pipe num(%d)\n", pipenum);
  168. }
  169. }
  170. static u16 control_reg_sqmon(struct r8a66597 *r8a66597, u16 pipenum)
  171. {
  172. unsigned long offset;
  173. if (pipenum == 0) {
  174. return r8a66597_read(r8a66597, DCPCTR) & SQMON;
  175. } else if (pipenum < R8A66597_MAX_NUM_PIPE) {
  176. offset = get_pipectr_addr(pipenum);
  177. return r8a66597_read(r8a66597, offset) & SQMON;
  178. } else {
  179. dev_err(r8a66597_to_dev(r8a66597),
  180. "unexpect pipe num(%d)\n", pipenum);
  181. }
  182. return 0;
  183. }
  184. static u16 save_usb_toggle(struct r8a66597 *r8a66597, u16 pipenum)
  185. {
  186. return control_reg_sqmon(r8a66597, pipenum);
  187. }
  188. static void restore_usb_toggle(struct r8a66597 *r8a66597, u16 pipenum,
  189. u16 toggle)
  190. {
  191. if (toggle)
  192. control_reg_sqset(r8a66597, pipenum);
  193. else
  194. control_reg_sqclr(r8a66597, pipenum);
  195. }
  196. static inline int get_buffer_size(struct r8a66597 *r8a66597, u16 pipenum)
  197. {
  198. u16 tmp;
  199. int size;
  200. if (pipenum == 0) {
  201. tmp = r8a66597_read(r8a66597, DCPCFG);
  202. if ((tmp & R8A66597_CNTMD) != 0)
  203. size = 256;
  204. else {
  205. tmp = r8a66597_read(r8a66597, DCPMAXP);
  206. size = tmp & MAXP;
  207. }
  208. } else {
  209. r8a66597_write(r8a66597, pipenum, PIPESEL);
  210. tmp = r8a66597_read(r8a66597, PIPECFG);
  211. if ((tmp & R8A66597_CNTMD) != 0) {
  212. tmp = r8a66597_read(r8a66597, PIPEBUF);
  213. size = ((tmp >> 10) + 1) * 64;
  214. } else {
  215. tmp = r8a66597_read(r8a66597, PIPEMAXP);
  216. size = tmp & MXPS;
  217. }
  218. }
  219. return size;
  220. }
  221. static inline unsigned short mbw_value(struct r8a66597 *r8a66597)
  222. {
  223. if (r8a66597->pdata->on_chip)
  224. return MBW_32;
  225. else
  226. return MBW_16;
  227. }
  228. static void r8a66597_change_curpipe(struct r8a66597 *r8a66597, u16 pipenum,
  229. u16 isel, u16 fifosel)
  230. {
  231. u16 tmp, mask, loop;
  232. int i = 0;
  233. if (!pipenum) {
  234. mask = ISEL | CURPIPE;
  235. loop = isel;
  236. } else {
  237. mask = CURPIPE;
  238. loop = pipenum;
  239. }
  240. r8a66597_mdfy(r8a66597, loop, mask, fifosel);
  241. do {
  242. tmp = r8a66597_read(r8a66597, fifosel);
  243. if (i++ > 1000000) {
  244. dev_err(r8a66597_to_dev(r8a66597),
  245. "r8a66597: register%x, loop %x "
  246. "is timeout\n", fifosel, loop);
  247. break;
  248. }
  249. ndelay(1);
  250. } while ((tmp & mask) != loop);
  251. }
  252. static inline void pipe_change(struct r8a66597 *r8a66597, u16 pipenum)
  253. {
  254. struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
  255. if (ep->use_dma)
  256. r8a66597_bclr(r8a66597, DREQE, ep->fifosel);
  257. r8a66597_mdfy(r8a66597, pipenum, CURPIPE, ep->fifosel);
  258. ndelay(450);
  259. if (r8a66597_is_sudmac(r8a66597) && ep->use_dma)
  260. r8a66597_bclr(r8a66597, mbw_value(r8a66597), ep->fifosel);
  261. else
  262. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  263. if (ep->use_dma)
  264. r8a66597_bset(r8a66597, DREQE, ep->fifosel);
  265. }
  266. static int pipe_buffer_setting(struct r8a66597 *r8a66597,
  267. struct r8a66597_pipe_info *info)
  268. {
  269. u16 bufnum = 0, buf_bsize = 0;
  270. u16 pipecfg = 0;
  271. if (info->pipe == 0)
  272. return -EINVAL;
  273. r8a66597_write(r8a66597, info->pipe, PIPESEL);
  274. if (info->dir_in)
  275. pipecfg |= R8A66597_DIR;
  276. pipecfg |= info->type;
  277. pipecfg |= info->epnum;
  278. switch (info->type) {
  279. case R8A66597_INT:
  280. bufnum = 4 + (info->pipe - R8A66597_BASE_PIPENUM_INT);
  281. buf_bsize = 0;
  282. break;
  283. case R8A66597_BULK:
  284. /* isochronous pipes may be used as bulk pipes */
  285. if (info->pipe >= R8A66597_BASE_PIPENUM_BULK)
  286. bufnum = info->pipe - R8A66597_BASE_PIPENUM_BULK;
  287. else
  288. bufnum = info->pipe - R8A66597_BASE_PIPENUM_ISOC;
  289. bufnum = R8A66597_BASE_BUFNUM + (bufnum * 16);
  290. buf_bsize = 7;
  291. pipecfg |= R8A66597_DBLB;
  292. if (!info->dir_in)
  293. pipecfg |= R8A66597_SHTNAK;
  294. break;
  295. case R8A66597_ISO:
  296. bufnum = R8A66597_BASE_BUFNUM +
  297. (info->pipe - R8A66597_BASE_PIPENUM_ISOC) * 16;
  298. buf_bsize = 7;
  299. break;
  300. }
  301. if (buf_bsize && ((bufnum + 16) >= R8A66597_MAX_BUFNUM)) {
  302. pr_err("r8a66597 pipe memory is insufficient\n");
  303. return -ENOMEM;
  304. }
  305. r8a66597_write(r8a66597, pipecfg, PIPECFG);
  306. r8a66597_write(r8a66597, (buf_bsize << 10) | (bufnum), PIPEBUF);
  307. r8a66597_write(r8a66597, info->maxpacket, PIPEMAXP);
  308. if (info->interval)
  309. info->interval--;
  310. r8a66597_write(r8a66597, info->interval, PIPEPERI);
  311. return 0;
  312. }
  313. static void pipe_buffer_release(struct r8a66597 *r8a66597,
  314. struct r8a66597_pipe_info *info)
  315. {
  316. if (info->pipe == 0)
  317. return;
  318. if (is_bulk_pipe(info->pipe)) {
  319. r8a66597->bulk--;
  320. } else if (is_interrupt_pipe(info->pipe)) {
  321. r8a66597->interrupt--;
  322. } else if (is_isoc_pipe(info->pipe)) {
  323. r8a66597->isochronous--;
  324. if (info->type == R8A66597_BULK)
  325. r8a66597->bulk--;
  326. } else {
  327. dev_err(r8a66597_to_dev(r8a66597),
  328. "ep_release: unexpect pipenum (%d)\n", info->pipe);
  329. }
  330. }
  331. static void pipe_initialize(struct r8a66597_ep *ep)
  332. {
  333. struct r8a66597 *r8a66597 = ep->r8a66597;
  334. r8a66597_mdfy(r8a66597, 0, CURPIPE, ep->fifosel);
  335. r8a66597_write(r8a66597, ACLRM, ep->pipectr);
  336. r8a66597_write(r8a66597, 0, ep->pipectr);
  337. r8a66597_write(r8a66597, SQCLR, ep->pipectr);
  338. if (ep->use_dma) {
  339. r8a66597_mdfy(r8a66597, ep->pipenum, CURPIPE, ep->fifosel);
  340. ndelay(450);
  341. r8a66597_bset(r8a66597, mbw_value(r8a66597), ep->fifosel);
  342. }
  343. }
  344. static void r8a66597_ep_setting(struct r8a66597 *r8a66597,
  345. struct r8a66597_ep *ep,
  346. const struct usb_endpoint_descriptor *desc,
  347. u16 pipenum, int dma)
  348. {
  349. ep->use_dma = 0;
  350. ep->fifoaddr = CFIFO;
  351. ep->fifosel = CFIFOSEL;
  352. ep->fifoctr = CFIFOCTR;
  353. ep->pipectr = get_pipectr_addr(pipenum);
  354. if (is_bulk_pipe(pipenum) || is_isoc_pipe(pipenum)) {
  355. ep->pipetre = get_pipetre_addr(pipenum);
  356. ep->pipetrn = get_pipetrn_addr(pipenum);
  357. } else {
  358. ep->pipetre = 0;
  359. ep->pipetrn = 0;
  360. }
  361. ep->pipenum = pipenum;
  362. ep->ep.maxpacket = usb_endpoint_maxp(desc);
  363. r8a66597->pipenum2ep[pipenum] = ep;
  364. r8a66597->epaddr2ep[desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK]
  365. = ep;
  366. INIT_LIST_HEAD(&ep->queue);
  367. }
  368. static void r8a66597_ep_release(struct r8a66597_ep *ep)
  369. {
  370. struct r8a66597 *r8a66597 = ep->r8a66597;
  371. u16 pipenum = ep->pipenum;
  372. if (pipenum == 0)
  373. return;
  374. if (ep->use_dma)
  375. r8a66597->num_dma--;
  376. ep->pipenum = 0;
  377. ep->busy = 0;
  378. ep->use_dma = 0;
  379. }
  380. static int alloc_pipe_config(struct r8a66597_ep *ep,
  381. const struct usb_endpoint_descriptor *desc)
  382. {
  383. struct r8a66597 *r8a66597 = ep->r8a66597;
  384. struct r8a66597_pipe_info info;
  385. int dma = 0;
  386. unsigned char *counter;
  387. int ret;
  388. ep->desc = desc;
  389. if (ep->pipenum) /* already allocated pipe */
  390. return 0;
  391. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  392. case USB_ENDPOINT_XFER_BULK:
  393. if (r8a66597->bulk >= R8A66597_MAX_NUM_BULK) {
  394. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  395. dev_err(r8a66597_to_dev(r8a66597),
  396. "bulk pipe is insufficient\n");
  397. return -ENODEV;
  398. } else {
  399. info.pipe = R8A66597_BASE_PIPENUM_ISOC
  400. + r8a66597->isochronous;
  401. counter = &r8a66597->isochronous;
  402. }
  403. } else {
  404. info.pipe = R8A66597_BASE_PIPENUM_BULK + r8a66597->bulk;
  405. counter = &r8a66597->bulk;
  406. }
  407. info.type = R8A66597_BULK;
  408. dma = 1;
  409. break;
  410. case USB_ENDPOINT_XFER_INT:
  411. if (r8a66597->interrupt >= R8A66597_MAX_NUM_INT) {
  412. dev_err(r8a66597_to_dev(r8a66597),
  413. "interrupt pipe is insufficient\n");
  414. return -ENODEV;
  415. }
  416. info.pipe = R8A66597_BASE_PIPENUM_INT + r8a66597->interrupt;
  417. info.type = R8A66597_INT;
  418. counter = &r8a66597->interrupt;
  419. break;
  420. case USB_ENDPOINT_XFER_ISOC:
  421. if (r8a66597->isochronous >= R8A66597_MAX_NUM_ISOC) {
  422. dev_err(r8a66597_to_dev(r8a66597),
  423. "isochronous pipe is insufficient\n");
  424. return -ENODEV;
  425. }
  426. info.pipe = R8A66597_BASE_PIPENUM_ISOC + r8a66597->isochronous;
  427. info.type = R8A66597_ISO;
  428. counter = &r8a66597->isochronous;
  429. break;
  430. default:
  431. dev_err(r8a66597_to_dev(r8a66597), "unexpect xfer type\n");
  432. return -EINVAL;
  433. }
  434. ep->type = info.type;
  435. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  436. info.maxpacket = usb_endpoint_maxp(desc);
  437. info.interval = desc->bInterval;
  438. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  439. info.dir_in = 1;
  440. else
  441. info.dir_in = 0;
  442. ret = pipe_buffer_setting(r8a66597, &info);
  443. if (ret < 0) {
  444. dev_err(r8a66597_to_dev(r8a66597),
  445. "pipe_buffer_setting fail\n");
  446. return ret;
  447. }
  448. (*counter)++;
  449. if ((counter == &r8a66597->isochronous) && info.type == R8A66597_BULK)
  450. r8a66597->bulk++;
  451. r8a66597_ep_setting(r8a66597, ep, desc, info.pipe, dma);
  452. pipe_initialize(ep);
  453. return 0;
  454. }
  455. static int free_pipe_config(struct r8a66597_ep *ep)
  456. {
  457. struct r8a66597 *r8a66597 = ep->r8a66597;
  458. struct r8a66597_pipe_info info;
  459. info.pipe = ep->pipenum;
  460. info.type = ep->type;
  461. pipe_buffer_release(r8a66597, &info);
  462. r8a66597_ep_release(ep);
  463. return 0;
  464. }
  465. /*-------------------------------------------------------------------------*/
  466. static void pipe_irq_enable(struct r8a66597 *r8a66597, u16 pipenum)
  467. {
  468. enable_irq_ready(r8a66597, pipenum);
  469. enable_irq_nrdy(r8a66597, pipenum);
  470. }
  471. static void pipe_irq_disable(struct r8a66597 *r8a66597, u16 pipenum)
  472. {
  473. disable_irq_ready(r8a66597, pipenum);
  474. disable_irq_nrdy(r8a66597, pipenum);
  475. }
  476. /* if complete is true, gadget driver complete function is not call */
  477. static void control_end(struct r8a66597 *r8a66597, unsigned ccpl)
  478. {
  479. r8a66597->ep[0].internal_ccpl = ccpl;
  480. pipe_start(r8a66597, 0);
  481. r8a66597_bset(r8a66597, CCPL, DCPCTR);
  482. }
  483. static void start_ep0_write(struct r8a66597_ep *ep,
  484. struct r8a66597_request *req)
  485. {
  486. struct r8a66597 *r8a66597 = ep->r8a66597;
  487. pipe_change(r8a66597, ep->pipenum);
  488. r8a66597_mdfy(r8a66597, ISEL, (ISEL | CURPIPE), CFIFOSEL);
  489. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  490. if (req->req.length == 0) {
  491. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  492. pipe_start(r8a66597, 0);
  493. transfer_complete(ep, req, 0);
  494. } else {
  495. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  496. irq_ep0_write(ep, req);
  497. }
  498. }
  499. static void disable_fifosel(struct r8a66597 *r8a66597, u16 pipenum,
  500. u16 fifosel)
  501. {
  502. u16 tmp;
  503. tmp = r8a66597_read(r8a66597, fifosel) & CURPIPE;
  504. if (tmp == pipenum)
  505. r8a66597_change_curpipe(r8a66597, 0, 0, fifosel);
  506. }
  507. static void change_bfre_mode(struct r8a66597 *r8a66597, u16 pipenum,
  508. int enable)
  509. {
  510. struct r8a66597_ep *ep = r8a66597->pipenum2ep[pipenum];
  511. u16 tmp, toggle;
  512. /* check current BFRE bit */
  513. r8a66597_write(r8a66597, pipenum, PIPESEL);
  514. tmp = r8a66597_read(r8a66597, PIPECFG) & R8A66597_BFRE;
  515. if ((enable && tmp) || (!enable && !tmp))
  516. return;
  517. /* change BFRE bit */
  518. pipe_stop(r8a66597, pipenum);
  519. disable_fifosel(r8a66597, pipenum, CFIFOSEL);
  520. disable_fifosel(r8a66597, pipenum, D0FIFOSEL);
  521. disable_fifosel(r8a66597, pipenum, D1FIFOSEL);
  522. toggle = save_usb_toggle(r8a66597, pipenum);
  523. r8a66597_write(r8a66597, pipenum, PIPESEL);
  524. if (enable)
  525. r8a66597_bset(r8a66597, R8A66597_BFRE, PIPECFG);
  526. else
  527. r8a66597_bclr(r8a66597, R8A66597_BFRE, PIPECFG);
  528. /* initialize for internal BFRE flag */
  529. r8a66597_bset(r8a66597, ACLRM, ep->pipectr);
  530. r8a66597_bclr(r8a66597, ACLRM, ep->pipectr);
  531. restore_usb_toggle(r8a66597, pipenum, toggle);
  532. }
  533. static int sudmac_alloc_channel(struct r8a66597 *r8a66597,
  534. struct r8a66597_ep *ep,
  535. struct r8a66597_request *req)
  536. {
  537. struct r8a66597_dma *dma;
  538. if (!r8a66597_is_sudmac(r8a66597))
  539. return -ENODEV;
  540. /* Check transfer type */
  541. if (!is_bulk_pipe(ep->pipenum))
  542. return -EIO;
  543. if (r8a66597->dma.used)
  544. return -EBUSY;
  545. /* set SUDMAC parameters */
  546. dma = &r8a66597->dma;
  547. dma->used = 1;
  548. if (ep->desc->bEndpointAddress & USB_DIR_IN) {
  549. dma->dir = 1;
  550. } else {
  551. dma->dir = 0;
  552. change_bfre_mode(r8a66597, ep->pipenum, 1);
  553. }
  554. /* set r8a66597_ep paramters */
  555. ep->use_dma = 1;
  556. ep->dma = dma;
  557. ep->fifoaddr = D0FIFO;
  558. ep->fifosel = D0FIFOSEL;
  559. ep->fifoctr = D0FIFOCTR;
  560. /* dma mapping */
  561. req->req.dma = dma_map_single(r8a66597_to_dev(ep->r8a66597),
  562. req->req.buf, req->req.length,
  563. dma->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  564. return 0;
  565. }
  566. static void sudmac_free_channel(struct r8a66597 *r8a66597,
  567. struct r8a66597_ep *ep,
  568. struct r8a66597_request *req)
  569. {
  570. if (!r8a66597_is_sudmac(r8a66597))
  571. return;
  572. dma_unmap_single(r8a66597_to_dev(ep->r8a66597),
  573. req->req.dma, req->req.length,
  574. ep->dma->dir ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  575. r8a66597_bclr(r8a66597, DREQE, ep->fifosel);
  576. r8a66597_change_curpipe(r8a66597, 0, 0, ep->fifosel);
  577. ep->dma->used = 0;
  578. ep->use_dma = 0;
  579. ep->fifoaddr = CFIFO;
  580. ep->fifosel = CFIFOSEL;
  581. ep->fifoctr = CFIFOCTR;
  582. }
  583. static void sudmac_start(struct r8a66597 *r8a66597, struct r8a66597_ep *ep,
  584. struct r8a66597_request *req)
  585. {
  586. BUG_ON(req->req.length == 0);
  587. r8a66597_sudmac_write(r8a66597, LBA_WAIT, CH0CFG);
  588. r8a66597_sudmac_write(r8a66597, req->req.dma, CH0BA);
  589. r8a66597_sudmac_write(r8a66597, req->req.length, CH0BBC);
  590. r8a66597_sudmac_write(r8a66597, CH0ENDE, DINTCTRL);
  591. r8a66597_sudmac_write(r8a66597, DEN, CH0DEN);
  592. }
  593. static void start_packet_write(struct r8a66597_ep *ep,
  594. struct r8a66597_request *req)
  595. {
  596. struct r8a66597 *r8a66597 = ep->r8a66597;
  597. u16 tmp;
  598. pipe_change(r8a66597, ep->pipenum);
  599. disable_irq_empty(r8a66597, ep->pipenum);
  600. pipe_start(r8a66597, ep->pipenum);
  601. if (req->req.length == 0) {
  602. transfer_complete(ep, req, 0);
  603. } else {
  604. r8a66597_write(r8a66597, ~(1 << ep->pipenum), BRDYSTS);
  605. if (sudmac_alloc_channel(r8a66597, ep, req) < 0) {
  606. /* PIO mode */
  607. pipe_change(r8a66597, ep->pipenum);
  608. disable_irq_empty(r8a66597, ep->pipenum);
  609. pipe_start(r8a66597, ep->pipenum);
  610. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  611. if (unlikely((tmp & FRDY) == 0))
  612. pipe_irq_enable(r8a66597, ep->pipenum);
  613. else
  614. irq_packet_write(ep, req);
  615. } else {
  616. /* DMA mode */
  617. pipe_change(r8a66597, ep->pipenum);
  618. disable_irq_nrdy(r8a66597, ep->pipenum);
  619. pipe_start(r8a66597, ep->pipenum);
  620. enable_irq_nrdy(r8a66597, ep->pipenum);
  621. sudmac_start(r8a66597, ep, req);
  622. }
  623. }
  624. }
  625. static void start_packet_read(struct r8a66597_ep *ep,
  626. struct r8a66597_request *req)
  627. {
  628. struct r8a66597 *r8a66597 = ep->r8a66597;
  629. u16 pipenum = ep->pipenum;
  630. if (ep->pipenum == 0) {
  631. r8a66597_mdfy(r8a66597, 0, (ISEL | CURPIPE), CFIFOSEL);
  632. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  633. pipe_start(r8a66597, pipenum);
  634. pipe_irq_enable(r8a66597, pipenum);
  635. } else {
  636. pipe_stop(r8a66597, pipenum);
  637. if (ep->pipetre) {
  638. enable_irq_nrdy(r8a66597, pipenum);
  639. r8a66597_write(r8a66597, TRCLR, ep->pipetre);
  640. r8a66597_write(r8a66597,
  641. DIV_ROUND_UP(req->req.length, ep->ep.maxpacket),
  642. ep->pipetrn);
  643. r8a66597_bset(r8a66597, TRENB, ep->pipetre);
  644. }
  645. if (sudmac_alloc_channel(r8a66597, ep, req) < 0) {
  646. /* PIO mode */
  647. change_bfre_mode(r8a66597, ep->pipenum, 0);
  648. pipe_start(r8a66597, pipenum); /* trigger once */
  649. pipe_irq_enable(r8a66597, pipenum);
  650. } else {
  651. pipe_change(r8a66597, pipenum);
  652. sudmac_start(r8a66597, ep, req);
  653. pipe_start(r8a66597, pipenum); /* trigger once */
  654. }
  655. }
  656. }
  657. static void start_packet(struct r8a66597_ep *ep, struct r8a66597_request *req)
  658. {
  659. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  660. start_packet_write(ep, req);
  661. else
  662. start_packet_read(ep, req);
  663. }
  664. static void start_ep0(struct r8a66597_ep *ep, struct r8a66597_request *req)
  665. {
  666. u16 ctsq;
  667. ctsq = r8a66597_read(ep->r8a66597, INTSTS0) & CTSQ;
  668. switch (ctsq) {
  669. case CS_RDDS:
  670. start_ep0_write(ep, req);
  671. break;
  672. case CS_WRDS:
  673. start_packet_read(ep, req);
  674. break;
  675. case CS_WRND:
  676. control_end(ep->r8a66597, 0);
  677. break;
  678. default:
  679. dev_err(r8a66597_to_dev(ep->r8a66597),
  680. "start_ep0: unexpect ctsq(%x)\n", ctsq);
  681. break;
  682. }
  683. }
  684. static void init_controller(struct r8a66597 *r8a66597)
  685. {
  686. u16 vif = r8a66597->pdata->vif ? LDRV : 0;
  687. u16 irq_sense = r8a66597->irq_sense_low ? INTL : 0;
  688. u16 endian = r8a66597->pdata->endian ? BIGEND : 0;
  689. if (r8a66597->pdata->on_chip) {
  690. if (r8a66597->pdata->buswait)
  691. r8a66597_write(r8a66597, r8a66597->pdata->buswait,
  692. SYSCFG1);
  693. else
  694. r8a66597_write(r8a66597, 0x0f, SYSCFG1);
  695. r8a66597_bset(r8a66597, HSE, SYSCFG0);
  696. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  697. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  698. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  699. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  700. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  701. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  702. DMA0CFG);
  703. } else {
  704. r8a66597_bset(r8a66597, vif | endian, PINCFG);
  705. r8a66597_bset(r8a66597, HSE, SYSCFG0); /* High spd */
  706. r8a66597_mdfy(r8a66597, get_xtal_from_pdata(r8a66597->pdata),
  707. XTAL, SYSCFG0);
  708. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  709. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  710. r8a66597_bset(r8a66597, USBE, SYSCFG0);
  711. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  712. msleep(3);
  713. r8a66597_bset(r8a66597, PLLC, SYSCFG0);
  714. msleep(1);
  715. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  716. r8a66597_bset(r8a66597, irq_sense, INTENB1);
  717. r8a66597_write(r8a66597, BURST | CPU_ADR_RD_WR,
  718. DMA0CFG);
  719. }
  720. }
  721. static void disable_controller(struct r8a66597 *r8a66597)
  722. {
  723. if (r8a66597->pdata->on_chip) {
  724. r8a66597_bset(r8a66597, SCKE, SYSCFG0);
  725. r8a66597_bclr(r8a66597, UTST, TESTMODE);
  726. /* disable interrupts */
  727. r8a66597_write(r8a66597, 0, INTENB0);
  728. r8a66597_write(r8a66597, 0, INTENB1);
  729. r8a66597_write(r8a66597, 0, BRDYENB);
  730. r8a66597_write(r8a66597, 0, BEMPENB);
  731. r8a66597_write(r8a66597, 0, NRDYENB);
  732. /* clear status */
  733. r8a66597_write(r8a66597, 0, BRDYSTS);
  734. r8a66597_write(r8a66597, 0, NRDYSTS);
  735. r8a66597_write(r8a66597, 0, BEMPSTS);
  736. r8a66597_bclr(r8a66597, USBE, SYSCFG0);
  737. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  738. } else {
  739. r8a66597_bclr(r8a66597, UTST, TESTMODE);
  740. r8a66597_bclr(r8a66597, SCKE, SYSCFG0);
  741. udelay(1);
  742. r8a66597_bclr(r8a66597, PLLC, SYSCFG0);
  743. udelay(1);
  744. udelay(1);
  745. r8a66597_bclr(r8a66597, XCKE, SYSCFG0);
  746. }
  747. }
  748. static void r8a66597_start_xclock(struct r8a66597 *r8a66597)
  749. {
  750. u16 tmp;
  751. if (!r8a66597->pdata->on_chip) {
  752. tmp = r8a66597_read(r8a66597, SYSCFG0);
  753. if (!(tmp & XCKE))
  754. r8a66597_bset(r8a66597, XCKE, SYSCFG0);
  755. }
  756. }
  757. static struct r8a66597_request *get_request_from_ep(struct r8a66597_ep *ep)
  758. {
  759. return list_entry(ep->queue.next, struct r8a66597_request, queue);
  760. }
  761. /*-------------------------------------------------------------------------*/
  762. static void transfer_complete(struct r8a66597_ep *ep,
  763. struct r8a66597_request *req, int status)
  764. __releases(r8a66597->lock)
  765. __acquires(r8a66597->lock)
  766. {
  767. int restart = 0;
  768. if (unlikely(ep->pipenum == 0)) {
  769. if (ep->internal_ccpl) {
  770. ep->internal_ccpl = 0;
  771. return;
  772. }
  773. }
  774. list_del_init(&req->queue);
  775. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  776. req->req.status = -ESHUTDOWN;
  777. else
  778. req->req.status = status;
  779. if (!list_empty(&ep->queue))
  780. restart = 1;
  781. if (ep->use_dma)
  782. sudmac_free_channel(ep->r8a66597, ep, req);
  783. spin_unlock(&ep->r8a66597->lock);
  784. req->req.complete(&ep->ep, &req->req);
  785. spin_lock(&ep->r8a66597->lock);
  786. if (restart) {
  787. req = get_request_from_ep(ep);
  788. if (ep->desc)
  789. start_packet(ep, req);
  790. }
  791. }
  792. static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req)
  793. {
  794. int i;
  795. u16 tmp;
  796. unsigned bufsize;
  797. size_t size;
  798. void *buf;
  799. u16 pipenum = ep->pipenum;
  800. struct r8a66597 *r8a66597 = ep->r8a66597;
  801. pipe_change(r8a66597, pipenum);
  802. r8a66597_bset(r8a66597, ISEL, ep->fifosel);
  803. i = 0;
  804. do {
  805. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  806. if (i++ > 100000) {
  807. dev_err(r8a66597_to_dev(r8a66597),
  808. "pipe0 is busy. maybe cpu i/o bus "
  809. "conflict. please power off this controller.");
  810. return;
  811. }
  812. ndelay(1);
  813. } while ((tmp & FRDY) == 0);
  814. /* prepare parameters */
  815. bufsize = get_buffer_size(r8a66597, pipenum);
  816. buf = req->req.buf + req->req.actual;
  817. size = min(bufsize, req->req.length - req->req.actual);
  818. /* write fifo */
  819. if (req->req.buf) {
  820. if (size > 0)
  821. r8a66597_write_fifo(r8a66597, ep, buf, size);
  822. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  823. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  824. }
  825. /* update parameters */
  826. req->req.actual += size;
  827. /* check transfer finish */
  828. if ((!req->req.zero && (req->req.actual == req->req.length))
  829. || (size % ep->ep.maxpacket)
  830. || (size == 0)) {
  831. disable_irq_ready(r8a66597, pipenum);
  832. disable_irq_empty(r8a66597, pipenum);
  833. } else {
  834. disable_irq_ready(r8a66597, pipenum);
  835. enable_irq_empty(r8a66597, pipenum);
  836. }
  837. pipe_start(r8a66597, pipenum);
  838. }
  839. static void irq_packet_write(struct r8a66597_ep *ep,
  840. struct r8a66597_request *req)
  841. {
  842. u16 tmp;
  843. unsigned bufsize;
  844. size_t size;
  845. void *buf;
  846. u16 pipenum = ep->pipenum;
  847. struct r8a66597 *r8a66597 = ep->r8a66597;
  848. pipe_change(r8a66597, pipenum);
  849. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  850. if (unlikely((tmp & FRDY) == 0)) {
  851. pipe_stop(r8a66597, pipenum);
  852. pipe_irq_disable(r8a66597, pipenum);
  853. dev_err(r8a66597_to_dev(r8a66597),
  854. "write fifo not ready. pipnum=%d\n", pipenum);
  855. return;
  856. }
  857. /* prepare parameters */
  858. bufsize = get_buffer_size(r8a66597, pipenum);
  859. buf = req->req.buf + req->req.actual;
  860. size = min(bufsize, req->req.length - req->req.actual);
  861. /* write fifo */
  862. if (req->req.buf) {
  863. r8a66597_write_fifo(r8a66597, ep, buf, size);
  864. if ((size == 0)
  865. || ((size % ep->ep.maxpacket) != 0)
  866. || ((bufsize != ep->ep.maxpacket)
  867. && (bufsize > size)))
  868. r8a66597_bset(r8a66597, BVAL, ep->fifoctr);
  869. }
  870. /* update parameters */
  871. req->req.actual += size;
  872. /* check transfer finish */
  873. if ((!req->req.zero && (req->req.actual == req->req.length))
  874. || (size % ep->ep.maxpacket)
  875. || (size == 0)) {
  876. disable_irq_ready(r8a66597, pipenum);
  877. enable_irq_empty(r8a66597, pipenum);
  878. } else {
  879. disable_irq_empty(r8a66597, pipenum);
  880. pipe_irq_enable(r8a66597, pipenum);
  881. }
  882. }
  883. static void irq_packet_read(struct r8a66597_ep *ep,
  884. struct r8a66597_request *req)
  885. {
  886. u16 tmp;
  887. int rcv_len, bufsize, req_len;
  888. int size;
  889. void *buf;
  890. u16 pipenum = ep->pipenum;
  891. struct r8a66597 *r8a66597 = ep->r8a66597;
  892. int finish = 0;
  893. pipe_change(r8a66597, pipenum);
  894. tmp = r8a66597_read(r8a66597, ep->fifoctr);
  895. if (unlikely((tmp & FRDY) == 0)) {
  896. req->req.status = -EPIPE;
  897. pipe_stop(r8a66597, pipenum);
  898. pipe_irq_disable(r8a66597, pipenum);
  899. dev_err(r8a66597_to_dev(r8a66597), "read fifo not ready");
  900. return;
  901. }
  902. /* prepare parameters */
  903. rcv_len = tmp & DTLN;
  904. bufsize = get_buffer_size(r8a66597, pipenum);
  905. buf = req->req.buf + req->req.actual;
  906. req_len = req->req.length - req->req.actual;
  907. if (rcv_len < bufsize)
  908. size = min(rcv_len, req_len);
  909. else
  910. size = min(bufsize, req_len);
  911. /* update parameters */
  912. req->req.actual += size;
  913. /* check transfer finish */
  914. if ((!req->req.zero && (req->req.actual == req->req.length))
  915. || (size % ep->ep.maxpacket)
  916. || (size == 0)) {
  917. pipe_stop(r8a66597, pipenum);
  918. pipe_irq_disable(r8a66597, pipenum);
  919. finish = 1;
  920. }
  921. /* read fifo */
  922. if (req->req.buf) {
  923. if (size == 0)
  924. r8a66597_write(r8a66597, BCLR, ep->fifoctr);
  925. else
  926. r8a66597_read_fifo(r8a66597, ep->fifoaddr, buf, size);
  927. }
  928. if ((ep->pipenum != 0) && finish)
  929. transfer_complete(ep, req, 0);
  930. }
  931. static void irq_pipe_ready(struct r8a66597 *r8a66597, u16 status, u16 enb)
  932. {
  933. u16 check;
  934. u16 pipenum;
  935. struct r8a66597_ep *ep;
  936. struct r8a66597_request *req;
  937. if ((status & BRDY0) && (enb & BRDY0)) {
  938. r8a66597_write(r8a66597, ~BRDY0, BRDYSTS);
  939. r8a66597_mdfy(r8a66597, 0, CURPIPE, CFIFOSEL);
  940. ep = &r8a66597->ep[0];
  941. req = get_request_from_ep(ep);
  942. irq_packet_read(ep, req);
  943. } else {
  944. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  945. check = 1 << pipenum;
  946. if ((status & check) && (enb & check)) {
  947. r8a66597_write(r8a66597, ~check, BRDYSTS);
  948. ep = r8a66597->pipenum2ep[pipenum];
  949. req = get_request_from_ep(ep);
  950. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  951. irq_packet_write(ep, req);
  952. else
  953. irq_packet_read(ep, req);
  954. }
  955. }
  956. }
  957. }
  958. static void irq_pipe_empty(struct r8a66597 *r8a66597, u16 status, u16 enb)
  959. {
  960. u16 tmp;
  961. u16 check;
  962. u16 pipenum;
  963. struct r8a66597_ep *ep;
  964. struct r8a66597_request *req;
  965. if ((status & BEMP0) && (enb & BEMP0)) {
  966. r8a66597_write(r8a66597, ~BEMP0, BEMPSTS);
  967. ep = &r8a66597->ep[0];
  968. req = get_request_from_ep(ep);
  969. irq_ep0_write(ep, req);
  970. } else {
  971. for (pipenum = 1; pipenum < R8A66597_MAX_NUM_PIPE; pipenum++) {
  972. check = 1 << pipenum;
  973. if ((status & check) && (enb & check)) {
  974. r8a66597_write(r8a66597, ~check, BEMPSTS);
  975. tmp = control_reg_get(r8a66597, pipenum);
  976. if ((tmp & INBUFM) == 0) {
  977. disable_irq_empty(r8a66597, pipenum);
  978. pipe_irq_disable(r8a66597, pipenum);
  979. pipe_stop(r8a66597, pipenum);
  980. ep = r8a66597->pipenum2ep[pipenum];
  981. req = get_request_from_ep(ep);
  982. if (!list_empty(&ep->queue))
  983. transfer_complete(ep, req, 0);
  984. }
  985. }
  986. }
  987. }
  988. }
  989. static void get_status(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  990. __releases(r8a66597->lock)
  991. __acquires(r8a66597->lock)
  992. {
  993. struct r8a66597_ep *ep;
  994. u16 pid;
  995. u16 status = 0;
  996. u16 w_index = le16_to_cpu(ctrl->wIndex);
  997. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  998. case USB_RECIP_DEVICE:
  999. status = 1 << USB_DEVICE_SELF_POWERED;
  1000. break;
  1001. case USB_RECIP_INTERFACE:
  1002. status = 0;
  1003. break;
  1004. case USB_RECIP_ENDPOINT:
  1005. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  1006. pid = control_reg_get_pid(r8a66597, ep->pipenum);
  1007. if (pid == PID_STALL)
  1008. status = 1 << USB_ENDPOINT_HALT;
  1009. else
  1010. status = 0;
  1011. break;
  1012. default:
  1013. pipe_stall(r8a66597, 0);
  1014. return; /* exit */
  1015. }
  1016. r8a66597->ep0_data = cpu_to_le16(status);
  1017. r8a66597->ep0_req->buf = &r8a66597->ep0_data;
  1018. r8a66597->ep0_req->length = 2;
  1019. /* AV: what happens if we get called again before that gets through? */
  1020. spin_unlock(&r8a66597->lock);
  1021. r8a66597_queue(r8a66597->gadget.ep0, r8a66597->ep0_req, GFP_KERNEL);
  1022. spin_lock(&r8a66597->lock);
  1023. }
  1024. static void clear_feature(struct r8a66597 *r8a66597,
  1025. struct usb_ctrlrequest *ctrl)
  1026. {
  1027. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  1028. case USB_RECIP_DEVICE:
  1029. control_end(r8a66597, 1);
  1030. break;
  1031. case USB_RECIP_INTERFACE:
  1032. control_end(r8a66597, 1);
  1033. break;
  1034. case USB_RECIP_ENDPOINT: {
  1035. struct r8a66597_ep *ep;
  1036. struct r8a66597_request *req;
  1037. u16 w_index = le16_to_cpu(ctrl->wIndex);
  1038. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  1039. if (!ep->wedge) {
  1040. pipe_stop(r8a66597, ep->pipenum);
  1041. control_reg_sqclr(r8a66597, ep->pipenum);
  1042. spin_unlock(&r8a66597->lock);
  1043. usb_ep_clear_halt(&ep->ep);
  1044. spin_lock(&r8a66597->lock);
  1045. }
  1046. control_end(r8a66597, 1);
  1047. req = get_request_from_ep(ep);
  1048. if (ep->busy) {
  1049. ep->busy = 0;
  1050. if (list_empty(&ep->queue))
  1051. break;
  1052. start_packet(ep, req);
  1053. } else if (!list_empty(&ep->queue))
  1054. pipe_start(r8a66597, ep->pipenum);
  1055. }
  1056. break;
  1057. default:
  1058. pipe_stall(r8a66597, 0);
  1059. break;
  1060. }
  1061. }
  1062. static void set_feature(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  1063. {
  1064. u16 tmp;
  1065. int timeout = 3000;
  1066. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  1067. case USB_RECIP_DEVICE:
  1068. switch (le16_to_cpu(ctrl->wValue)) {
  1069. case USB_DEVICE_TEST_MODE:
  1070. control_end(r8a66597, 1);
  1071. /* Wait for the completion of status stage */
  1072. do {
  1073. tmp = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
  1074. udelay(1);
  1075. } while (tmp != CS_IDST || timeout-- > 0);
  1076. if (tmp == CS_IDST)
  1077. r8a66597_bset(r8a66597,
  1078. le16_to_cpu(ctrl->wIndex >> 8),
  1079. TESTMODE);
  1080. break;
  1081. default:
  1082. pipe_stall(r8a66597, 0);
  1083. break;
  1084. }
  1085. break;
  1086. case USB_RECIP_INTERFACE:
  1087. control_end(r8a66597, 1);
  1088. break;
  1089. case USB_RECIP_ENDPOINT: {
  1090. struct r8a66597_ep *ep;
  1091. u16 w_index = le16_to_cpu(ctrl->wIndex);
  1092. ep = r8a66597->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  1093. pipe_stall(r8a66597, ep->pipenum);
  1094. control_end(r8a66597, 1);
  1095. }
  1096. break;
  1097. default:
  1098. pipe_stall(r8a66597, 0);
  1099. break;
  1100. }
  1101. }
  1102. /* if return value is true, call class driver's setup() */
  1103. static int setup_packet(struct r8a66597 *r8a66597, struct usb_ctrlrequest *ctrl)
  1104. {
  1105. u16 *p = (u16 *)ctrl;
  1106. unsigned long offset = USBREQ;
  1107. int i, ret = 0;
  1108. /* read fifo */
  1109. r8a66597_write(r8a66597, ~VALID, INTSTS0);
  1110. for (i = 0; i < 4; i++)
  1111. p[i] = r8a66597_read(r8a66597, offset + i*2);
  1112. /* check request */
  1113. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  1114. switch (ctrl->bRequest) {
  1115. case USB_REQ_GET_STATUS:
  1116. get_status(r8a66597, ctrl);
  1117. break;
  1118. case USB_REQ_CLEAR_FEATURE:
  1119. clear_feature(r8a66597, ctrl);
  1120. break;
  1121. case USB_REQ_SET_FEATURE:
  1122. set_feature(r8a66597, ctrl);
  1123. break;
  1124. default:
  1125. ret = 1;
  1126. break;
  1127. }
  1128. } else
  1129. ret = 1;
  1130. return ret;
  1131. }
  1132. static void r8a66597_update_usb_speed(struct r8a66597 *r8a66597)
  1133. {
  1134. u16 speed = get_usb_speed(r8a66597);
  1135. switch (speed) {
  1136. case HSMODE:
  1137. r8a66597->gadget.speed = USB_SPEED_HIGH;
  1138. break;
  1139. case FSMODE:
  1140. r8a66597->gadget.speed = USB_SPEED_FULL;
  1141. break;
  1142. default:
  1143. r8a66597->gadget.speed = USB_SPEED_UNKNOWN;
  1144. dev_err(r8a66597_to_dev(r8a66597), "USB speed unknown\n");
  1145. }
  1146. }
  1147. static void irq_device_state(struct r8a66597 *r8a66597)
  1148. {
  1149. u16 dvsq;
  1150. dvsq = r8a66597_read(r8a66597, INTSTS0) & DVSQ;
  1151. r8a66597_write(r8a66597, ~DVST, INTSTS0);
  1152. if (dvsq == DS_DFLT) {
  1153. /* bus reset */
  1154. spin_unlock(&r8a66597->lock);
  1155. r8a66597->driver->disconnect(&r8a66597->gadget);
  1156. spin_lock(&r8a66597->lock);
  1157. r8a66597_update_usb_speed(r8a66597);
  1158. }
  1159. if (r8a66597->old_dvsq == DS_CNFG && dvsq != DS_CNFG)
  1160. r8a66597_update_usb_speed(r8a66597);
  1161. if ((dvsq == DS_CNFG || dvsq == DS_ADDS)
  1162. && r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  1163. r8a66597_update_usb_speed(r8a66597);
  1164. r8a66597->old_dvsq = dvsq;
  1165. }
  1166. static void irq_control_stage(struct r8a66597 *r8a66597)
  1167. __releases(r8a66597->lock)
  1168. __acquires(r8a66597->lock)
  1169. {
  1170. struct usb_ctrlrequest ctrl;
  1171. u16 ctsq;
  1172. ctsq = r8a66597_read(r8a66597, INTSTS0) & CTSQ;
  1173. r8a66597_write(r8a66597, ~CTRT, INTSTS0);
  1174. switch (ctsq) {
  1175. case CS_IDST: {
  1176. struct r8a66597_ep *ep;
  1177. struct r8a66597_request *req;
  1178. ep = &r8a66597->ep[0];
  1179. req = get_request_from_ep(ep);
  1180. transfer_complete(ep, req, 0);
  1181. }
  1182. break;
  1183. case CS_RDDS:
  1184. case CS_WRDS:
  1185. case CS_WRND:
  1186. if (setup_packet(r8a66597, &ctrl)) {
  1187. spin_unlock(&r8a66597->lock);
  1188. if (r8a66597->driver->setup(&r8a66597->gadget, &ctrl)
  1189. < 0)
  1190. pipe_stall(r8a66597, 0);
  1191. spin_lock(&r8a66597->lock);
  1192. }
  1193. break;
  1194. case CS_RDSS:
  1195. case CS_WRSS:
  1196. control_end(r8a66597, 0);
  1197. break;
  1198. default:
  1199. dev_err(r8a66597_to_dev(r8a66597),
  1200. "ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  1201. break;
  1202. }
  1203. }
  1204. static void sudmac_finish(struct r8a66597 *r8a66597, struct r8a66597_ep *ep)
  1205. {
  1206. u16 pipenum;
  1207. struct r8a66597_request *req;
  1208. u32 len;
  1209. int i = 0;
  1210. pipenum = ep->pipenum;
  1211. pipe_change(r8a66597, pipenum);
  1212. while (!(r8a66597_read(r8a66597, ep->fifoctr) & FRDY)) {
  1213. udelay(1);
  1214. if (unlikely(i++ >= 10000)) { /* timeout = 10 msec */
  1215. dev_err(r8a66597_to_dev(r8a66597),
  1216. "%s: FRDY was not set (%d)\n",
  1217. __func__, pipenum);
  1218. return;
  1219. }
  1220. }
  1221. r8a66597_bset(r8a66597, BCLR, ep->fifoctr);
  1222. req = get_request_from_ep(ep);
  1223. /* prepare parameters */
  1224. len = r8a66597_sudmac_read(r8a66597, CH0CBC);
  1225. req->req.actual += len;
  1226. /* clear */
  1227. r8a66597_sudmac_write(r8a66597, CH0STCLR, DSTSCLR);
  1228. /* check transfer finish */
  1229. if ((!req->req.zero && (req->req.actual == req->req.length))
  1230. || (len % ep->ep.maxpacket)) {
  1231. if (ep->dma->dir) {
  1232. disable_irq_ready(r8a66597, pipenum);
  1233. enable_irq_empty(r8a66597, pipenum);
  1234. } else {
  1235. /* Clear the interrupt flag for next transfer */
  1236. r8a66597_write(r8a66597, ~(1 << pipenum), BRDYSTS);
  1237. transfer_complete(ep, req, 0);
  1238. }
  1239. }
  1240. }
  1241. static void r8a66597_sudmac_irq(struct r8a66597 *r8a66597)
  1242. {
  1243. u32 irqsts;
  1244. struct r8a66597_ep *ep;
  1245. u16 pipenum;
  1246. irqsts = r8a66597_sudmac_read(r8a66597, DINTSTS);
  1247. if (irqsts & CH0ENDS) {
  1248. r8a66597_sudmac_write(r8a66597, CH0ENDC, DINTSTSCLR);
  1249. pipenum = (r8a66597_read(r8a66597, D0FIFOSEL) & CURPIPE);
  1250. ep = r8a66597->pipenum2ep[pipenum];
  1251. sudmac_finish(r8a66597, ep);
  1252. }
  1253. }
  1254. static irqreturn_t r8a66597_irq(int irq, void *_r8a66597)
  1255. {
  1256. struct r8a66597 *r8a66597 = _r8a66597;
  1257. u16 intsts0;
  1258. u16 intenb0;
  1259. u16 brdysts, nrdysts, bempsts;
  1260. u16 brdyenb, nrdyenb, bempenb;
  1261. u16 savepipe;
  1262. u16 mask0;
  1263. if (r8a66597_is_sudmac(r8a66597))
  1264. r8a66597_sudmac_irq(r8a66597);
  1265. spin_lock(&r8a66597->lock);
  1266. intsts0 = r8a66597_read(r8a66597, INTSTS0);
  1267. intenb0 = r8a66597_read(r8a66597, INTENB0);
  1268. savepipe = r8a66597_read(r8a66597, CFIFOSEL);
  1269. mask0 = intsts0 & intenb0;
  1270. if (mask0) {
  1271. brdysts = r8a66597_read(r8a66597, BRDYSTS);
  1272. nrdysts = r8a66597_read(r8a66597, NRDYSTS);
  1273. bempsts = r8a66597_read(r8a66597, BEMPSTS);
  1274. brdyenb = r8a66597_read(r8a66597, BRDYENB);
  1275. nrdyenb = r8a66597_read(r8a66597, NRDYENB);
  1276. bempenb = r8a66597_read(r8a66597, BEMPENB);
  1277. if (mask0 & VBINT) {
  1278. r8a66597_write(r8a66597, 0xffff & ~VBINT,
  1279. INTSTS0);
  1280. r8a66597_start_xclock(r8a66597);
  1281. /* start vbus sampling */
  1282. r8a66597->old_vbus = r8a66597_read(r8a66597, INTSTS0)
  1283. & VBSTS;
  1284. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1285. mod_timer(&r8a66597->timer,
  1286. jiffies + msecs_to_jiffies(50));
  1287. }
  1288. if (intsts0 & DVSQ)
  1289. irq_device_state(r8a66597);
  1290. if ((intsts0 & BRDY) && (intenb0 & BRDYE)
  1291. && (brdysts & brdyenb))
  1292. irq_pipe_ready(r8a66597, brdysts, brdyenb);
  1293. if ((intsts0 & BEMP) && (intenb0 & BEMPE)
  1294. && (bempsts & bempenb))
  1295. irq_pipe_empty(r8a66597, bempsts, bempenb);
  1296. if (intsts0 & CTRT)
  1297. irq_control_stage(r8a66597);
  1298. }
  1299. r8a66597_write(r8a66597, savepipe, CFIFOSEL);
  1300. spin_unlock(&r8a66597->lock);
  1301. return IRQ_HANDLED;
  1302. }
  1303. static void r8a66597_timer(unsigned long _r8a66597)
  1304. {
  1305. struct r8a66597 *r8a66597 = (struct r8a66597 *)_r8a66597;
  1306. unsigned long flags;
  1307. u16 tmp;
  1308. spin_lock_irqsave(&r8a66597->lock, flags);
  1309. tmp = r8a66597_read(r8a66597, SYSCFG0);
  1310. if (r8a66597->scount > 0) {
  1311. tmp = r8a66597_read(r8a66597, INTSTS0) & VBSTS;
  1312. if (tmp == r8a66597->old_vbus) {
  1313. r8a66597->scount--;
  1314. if (r8a66597->scount == 0) {
  1315. if (tmp == VBSTS)
  1316. r8a66597_usb_connect(r8a66597);
  1317. else
  1318. r8a66597_usb_disconnect(r8a66597);
  1319. } else {
  1320. mod_timer(&r8a66597->timer,
  1321. jiffies + msecs_to_jiffies(50));
  1322. }
  1323. } else {
  1324. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1325. r8a66597->old_vbus = tmp;
  1326. mod_timer(&r8a66597->timer,
  1327. jiffies + msecs_to_jiffies(50));
  1328. }
  1329. }
  1330. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1331. }
  1332. /*-------------------------------------------------------------------------*/
  1333. static int r8a66597_enable(struct usb_ep *_ep,
  1334. const struct usb_endpoint_descriptor *desc)
  1335. {
  1336. struct r8a66597_ep *ep;
  1337. ep = container_of(_ep, struct r8a66597_ep, ep);
  1338. return alloc_pipe_config(ep, desc);
  1339. }
  1340. static int r8a66597_disable(struct usb_ep *_ep)
  1341. {
  1342. struct r8a66597_ep *ep;
  1343. struct r8a66597_request *req;
  1344. unsigned long flags;
  1345. ep = container_of(_ep, struct r8a66597_ep, ep);
  1346. BUG_ON(!ep);
  1347. while (!list_empty(&ep->queue)) {
  1348. req = get_request_from_ep(ep);
  1349. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1350. transfer_complete(ep, req, -ECONNRESET);
  1351. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1352. }
  1353. pipe_irq_disable(ep->r8a66597, ep->pipenum);
  1354. return free_pipe_config(ep);
  1355. }
  1356. static struct usb_request *r8a66597_alloc_request(struct usb_ep *_ep,
  1357. gfp_t gfp_flags)
  1358. {
  1359. struct r8a66597_request *req;
  1360. req = kzalloc(sizeof(struct r8a66597_request), gfp_flags);
  1361. if (!req)
  1362. return NULL;
  1363. INIT_LIST_HEAD(&req->queue);
  1364. return &req->req;
  1365. }
  1366. static void r8a66597_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1367. {
  1368. struct r8a66597_request *req;
  1369. req = container_of(_req, struct r8a66597_request, req);
  1370. kfree(req);
  1371. }
  1372. static int r8a66597_queue(struct usb_ep *_ep, struct usb_request *_req,
  1373. gfp_t gfp_flags)
  1374. {
  1375. struct r8a66597_ep *ep;
  1376. struct r8a66597_request *req;
  1377. unsigned long flags;
  1378. int request = 0;
  1379. ep = container_of(_ep, struct r8a66597_ep, ep);
  1380. req = container_of(_req, struct r8a66597_request, req);
  1381. if (ep->r8a66597->gadget.speed == USB_SPEED_UNKNOWN)
  1382. return -ESHUTDOWN;
  1383. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1384. if (list_empty(&ep->queue))
  1385. request = 1;
  1386. list_add_tail(&req->queue, &ep->queue);
  1387. req->req.actual = 0;
  1388. req->req.status = -EINPROGRESS;
  1389. if (ep->desc == NULL) /* control */
  1390. start_ep0(ep, req);
  1391. else {
  1392. if (request && !ep->busy)
  1393. start_packet(ep, req);
  1394. }
  1395. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1396. return 0;
  1397. }
  1398. static int r8a66597_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1399. {
  1400. struct r8a66597_ep *ep;
  1401. struct r8a66597_request *req;
  1402. unsigned long flags;
  1403. ep = container_of(_ep, struct r8a66597_ep, ep);
  1404. req = container_of(_req, struct r8a66597_request, req);
  1405. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1406. if (!list_empty(&ep->queue))
  1407. transfer_complete(ep, req, -ECONNRESET);
  1408. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1409. return 0;
  1410. }
  1411. static int r8a66597_set_halt(struct usb_ep *_ep, int value)
  1412. {
  1413. struct r8a66597_ep *ep;
  1414. struct r8a66597_request *req;
  1415. unsigned long flags;
  1416. int ret = 0;
  1417. ep = container_of(_ep, struct r8a66597_ep, ep);
  1418. req = get_request_from_ep(ep);
  1419. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1420. if (!list_empty(&ep->queue)) {
  1421. ret = -EAGAIN;
  1422. goto out;
  1423. }
  1424. if (value) {
  1425. ep->busy = 1;
  1426. pipe_stall(ep->r8a66597, ep->pipenum);
  1427. } else {
  1428. ep->busy = 0;
  1429. ep->wedge = 0;
  1430. pipe_stop(ep->r8a66597, ep->pipenum);
  1431. }
  1432. out:
  1433. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1434. return ret;
  1435. }
  1436. static int r8a66597_set_wedge(struct usb_ep *_ep)
  1437. {
  1438. struct r8a66597_ep *ep;
  1439. unsigned long flags;
  1440. ep = container_of(_ep, struct r8a66597_ep, ep);
  1441. if (!ep || !ep->desc)
  1442. return -EINVAL;
  1443. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1444. ep->wedge = 1;
  1445. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1446. return usb_ep_set_halt(_ep);
  1447. }
  1448. static void r8a66597_fifo_flush(struct usb_ep *_ep)
  1449. {
  1450. struct r8a66597_ep *ep;
  1451. unsigned long flags;
  1452. ep = container_of(_ep, struct r8a66597_ep, ep);
  1453. spin_lock_irqsave(&ep->r8a66597->lock, flags);
  1454. if (list_empty(&ep->queue) && !ep->busy) {
  1455. pipe_stop(ep->r8a66597, ep->pipenum);
  1456. r8a66597_bclr(ep->r8a66597, BCLR, ep->fifoctr);
  1457. r8a66597_write(ep->r8a66597, ACLRM, ep->pipectr);
  1458. r8a66597_write(ep->r8a66597, 0, ep->pipectr);
  1459. }
  1460. spin_unlock_irqrestore(&ep->r8a66597->lock, flags);
  1461. }
  1462. static struct usb_ep_ops r8a66597_ep_ops = {
  1463. .enable = r8a66597_enable,
  1464. .disable = r8a66597_disable,
  1465. .alloc_request = r8a66597_alloc_request,
  1466. .free_request = r8a66597_free_request,
  1467. .queue = r8a66597_queue,
  1468. .dequeue = r8a66597_dequeue,
  1469. .set_halt = r8a66597_set_halt,
  1470. .set_wedge = r8a66597_set_wedge,
  1471. .fifo_flush = r8a66597_fifo_flush,
  1472. };
  1473. /*-------------------------------------------------------------------------*/
  1474. static int r8a66597_start(struct usb_gadget *gadget,
  1475. struct usb_gadget_driver *driver)
  1476. {
  1477. struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
  1478. if (!driver
  1479. || driver->max_speed < USB_SPEED_HIGH
  1480. || !driver->setup)
  1481. return -EINVAL;
  1482. if (!r8a66597)
  1483. return -ENODEV;
  1484. /* hook up the driver */
  1485. r8a66597->driver = driver;
  1486. init_controller(r8a66597);
  1487. r8a66597_bset(r8a66597, VBSE, INTENB0);
  1488. if (r8a66597_read(r8a66597, INTSTS0) & VBSTS) {
  1489. r8a66597_start_xclock(r8a66597);
  1490. /* start vbus sampling */
  1491. r8a66597->old_vbus = r8a66597_read(r8a66597,
  1492. INTSTS0) & VBSTS;
  1493. r8a66597->scount = R8A66597_MAX_SAMPLING;
  1494. mod_timer(&r8a66597->timer, jiffies + msecs_to_jiffies(50));
  1495. }
  1496. return 0;
  1497. }
  1498. static int r8a66597_stop(struct usb_gadget *gadget,
  1499. struct usb_gadget_driver *driver)
  1500. {
  1501. struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
  1502. unsigned long flags;
  1503. spin_lock_irqsave(&r8a66597->lock, flags);
  1504. r8a66597_bclr(r8a66597, VBSE, INTENB0);
  1505. disable_controller(r8a66597);
  1506. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1507. r8a66597->driver = NULL;
  1508. return 0;
  1509. }
  1510. /*-------------------------------------------------------------------------*/
  1511. static int r8a66597_get_frame(struct usb_gadget *_gadget)
  1512. {
  1513. struct r8a66597 *r8a66597 = gadget_to_r8a66597(_gadget);
  1514. return r8a66597_read(r8a66597, FRMNUM) & 0x03FF;
  1515. }
  1516. static int r8a66597_pullup(struct usb_gadget *gadget, int is_on)
  1517. {
  1518. struct r8a66597 *r8a66597 = gadget_to_r8a66597(gadget);
  1519. unsigned long flags;
  1520. spin_lock_irqsave(&r8a66597->lock, flags);
  1521. if (is_on)
  1522. r8a66597_bset(r8a66597, DPRPU, SYSCFG0);
  1523. else
  1524. r8a66597_bclr(r8a66597, DPRPU, SYSCFG0);
  1525. spin_unlock_irqrestore(&r8a66597->lock, flags);
  1526. return 0;
  1527. }
  1528. static struct usb_gadget_ops r8a66597_gadget_ops = {
  1529. .get_frame = r8a66597_get_frame,
  1530. .udc_start = r8a66597_start,
  1531. .udc_stop = r8a66597_stop,
  1532. .pullup = r8a66597_pullup,
  1533. };
  1534. static int __exit r8a66597_remove(struct platform_device *pdev)
  1535. {
  1536. struct r8a66597 *r8a66597 = dev_get_drvdata(&pdev->dev);
  1537. usb_del_gadget_udc(&r8a66597->gadget);
  1538. del_timer_sync(&r8a66597->timer);
  1539. iounmap(r8a66597->reg);
  1540. if (r8a66597->pdata->sudmac)
  1541. iounmap(r8a66597->sudmac_reg);
  1542. free_irq(platform_get_irq(pdev, 0), r8a66597);
  1543. r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
  1544. #ifdef CONFIG_HAVE_CLK
  1545. if (r8a66597->pdata->on_chip) {
  1546. clk_disable(r8a66597->clk);
  1547. clk_put(r8a66597->clk);
  1548. }
  1549. #endif
  1550. device_unregister(&r8a66597->gadget.dev);
  1551. kfree(r8a66597);
  1552. return 0;
  1553. }
  1554. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1555. {
  1556. }
  1557. static int __init r8a66597_sudmac_ioremap(struct r8a66597 *r8a66597,
  1558. struct platform_device *pdev)
  1559. {
  1560. struct resource *res;
  1561. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sudmac");
  1562. if (!res) {
  1563. dev_err(&pdev->dev, "platform_get_resource error(sudmac).\n");
  1564. return -ENODEV;
  1565. }
  1566. r8a66597->sudmac_reg = ioremap(res->start, resource_size(res));
  1567. if (r8a66597->sudmac_reg == NULL) {
  1568. dev_err(&pdev->dev, "ioremap error(sudmac).\n");
  1569. return -ENOMEM;
  1570. }
  1571. return 0;
  1572. }
  1573. static int __init r8a66597_probe(struct platform_device *pdev)
  1574. {
  1575. #ifdef CONFIG_HAVE_CLK
  1576. char clk_name[8];
  1577. #endif
  1578. struct resource *res, *ires;
  1579. int irq;
  1580. void __iomem *reg = NULL;
  1581. struct r8a66597 *r8a66597 = NULL;
  1582. int ret = 0;
  1583. int i;
  1584. unsigned long irq_trigger;
  1585. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1586. if (!res) {
  1587. ret = -ENODEV;
  1588. dev_err(&pdev->dev, "platform_get_resource error.\n");
  1589. goto clean_up;
  1590. }
  1591. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1592. irq = ires->start;
  1593. irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
  1594. if (irq < 0) {
  1595. ret = -ENODEV;
  1596. dev_err(&pdev->dev, "platform_get_irq error.\n");
  1597. goto clean_up;
  1598. }
  1599. reg = ioremap(res->start, resource_size(res));
  1600. if (reg == NULL) {
  1601. ret = -ENOMEM;
  1602. dev_err(&pdev->dev, "ioremap error.\n");
  1603. goto clean_up;
  1604. }
  1605. /* initialize ucd */
  1606. r8a66597 = kzalloc(sizeof(struct r8a66597), GFP_KERNEL);
  1607. if (r8a66597 == NULL) {
  1608. ret = -ENOMEM;
  1609. dev_err(&pdev->dev, "kzalloc error\n");
  1610. goto clean_up;
  1611. }
  1612. spin_lock_init(&r8a66597->lock);
  1613. dev_set_drvdata(&pdev->dev, r8a66597);
  1614. r8a66597->pdata = pdev->dev.platform_data;
  1615. r8a66597->irq_sense_low = irq_trigger == IRQF_TRIGGER_LOW;
  1616. r8a66597->gadget.ops = &r8a66597_gadget_ops;
  1617. dev_set_name(&r8a66597->gadget.dev, "gadget");
  1618. r8a66597->gadget.max_speed = USB_SPEED_HIGH;
  1619. r8a66597->gadget.dev.parent = &pdev->dev;
  1620. r8a66597->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1621. r8a66597->gadget.dev.release = pdev->dev.release;
  1622. r8a66597->gadget.name = udc_name;
  1623. ret = device_register(&r8a66597->gadget.dev);
  1624. if (ret < 0) {
  1625. dev_err(&pdev->dev, "device_register failed\n");
  1626. goto clean_up;
  1627. }
  1628. init_timer(&r8a66597->timer);
  1629. r8a66597->timer.function = r8a66597_timer;
  1630. r8a66597->timer.data = (unsigned long)r8a66597;
  1631. r8a66597->reg = reg;
  1632. #ifdef CONFIG_HAVE_CLK
  1633. if (r8a66597->pdata->on_chip) {
  1634. snprintf(clk_name, sizeof(clk_name), "usb%d", pdev->id);
  1635. r8a66597->clk = clk_get(&pdev->dev, clk_name);
  1636. if (IS_ERR(r8a66597->clk)) {
  1637. dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
  1638. clk_name);
  1639. ret = PTR_ERR(r8a66597->clk);
  1640. goto clean_up_dev;
  1641. }
  1642. clk_enable(r8a66597->clk);
  1643. }
  1644. #endif
  1645. if (r8a66597->pdata->sudmac) {
  1646. ret = r8a66597_sudmac_ioremap(r8a66597, pdev);
  1647. if (ret < 0)
  1648. goto clean_up2;
  1649. }
  1650. disable_controller(r8a66597); /* make sure controller is disabled */
  1651. ret = request_irq(irq, r8a66597_irq, IRQF_SHARED,
  1652. udc_name, r8a66597);
  1653. if (ret < 0) {
  1654. dev_err(&pdev->dev, "request_irq error (%d)\n", ret);
  1655. goto clean_up2;
  1656. }
  1657. INIT_LIST_HEAD(&r8a66597->gadget.ep_list);
  1658. r8a66597->gadget.ep0 = &r8a66597->ep[0].ep;
  1659. INIT_LIST_HEAD(&r8a66597->gadget.ep0->ep_list);
  1660. for (i = 0; i < R8A66597_MAX_NUM_PIPE; i++) {
  1661. struct r8a66597_ep *ep = &r8a66597->ep[i];
  1662. if (i != 0) {
  1663. INIT_LIST_HEAD(&r8a66597->ep[i].ep.ep_list);
  1664. list_add_tail(&r8a66597->ep[i].ep.ep_list,
  1665. &r8a66597->gadget.ep_list);
  1666. }
  1667. ep->r8a66597 = r8a66597;
  1668. INIT_LIST_HEAD(&ep->queue);
  1669. ep->ep.name = r8a66597_ep_name[i];
  1670. ep->ep.ops = &r8a66597_ep_ops;
  1671. ep->ep.maxpacket = 512;
  1672. }
  1673. r8a66597->ep[0].ep.maxpacket = 64;
  1674. r8a66597->ep[0].pipenum = 0;
  1675. r8a66597->ep[0].fifoaddr = CFIFO;
  1676. r8a66597->ep[0].fifosel = CFIFOSEL;
  1677. r8a66597->ep[0].fifoctr = CFIFOCTR;
  1678. r8a66597->ep[0].pipectr = get_pipectr_addr(0);
  1679. r8a66597->pipenum2ep[0] = &r8a66597->ep[0];
  1680. r8a66597->epaddr2ep[0] = &r8a66597->ep[0];
  1681. r8a66597->ep0_req = r8a66597_alloc_request(&r8a66597->ep[0].ep,
  1682. GFP_KERNEL);
  1683. if (r8a66597->ep0_req == NULL)
  1684. goto clean_up3;
  1685. r8a66597->ep0_req->complete = nop_completion;
  1686. ret = usb_add_gadget_udc(&pdev->dev, &r8a66597->gadget);
  1687. if (ret)
  1688. goto err_add_udc;
  1689. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1690. return 0;
  1691. err_add_udc:
  1692. r8a66597_free_request(&r8a66597->ep[0].ep, r8a66597->ep0_req);
  1693. clean_up3:
  1694. free_irq(irq, r8a66597);
  1695. clean_up2:
  1696. #ifdef CONFIG_HAVE_CLK
  1697. if (r8a66597->pdata->on_chip) {
  1698. clk_disable(r8a66597->clk);
  1699. clk_put(r8a66597->clk);
  1700. }
  1701. clean_up_dev:
  1702. #endif
  1703. device_unregister(&r8a66597->gadget.dev);
  1704. clean_up:
  1705. if (r8a66597) {
  1706. if (r8a66597->sudmac_reg)
  1707. iounmap(r8a66597->sudmac_reg);
  1708. if (r8a66597->ep0_req)
  1709. r8a66597_free_request(&r8a66597->ep[0].ep,
  1710. r8a66597->ep0_req);
  1711. kfree(r8a66597);
  1712. }
  1713. if (reg)
  1714. iounmap(reg);
  1715. return ret;
  1716. }
  1717. /*-------------------------------------------------------------------------*/
  1718. static struct platform_driver r8a66597_driver = {
  1719. .remove = __exit_p(r8a66597_remove),
  1720. .driver = {
  1721. .name = (char *) udc_name,
  1722. },
  1723. };
  1724. MODULE_ALIAS("platform:r8a66597_udc");
  1725. static int __init r8a66597_udc_init(void)
  1726. {
  1727. return platform_driver_probe(&r8a66597_driver, r8a66597_probe);
  1728. }
  1729. module_init(r8a66597_udc_init);
  1730. static void __exit r8a66597_udc_cleanup(void)
  1731. {
  1732. platform_driver_unregister(&r8a66597_driver);
  1733. }
  1734. module_exit(r8a66597_udc_cleanup);
  1735. MODULE_DESCRIPTION("R8A66597 USB gadget driver");
  1736. MODULE_LICENSE("GPL");
  1737. MODULE_AUTHOR("Yoshihiro Shimoda");