omap-serial.c 44 KB

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  1. /*
  2. * Driver for OMAP-UART controller.
  3. * Based on drivers/serial/8250.c
  4. *
  5. * Copyright (C) 2010 Texas Instruments.
  6. *
  7. * Authors:
  8. * Govindraj R <govindraj.raja@ti.com>
  9. * Thara Gopinath <thara@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * Note: This driver is made separate from 8250 driver as we cannot
  17. * over load 8250 driver with omap platform specific configuration for
  18. * features like DMA, it makes easier to implement features like DMA and
  19. * hardware flow control and software flow control configuration with
  20. * this driver as required for the omap-platform.
  21. */
  22. #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  23. #define SUPPORT_SYSRQ
  24. #endif
  25. #include <linux/module.h>
  26. #include <linux/init.h>
  27. #include <linux/console.h>
  28. #include <linux/serial_reg.h>
  29. #include <linux/delay.h>
  30. #include <linux/slab.h>
  31. #include <linux/tty.h>
  32. #include <linux/tty_flip.h>
  33. #include <linux/io.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/clk.h>
  36. #include <linux/serial_core.h>
  37. #include <linux/irq.h>
  38. #include <linux/pm_runtime.h>
  39. #include <linux/of.h>
  40. #include <plat/dma.h>
  41. #include <plat/dmtimer.h>
  42. #include <plat/omap-serial.h>
  43. #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  44. static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
  45. /* Forward declaration of functions */
  46. static void uart_tx_dma_callback(int lch, u16 ch_status, void *data);
  47. static void serial_omap_rxdma_poll(unsigned long uart_no);
  48. static int serial_omap_start_rxdma(struct uart_omap_port *up);
  49. static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
  50. static struct workqueue_struct *serial_omap_uart_wq;
  51. static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
  52. {
  53. offset <<= up->port.regshift;
  54. return readw(up->port.membase + offset);
  55. }
  56. static inline void serial_out(struct uart_omap_port *up, int offset, int value)
  57. {
  58. offset <<= up->port.regshift;
  59. writew(value, up->port.membase + offset);
  60. }
  61. static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
  62. {
  63. serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
  64. serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
  65. UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
  66. serial_out(up, UART_FCR, 0);
  67. }
  68. /*
  69. * serial_omap_get_divisor - calculate divisor value
  70. * @port: uart port info
  71. * @baud: baudrate for which divisor needs to be calculated.
  72. *
  73. * We have written our own function to get the divisor so as to support
  74. * 13x mode. 3Mbps Baudrate as an different divisor.
  75. * Reference OMAP TRM Chapter 17:
  76. * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
  77. * referring to oversampling - divisor value
  78. * baudrate 460,800 to 3,686,400 all have divisor 13
  79. * except 3,000,000 which has divisor value 16
  80. */
  81. static unsigned int
  82. serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
  83. {
  84. unsigned int divisor;
  85. if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
  86. divisor = 13;
  87. else
  88. divisor = 16;
  89. return port->uartclk/(baud * divisor);
  90. }
  91. static void serial_omap_stop_rxdma(struct uart_omap_port *up)
  92. {
  93. if (up->uart_dma.rx_dma_used) {
  94. del_timer(&up->uart_dma.rx_timer);
  95. omap_stop_dma(up->uart_dma.rx_dma_channel);
  96. omap_free_dma(up->uart_dma.rx_dma_channel);
  97. up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
  98. up->uart_dma.rx_dma_used = false;
  99. pm_runtime_mark_last_busy(&up->pdev->dev);
  100. pm_runtime_put_autosuspend(&up->pdev->dev);
  101. }
  102. }
  103. static void serial_omap_enable_ms(struct uart_port *port)
  104. {
  105. struct uart_omap_port *up = (struct uart_omap_port *)port;
  106. dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
  107. pm_runtime_get_sync(&up->pdev->dev);
  108. up->ier |= UART_IER_MSI;
  109. serial_out(up, UART_IER, up->ier);
  110. pm_runtime_put(&up->pdev->dev);
  111. }
  112. static void serial_omap_stop_tx(struct uart_port *port)
  113. {
  114. struct uart_omap_port *up = (struct uart_omap_port *)port;
  115. if (up->use_dma &&
  116. up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) {
  117. /*
  118. * Check if dma is still active. If yes do nothing,
  119. * return. Else stop dma
  120. */
  121. if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel))
  122. return;
  123. omap_stop_dma(up->uart_dma.tx_dma_channel);
  124. omap_free_dma(up->uart_dma.tx_dma_channel);
  125. up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
  126. pm_runtime_mark_last_busy(&up->pdev->dev);
  127. pm_runtime_put_autosuspend(&up->pdev->dev);
  128. }
  129. pm_runtime_get_sync(&up->pdev->dev);
  130. if (up->ier & UART_IER_THRI) {
  131. up->ier &= ~UART_IER_THRI;
  132. serial_out(up, UART_IER, up->ier);
  133. }
  134. pm_runtime_mark_last_busy(&up->pdev->dev);
  135. pm_runtime_put_autosuspend(&up->pdev->dev);
  136. }
  137. static void serial_omap_stop_rx(struct uart_port *port)
  138. {
  139. struct uart_omap_port *up = (struct uart_omap_port *)port;
  140. pm_runtime_get_sync(&up->pdev->dev);
  141. if (up->use_dma)
  142. serial_omap_stop_rxdma(up);
  143. up->ier &= ~UART_IER_RLSI;
  144. up->port.read_status_mask &= ~UART_LSR_DR;
  145. serial_out(up, UART_IER, up->ier);
  146. pm_runtime_mark_last_busy(&up->pdev->dev);
  147. pm_runtime_put_autosuspend(&up->pdev->dev);
  148. }
  149. static inline void receive_chars(struct uart_omap_port *up,
  150. unsigned int *status)
  151. {
  152. struct tty_struct *tty = up->port.state->port.tty;
  153. unsigned int flag, lsr = *status;
  154. unsigned char ch = 0;
  155. int max_count = 256;
  156. do {
  157. if (likely(lsr & UART_LSR_DR))
  158. ch = serial_in(up, UART_RX);
  159. flag = TTY_NORMAL;
  160. up->port.icount.rx++;
  161. if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
  162. /*
  163. * For statistics only
  164. */
  165. if (lsr & UART_LSR_BI) {
  166. lsr &= ~(UART_LSR_FE | UART_LSR_PE);
  167. up->port.icount.brk++;
  168. /*
  169. * We do the SysRQ and SAK checking
  170. * here because otherwise the break
  171. * may get masked by ignore_status_mask
  172. * or read_status_mask.
  173. */
  174. if (uart_handle_break(&up->port))
  175. goto ignore_char;
  176. } else if (lsr & UART_LSR_PE) {
  177. up->port.icount.parity++;
  178. } else if (lsr & UART_LSR_FE) {
  179. up->port.icount.frame++;
  180. }
  181. if (lsr & UART_LSR_OE)
  182. up->port.icount.overrun++;
  183. /*
  184. * Mask off conditions which should be ignored.
  185. */
  186. lsr &= up->port.read_status_mask;
  187. #ifdef CONFIG_SERIAL_OMAP_CONSOLE
  188. if (up->port.line == up->port.cons->index) {
  189. /* Recover the break flag from console xmit */
  190. lsr |= up->lsr_break_flag;
  191. }
  192. #endif
  193. if (lsr & UART_LSR_BI)
  194. flag = TTY_BREAK;
  195. else if (lsr & UART_LSR_PE)
  196. flag = TTY_PARITY;
  197. else if (lsr & UART_LSR_FE)
  198. flag = TTY_FRAME;
  199. }
  200. if (uart_handle_sysrq_char(&up->port, ch))
  201. goto ignore_char;
  202. uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
  203. ignore_char:
  204. lsr = serial_in(up, UART_LSR);
  205. } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
  206. spin_unlock(&up->port.lock);
  207. tty_flip_buffer_push(tty);
  208. spin_lock(&up->port.lock);
  209. }
  210. static void transmit_chars(struct uart_omap_port *up)
  211. {
  212. struct circ_buf *xmit = &up->port.state->xmit;
  213. int count;
  214. if (up->port.x_char) {
  215. serial_out(up, UART_TX, up->port.x_char);
  216. up->port.icount.tx++;
  217. up->port.x_char = 0;
  218. return;
  219. }
  220. if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
  221. serial_omap_stop_tx(&up->port);
  222. return;
  223. }
  224. count = up->port.fifosize / 4;
  225. do {
  226. serial_out(up, UART_TX, xmit->buf[xmit->tail]);
  227. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  228. up->port.icount.tx++;
  229. if (uart_circ_empty(xmit))
  230. break;
  231. } while (--count > 0);
  232. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  233. uart_write_wakeup(&up->port);
  234. if (uart_circ_empty(xmit))
  235. serial_omap_stop_tx(&up->port);
  236. }
  237. static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
  238. {
  239. if (!(up->ier & UART_IER_THRI)) {
  240. up->ier |= UART_IER_THRI;
  241. serial_out(up, UART_IER, up->ier);
  242. }
  243. }
  244. static void serial_omap_start_tx(struct uart_port *port)
  245. {
  246. struct uart_omap_port *up = (struct uart_omap_port *)port;
  247. struct circ_buf *xmit;
  248. unsigned int start;
  249. int ret = 0;
  250. if (!up->use_dma) {
  251. pm_runtime_get_sync(&up->pdev->dev);
  252. serial_omap_enable_ier_thri(up);
  253. pm_runtime_mark_last_busy(&up->pdev->dev);
  254. pm_runtime_put_autosuspend(&up->pdev->dev);
  255. return;
  256. }
  257. if (up->uart_dma.tx_dma_used)
  258. return;
  259. xmit = &up->port.state->xmit;
  260. if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) {
  261. pm_runtime_get_sync(&up->pdev->dev);
  262. ret = omap_request_dma(up->uart_dma.uart_dma_tx,
  263. "UART Tx DMA",
  264. (void *)uart_tx_dma_callback, up,
  265. &(up->uart_dma.tx_dma_channel));
  266. if (ret < 0) {
  267. serial_omap_enable_ier_thri(up);
  268. return;
  269. }
  270. }
  271. spin_lock(&(up->uart_dma.tx_lock));
  272. up->uart_dma.tx_dma_used = true;
  273. spin_unlock(&(up->uart_dma.tx_lock));
  274. start = up->uart_dma.tx_buf_dma_phys +
  275. (xmit->tail & (UART_XMIT_SIZE - 1));
  276. up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
  277. /*
  278. * It is a circular buffer. See if the buffer has wounded back.
  279. * If yes it will have to be transferred in two separate dma
  280. * transfers
  281. */
  282. if (start + up->uart_dma.tx_buf_size >=
  283. up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
  284. up->uart_dma.tx_buf_size =
  285. (up->uart_dma.tx_buf_dma_phys +
  286. UART_XMIT_SIZE) - start;
  287. omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
  288. OMAP_DMA_AMODE_CONSTANT,
  289. up->uart_dma.uart_base, 0, 0);
  290. omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
  291. OMAP_DMA_AMODE_POST_INC, start, 0, 0);
  292. omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
  293. OMAP_DMA_DATA_TYPE_S8,
  294. up->uart_dma.tx_buf_size, 1,
  295. OMAP_DMA_SYNC_ELEMENT,
  296. up->uart_dma.uart_dma_tx, 0);
  297. /* FIXME: Cache maintenance needed here? */
  298. omap_start_dma(up->uart_dma.tx_dma_channel);
  299. }
  300. static unsigned int check_modem_status(struct uart_omap_port *up)
  301. {
  302. unsigned int status;
  303. status = serial_in(up, UART_MSR);
  304. status |= up->msr_saved_flags;
  305. up->msr_saved_flags = 0;
  306. if ((status & UART_MSR_ANY_DELTA) == 0)
  307. return status;
  308. if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
  309. up->port.state != NULL) {
  310. if (status & UART_MSR_TERI)
  311. up->port.icount.rng++;
  312. if (status & UART_MSR_DDSR)
  313. up->port.icount.dsr++;
  314. if (status & UART_MSR_DDCD)
  315. uart_handle_dcd_change
  316. (&up->port, status & UART_MSR_DCD);
  317. if (status & UART_MSR_DCTS)
  318. uart_handle_cts_change
  319. (&up->port, status & UART_MSR_CTS);
  320. wake_up_interruptible(&up->port.state->port.delta_msr_wait);
  321. }
  322. return status;
  323. }
  324. /**
  325. * serial_omap_irq() - This handles the interrupt from one port
  326. * @irq: uart port irq number
  327. * @dev_id: uart port info
  328. */
  329. static inline irqreturn_t serial_omap_irq(int irq, void *dev_id)
  330. {
  331. struct uart_omap_port *up = dev_id;
  332. unsigned int iir, lsr;
  333. unsigned long flags;
  334. pm_runtime_get_sync(&up->pdev->dev);
  335. iir = serial_in(up, UART_IIR);
  336. if (iir & UART_IIR_NO_INT) {
  337. pm_runtime_mark_last_busy(&up->pdev->dev);
  338. pm_runtime_put_autosuspend(&up->pdev->dev);
  339. return IRQ_NONE;
  340. }
  341. spin_lock_irqsave(&up->port.lock, flags);
  342. lsr = serial_in(up, UART_LSR);
  343. if (iir & UART_IIR_RLSI) {
  344. if (!up->use_dma) {
  345. if (lsr & UART_LSR_DR)
  346. receive_chars(up, &lsr);
  347. } else {
  348. up->ier &= ~(UART_IER_RDI | UART_IER_RLSI);
  349. serial_out(up, UART_IER, up->ier);
  350. if ((serial_omap_start_rxdma(up) != 0) &&
  351. (lsr & UART_LSR_DR))
  352. receive_chars(up, &lsr);
  353. }
  354. }
  355. check_modem_status(up);
  356. if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI))
  357. transmit_chars(up);
  358. spin_unlock_irqrestore(&up->port.lock, flags);
  359. pm_runtime_mark_last_busy(&up->pdev->dev);
  360. pm_runtime_put_autosuspend(&up->pdev->dev);
  361. up->port_activity = jiffies;
  362. return IRQ_HANDLED;
  363. }
  364. static unsigned int serial_omap_tx_empty(struct uart_port *port)
  365. {
  366. struct uart_omap_port *up = (struct uart_omap_port *)port;
  367. unsigned long flags = 0;
  368. unsigned int ret = 0;
  369. pm_runtime_get_sync(&up->pdev->dev);
  370. dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
  371. spin_lock_irqsave(&up->port.lock, flags);
  372. ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
  373. spin_unlock_irqrestore(&up->port.lock, flags);
  374. pm_runtime_put(&up->pdev->dev);
  375. return ret;
  376. }
  377. static unsigned int serial_omap_get_mctrl(struct uart_port *port)
  378. {
  379. struct uart_omap_port *up = (struct uart_omap_port *)port;
  380. unsigned int status;
  381. unsigned int ret = 0;
  382. pm_runtime_get_sync(&up->pdev->dev);
  383. status = check_modem_status(up);
  384. pm_runtime_put(&up->pdev->dev);
  385. dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
  386. if (status & UART_MSR_DCD)
  387. ret |= TIOCM_CAR;
  388. if (status & UART_MSR_RI)
  389. ret |= TIOCM_RNG;
  390. if (status & UART_MSR_DSR)
  391. ret |= TIOCM_DSR;
  392. if (status & UART_MSR_CTS)
  393. ret |= TIOCM_CTS;
  394. return ret;
  395. }
  396. static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
  397. {
  398. struct uart_omap_port *up = (struct uart_omap_port *)port;
  399. unsigned char mcr = 0;
  400. dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
  401. if (mctrl & TIOCM_RTS)
  402. mcr |= UART_MCR_RTS;
  403. if (mctrl & TIOCM_DTR)
  404. mcr |= UART_MCR_DTR;
  405. if (mctrl & TIOCM_OUT1)
  406. mcr |= UART_MCR_OUT1;
  407. if (mctrl & TIOCM_OUT2)
  408. mcr |= UART_MCR_OUT2;
  409. if (mctrl & TIOCM_LOOP)
  410. mcr |= UART_MCR_LOOP;
  411. pm_runtime_get_sync(&up->pdev->dev);
  412. up->mcr = serial_in(up, UART_MCR);
  413. up->mcr |= mcr;
  414. serial_out(up, UART_MCR, up->mcr);
  415. pm_runtime_put(&up->pdev->dev);
  416. }
  417. static void serial_omap_break_ctl(struct uart_port *port, int break_state)
  418. {
  419. struct uart_omap_port *up = (struct uart_omap_port *)port;
  420. unsigned long flags = 0;
  421. dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
  422. pm_runtime_get_sync(&up->pdev->dev);
  423. spin_lock_irqsave(&up->port.lock, flags);
  424. if (break_state == -1)
  425. up->lcr |= UART_LCR_SBC;
  426. else
  427. up->lcr &= ~UART_LCR_SBC;
  428. serial_out(up, UART_LCR, up->lcr);
  429. spin_unlock_irqrestore(&up->port.lock, flags);
  430. pm_runtime_put(&up->pdev->dev);
  431. }
  432. static int serial_omap_startup(struct uart_port *port)
  433. {
  434. struct uart_omap_port *up = (struct uart_omap_port *)port;
  435. unsigned long flags = 0;
  436. int retval;
  437. /*
  438. * Allocate the IRQ
  439. */
  440. retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
  441. up->name, up);
  442. if (retval)
  443. return retval;
  444. dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
  445. pm_runtime_get_sync(&up->pdev->dev);
  446. /*
  447. * Clear the FIFO buffers and disable them.
  448. * (they will be reenabled in set_termios())
  449. */
  450. serial_omap_clear_fifos(up);
  451. /* For Hardware flow control */
  452. serial_out(up, UART_MCR, UART_MCR_RTS);
  453. /*
  454. * Clear the interrupt registers.
  455. */
  456. (void) serial_in(up, UART_LSR);
  457. if (serial_in(up, UART_LSR) & UART_LSR_DR)
  458. (void) serial_in(up, UART_RX);
  459. (void) serial_in(up, UART_IIR);
  460. (void) serial_in(up, UART_MSR);
  461. /*
  462. * Now, initialize the UART
  463. */
  464. serial_out(up, UART_LCR, UART_LCR_WLEN8);
  465. spin_lock_irqsave(&up->port.lock, flags);
  466. /*
  467. * Most PC uarts need OUT2 raised to enable interrupts.
  468. */
  469. up->port.mctrl |= TIOCM_OUT2;
  470. serial_omap_set_mctrl(&up->port, up->port.mctrl);
  471. spin_unlock_irqrestore(&up->port.lock, flags);
  472. up->msr_saved_flags = 0;
  473. if (up->use_dma) {
  474. free_page((unsigned long)up->port.state->xmit.buf);
  475. up->port.state->xmit.buf = dma_alloc_coherent(NULL,
  476. UART_XMIT_SIZE,
  477. (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys),
  478. 0);
  479. init_timer(&(up->uart_dma.rx_timer));
  480. up->uart_dma.rx_timer.function = serial_omap_rxdma_poll;
  481. up->uart_dma.rx_timer.data = up->port.line;
  482. /* Currently the buffer size is 4KB. Can increase it */
  483. up->uart_dma.rx_buf = dma_alloc_coherent(NULL,
  484. up->uart_dma.rx_buf_size,
  485. (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0);
  486. }
  487. /*
  488. * Finally, enable interrupts. Note: Modem status interrupts
  489. * are set via set_termios(), which will be occurring imminently
  490. * anyway, so we don't enable them here.
  491. */
  492. up->ier = UART_IER_RLSI | UART_IER_RDI;
  493. serial_out(up, UART_IER, up->ier);
  494. /* Enable module level wake up */
  495. serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
  496. pm_runtime_mark_last_busy(&up->pdev->dev);
  497. pm_runtime_put_autosuspend(&up->pdev->dev);
  498. up->port_activity = jiffies;
  499. return 0;
  500. }
  501. static void serial_omap_shutdown(struct uart_port *port)
  502. {
  503. struct uart_omap_port *up = (struct uart_omap_port *)port;
  504. unsigned long flags = 0;
  505. dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
  506. pm_runtime_get_sync(&up->pdev->dev);
  507. /*
  508. * Disable interrupts from this port
  509. */
  510. up->ier = 0;
  511. serial_out(up, UART_IER, 0);
  512. spin_lock_irqsave(&up->port.lock, flags);
  513. up->port.mctrl &= ~TIOCM_OUT2;
  514. serial_omap_set_mctrl(&up->port, up->port.mctrl);
  515. spin_unlock_irqrestore(&up->port.lock, flags);
  516. /*
  517. * Disable break condition and FIFOs
  518. */
  519. serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
  520. serial_omap_clear_fifos(up);
  521. /*
  522. * Read data port to reset things, and then free the irq
  523. */
  524. if (serial_in(up, UART_LSR) & UART_LSR_DR)
  525. (void) serial_in(up, UART_RX);
  526. if (up->use_dma) {
  527. dma_free_coherent(up->port.dev,
  528. UART_XMIT_SIZE, up->port.state->xmit.buf,
  529. up->uart_dma.tx_buf_dma_phys);
  530. up->port.state->xmit.buf = NULL;
  531. serial_omap_stop_rx(port);
  532. dma_free_coherent(up->port.dev,
  533. up->uart_dma.rx_buf_size, up->uart_dma.rx_buf,
  534. up->uart_dma.rx_buf_dma_phys);
  535. up->uart_dma.rx_buf = NULL;
  536. }
  537. pm_runtime_put(&up->pdev->dev);
  538. free_irq(up->port.irq, up);
  539. }
  540. static inline void
  541. serial_omap_configure_xonxoff
  542. (struct uart_omap_port *up, struct ktermios *termios)
  543. {
  544. up->lcr = serial_in(up, UART_LCR);
  545. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  546. up->efr = serial_in(up, UART_EFR);
  547. serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
  548. serial_out(up, UART_XON1, termios->c_cc[VSTART]);
  549. serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
  550. /* clear SW control mode bits */
  551. up->efr &= OMAP_UART_SW_CLR;
  552. /*
  553. * IXON Flag:
  554. * Enable XON/XOFF flow control on output.
  555. * Transmit XON1, XOFF1
  556. */
  557. if (termios->c_iflag & IXON)
  558. up->efr |= OMAP_UART_SW_TX;
  559. /*
  560. * IXOFF Flag:
  561. * Enable XON/XOFF flow control on input.
  562. * Receiver compares XON1, XOFF1.
  563. */
  564. if (termios->c_iflag & IXOFF)
  565. up->efr |= OMAP_UART_SW_RX;
  566. serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
  567. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  568. up->mcr = serial_in(up, UART_MCR);
  569. /*
  570. * IXANY Flag:
  571. * Enable any character to restart output.
  572. * Operation resumes after receiving any
  573. * character after recognition of the XOFF character
  574. */
  575. if (termios->c_iflag & IXANY)
  576. up->mcr |= UART_MCR_XONANY;
  577. serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
  578. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  579. serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
  580. /* Enable special char function UARTi.EFR_REG[5] and
  581. * load the new software flow control mode IXON or IXOFF
  582. * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
  583. */
  584. serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
  585. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  586. serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
  587. serial_out(up, UART_LCR, up->lcr);
  588. }
  589. static void serial_omap_uart_qos_work(struct work_struct *work)
  590. {
  591. struct uart_omap_port *up = container_of(work, struct uart_omap_port,
  592. qos_work);
  593. pm_qos_update_request(&up->pm_qos_request, up->latency);
  594. }
  595. static void
  596. serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
  597. struct ktermios *old)
  598. {
  599. struct uart_omap_port *up = (struct uart_omap_port *)port;
  600. unsigned char cval = 0;
  601. unsigned char efr = 0;
  602. unsigned long flags = 0;
  603. unsigned int baud, quot;
  604. switch (termios->c_cflag & CSIZE) {
  605. case CS5:
  606. cval = UART_LCR_WLEN5;
  607. break;
  608. case CS6:
  609. cval = UART_LCR_WLEN6;
  610. break;
  611. case CS7:
  612. cval = UART_LCR_WLEN7;
  613. break;
  614. default:
  615. case CS8:
  616. cval = UART_LCR_WLEN8;
  617. break;
  618. }
  619. if (termios->c_cflag & CSTOPB)
  620. cval |= UART_LCR_STOP;
  621. if (termios->c_cflag & PARENB)
  622. cval |= UART_LCR_PARITY;
  623. if (!(termios->c_cflag & PARODD))
  624. cval |= UART_LCR_EPAR;
  625. /*
  626. * Ask the core to calculate the divisor for us.
  627. */
  628. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
  629. quot = serial_omap_get_divisor(port, baud);
  630. /* calculate wakeup latency constraint */
  631. up->calc_latency = (1000000 * up->port.fifosize) /
  632. (1000 * baud / 8);
  633. up->latency = up->calc_latency;
  634. schedule_work(&up->qos_work);
  635. up->dll = quot & 0xff;
  636. up->dlh = quot >> 8;
  637. up->mdr1 = UART_OMAP_MDR1_DISABLE;
  638. up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
  639. UART_FCR_ENABLE_FIFO;
  640. if (up->use_dma)
  641. up->fcr |= UART_FCR_DMA_SELECT;
  642. /*
  643. * Ok, we're now changing the port state. Do it with
  644. * interrupts disabled.
  645. */
  646. pm_runtime_get_sync(&up->pdev->dev);
  647. spin_lock_irqsave(&up->port.lock, flags);
  648. /*
  649. * Update the per-port timeout.
  650. */
  651. uart_update_timeout(port, termios->c_cflag, baud);
  652. up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
  653. if (termios->c_iflag & INPCK)
  654. up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
  655. if (termios->c_iflag & (BRKINT | PARMRK))
  656. up->port.read_status_mask |= UART_LSR_BI;
  657. /*
  658. * Characters to ignore
  659. */
  660. up->port.ignore_status_mask = 0;
  661. if (termios->c_iflag & IGNPAR)
  662. up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
  663. if (termios->c_iflag & IGNBRK) {
  664. up->port.ignore_status_mask |= UART_LSR_BI;
  665. /*
  666. * If we're ignoring parity and break indicators,
  667. * ignore overruns too (for real raw support).
  668. */
  669. if (termios->c_iflag & IGNPAR)
  670. up->port.ignore_status_mask |= UART_LSR_OE;
  671. }
  672. /*
  673. * ignore all characters if CREAD is not set
  674. */
  675. if ((termios->c_cflag & CREAD) == 0)
  676. up->port.ignore_status_mask |= UART_LSR_DR;
  677. /*
  678. * Modem status interrupts
  679. */
  680. up->ier &= ~UART_IER_MSI;
  681. if (UART_ENABLE_MS(&up->port, termios->c_cflag))
  682. up->ier |= UART_IER_MSI;
  683. serial_out(up, UART_IER, up->ier);
  684. serial_out(up, UART_LCR, cval); /* reset DLAB */
  685. up->lcr = cval;
  686. up->scr = OMAP_UART_SCR_TX_EMPTY;
  687. /* FIFOs and DMA Settings */
  688. /* FCR can be changed only when the
  689. * baud clock is not running
  690. * DLL_REG and DLH_REG set to 0.
  691. */
  692. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  693. serial_out(up, UART_DLL, 0);
  694. serial_out(up, UART_DLM, 0);
  695. serial_out(up, UART_LCR, 0);
  696. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  697. up->efr = serial_in(up, UART_EFR);
  698. serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
  699. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  700. up->mcr = serial_in(up, UART_MCR);
  701. serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
  702. /* FIFO ENABLE, DMA MODE */
  703. serial_out(up, UART_FCR, up->fcr);
  704. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  705. if (up->use_dma) {
  706. serial_out(up, UART_TI752_TLR, 0);
  707. up->scr |= (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8);
  708. }
  709. serial_out(up, UART_OMAP_SCR, up->scr);
  710. serial_out(up, UART_EFR, up->efr);
  711. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  712. serial_out(up, UART_MCR, up->mcr);
  713. /* Protocol, Baud Rate, and Interrupt Settings */
  714. if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
  715. serial_omap_mdr1_errataset(up, up->mdr1);
  716. else
  717. serial_out(up, UART_OMAP_MDR1, up->mdr1);
  718. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  719. up->efr = serial_in(up, UART_EFR);
  720. serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
  721. serial_out(up, UART_LCR, 0);
  722. serial_out(up, UART_IER, 0);
  723. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  724. serial_out(up, UART_DLL, up->dll); /* LS of divisor */
  725. serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
  726. serial_out(up, UART_LCR, 0);
  727. serial_out(up, UART_IER, up->ier);
  728. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  729. serial_out(up, UART_EFR, up->efr);
  730. serial_out(up, UART_LCR, cval);
  731. if (baud > 230400 && baud != 3000000)
  732. up->mdr1 = UART_OMAP_MDR1_13X_MODE;
  733. else
  734. up->mdr1 = UART_OMAP_MDR1_16X_MODE;
  735. if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
  736. serial_omap_mdr1_errataset(up, up->mdr1);
  737. else
  738. serial_out(up, UART_OMAP_MDR1, up->mdr1);
  739. /* Hardware Flow Control Configuration */
  740. if (termios->c_cflag & CRTSCTS) {
  741. efr |= (UART_EFR_CTS | UART_EFR_RTS);
  742. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  743. up->mcr = serial_in(up, UART_MCR);
  744. serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
  745. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  746. up->efr = serial_in(up, UART_EFR);
  747. serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
  748. serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
  749. serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
  750. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  751. serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
  752. serial_out(up, UART_LCR, cval);
  753. }
  754. serial_omap_set_mctrl(&up->port, up->port.mctrl);
  755. /* Software Flow Control Configuration */
  756. serial_omap_configure_xonxoff(up, termios);
  757. spin_unlock_irqrestore(&up->port.lock, flags);
  758. pm_runtime_put(&up->pdev->dev);
  759. dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
  760. }
  761. static void
  762. serial_omap_pm(struct uart_port *port, unsigned int state,
  763. unsigned int oldstate)
  764. {
  765. struct uart_omap_port *up = (struct uart_omap_port *)port;
  766. unsigned char efr;
  767. dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
  768. pm_runtime_get_sync(&up->pdev->dev);
  769. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  770. efr = serial_in(up, UART_EFR);
  771. serial_out(up, UART_EFR, efr | UART_EFR_ECB);
  772. serial_out(up, UART_LCR, 0);
  773. serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
  774. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
  775. serial_out(up, UART_EFR, efr);
  776. serial_out(up, UART_LCR, 0);
  777. if (!device_may_wakeup(&up->pdev->dev)) {
  778. if (!state)
  779. pm_runtime_forbid(&up->pdev->dev);
  780. else
  781. pm_runtime_allow(&up->pdev->dev);
  782. }
  783. pm_runtime_put(&up->pdev->dev);
  784. }
  785. static void serial_omap_release_port(struct uart_port *port)
  786. {
  787. dev_dbg(port->dev, "serial_omap_release_port+\n");
  788. }
  789. static int serial_omap_request_port(struct uart_port *port)
  790. {
  791. dev_dbg(port->dev, "serial_omap_request_port+\n");
  792. return 0;
  793. }
  794. static void serial_omap_config_port(struct uart_port *port, int flags)
  795. {
  796. struct uart_omap_port *up = (struct uart_omap_port *)port;
  797. dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
  798. up->port.line);
  799. up->port.type = PORT_OMAP;
  800. }
  801. static int
  802. serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
  803. {
  804. /* we don't want the core code to modify any port params */
  805. dev_dbg(port->dev, "serial_omap_verify_port+\n");
  806. return -EINVAL;
  807. }
  808. static const char *
  809. serial_omap_type(struct uart_port *port)
  810. {
  811. struct uart_omap_port *up = (struct uart_omap_port *)port;
  812. dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
  813. return up->name;
  814. }
  815. #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
  816. static inline void wait_for_xmitr(struct uart_omap_port *up)
  817. {
  818. unsigned int status, tmout = 10000;
  819. /* Wait up to 10ms for the character(s) to be sent. */
  820. do {
  821. status = serial_in(up, UART_LSR);
  822. if (status & UART_LSR_BI)
  823. up->lsr_break_flag = UART_LSR_BI;
  824. if (--tmout == 0)
  825. break;
  826. udelay(1);
  827. } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
  828. /* Wait up to 1s for flow control if necessary */
  829. if (up->port.flags & UPF_CONS_FLOW) {
  830. tmout = 1000000;
  831. for (tmout = 1000000; tmout; tmout--) {
  832. unsigned int msr = serial_in(up, UART_MSR);
  833. up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
  834. if (msr & UART_MSR_CTS)
  835. break;
  836. udelay(1);
  837. }
  838. }
  839. }
  840. #ifdef CONFIG_CONSOLE_POLL
  841. static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
  842. {
  843. struct uart_omap_port *up = (struct uart_omap_port *)port;
  844. pm_runtime_get_sync(&up->pdev->dev);
  845. wait_for_xmitr(up);
  846. serial_out(up, UART_TX, ch);
  847. pm_runtime_put(&up->pdev->dev);
  848. }
  849. static int serial_omap_poll_get_char(struct uart_port *port)
  850. {
  851. struct uart_omap_port *up = (struct uart_omap_port *)port;
  852. unsigned int status;
  853. pm_runtime_get_sync(&up->pdev->dev);
  854. status = serial_in(up, UART_LSR);
  855. if (!(status & UART_LSR_DR))
  856. return NO_POLL_CHAR;
  857. status = serial_in(up, UART_RX);
  858. pm_runtime_put(&up->pdev->dev);
  859. return status;
  860. }
  861. #endif /* CONFIG_CONSOLE_POLL */
  862. #ifdef CONFIG_SERIAL_OMAP_CONSOLE
  863. static struct uart_omap_port *serial_omap_console_ports[4];
  864. static struct uart_driver serial_omap_reg;
  865. static void serial_omap_console_putchar(struct uart_port *port, int ch)
  866. {
  867. struct uart_omap_port *up = (struct uart_omap_port *)port;
  868. wait_for_xmitr(up);
  869. serial_out(up, UART_TX, ch);
  870. }
  871. static void
  872. serial_omap_console_write(struct console *co, const char *s,
  873. unsigned int count)
  874. {
  875. struct uart_omap_port *up = serial_omap_console_ports[co->index];
  876. unsigned long flags;
  877. unsigned int ier;
  878. int locked = 1;
  879. pm_runtime_get_sync(&up->pdev->dev);
  880. local_irq_save(flags);
  881. if (up->port.sysrq)
  882. locked = 0;
  883. else if (oops_in_progress)
  884. locked = spin_trylock(&up->port.lock);
  885. else
  886. spin_lock(&up->port.lock);
  887. /*
  888. * First save the IER then disable the interrupts
  889. */
  890. ier = serial_in(up, UART_IER);
  891. serial_out(up, UART_IER, 0);
  892. uart_console_write(&up->port, s, count, serial_omap_console_putchar);
  893. /*
  894. * Finally, wait for transmitter to become empty
  895. * and restore the IER
  896. */
  897. wait_for_xmitr(up);
  898. serial_out(up, UART_IER, ier);
  899. /*
  900. * The receive handling will happen properly because the
  901. * receive ready bit will still be set; it is not cleared
  902. * on read. However, modem control will not, we must
  903. * call it if we have saved something in the saved flags
  904. * while processing with interrupts off.
  905. */
  906. if (up->msr_saved_flags)
  907. check_modem_status(up);
  908. pm_runtime_mark_last_busy(&up->pdev->dev);
  909. pm_runtime_put_autosuspend(&up->pdev->dev);
  910. if (locked)
  911. spin_unlock(&up->port.lock);
  912. local_irq_restore(flags);
  913. }
  914. static int __init
  915. serial_omap_console_setup(struct console *co, char *options)
  916. {
  917. struct uart_omap_port *up;
  918. int baud = 115200;
  919. int bits = 8;
  920. int parity = 'n';
  921. int flow = 'n';
  922. if (serial_omap_console_ports[co->index] == NULL)
  923. return -ENODEV;
  924. up = serial_omap_console_ports[co->index];
  925. if (options)
  926. uart_parse_options(options, &baud, &parity, &bits, &flow);
  927. return uart_set_options(&up->port, co, baud, parity, bits, flow);
  928. }
  929. static struct console serial_omap_console = {
  930. .name = OMAP_SERIAL_NAME,
  931. .write = serial_omap_console_write,
  932. .device = uart_console_device,
  933. .setup = serial_omap_console_setup,
  934. .flags = CON_PRINTBUFFER,
  935. .index = -1,
  936. .data = &serial_omap_reg,
  937. };
  938. static void serial_omap_add_console_port(struct uart_omap_port *up)
  939. {
  940. serial_omap_console_ports[up->port.line] = up;
  941. }
  942. #define OMAP_CONSOLE (&serial_omap_console)
  943. #else
  944. #define OMAP_CONSOLE NULL
  945. static inline void serial_omap_add_console_port(struct uart_omap_port *up)
  946. {}
  947. #endif
  948. static struct uart_ops serial_omap_pops = {
  949. .tx_empty = serial_omap_tx_empty,
  950. .set_mctrl = serial_omap_set_mctrl,
  951. .get_mctrl = serial_omap_get_mctrl,
  952. .stop_tx = serial_omap_stop_tx,
  953. .start_tx = serial_omap_start_tx,
  954. .stop_rx = serial_omap_stop_rx,
  955. .enable_ms = serial_omap_enable_ms,
  956. .break_ctl = serial_omap_break_ctl,
  957. .startup = serial_omap_startup,
  958. .shutdown = serial_omap_shutdown,
  959. .set_termios = serial_omap_set_termios,
  960. .pm = serial_omap_pm,
  961. .type = serial_omap_type,
  962. .release_port = serial_omap_release_port,
  963. .request_port = serial_omap_request_port,
  964. .config_port = serial_omap_config_port,
  965. .verify_port = serial_omap_verify_port,
  966. #ifdef CONFIG_CONSOLE_POLL
  967. .poll_put_char = serial_omap_poll_put_char,
  968. .poll_get_char = serial_omap_poll_get_char,
  969. #endif
  970. };
  971. static struct uart_driver serial_omap_reg = {
  972. .owner = THIS_MODULE,
  973. .driver_name = "OMAP-SERIAL",
  974. .dev_name = OMAP_SERIAL_NAME,
  975. .nr = OMAP_MAX_HSUART_PORTS,
  976. .cons = OMAP_CONSOLE,
  977. };
  978. #ifdef CONFIG_SUSPEND
  979. static int serial_omap_suspend(struct device *dev)
  980. {
  981. struct uart_omap_port *up = dev_get_drvdata(dev);
  982. if (up) {
  983. uart_suspend_port(&serial_omap_reg, &up->port);
  984. flush_work_sync(&up->qos_work);
  985. }
  986. return 0;
  987. }
  988. static int serial_omap_resume(struct device *dev)
  989. {
  990. struct uart_omap_port *up = dev_get_drvdata(dev);
  991. if (up)
  992. uart_resume_port(&serial_omap_reg, &up->port);
  993. return 0;
  994. }
  995. #endif
  996. static void serial_omap_rxdma_poll(unsigned long uart_no)
  997. {
  998. struct uart_omap_port *up = ui[uart_no];
  999. unsigned int curr_dma_pos, curr_transmitted_size;
  1000. int ret = 0;
  1001. curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel);
  1002. if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) ||
  1003. (curr_dma_pos == 0)) {
  1004. if (jiffies_to_msecs(jiffies - up->port_activity) <
  1005. up->uart_dma.rx_timeout) {
  1006. mod_timer(&up->uart_dma.rx_timer, jiffies +
  1007. usecs_to_jiffies(up->uart_dma.rx_poll_rate));
  1008. } else {
  1009. serial_omap_stop_rxdma(up);
  1010. up->ier |= (UART_IER_RDI | UART_IER_RLSI);
  1011. serial_out(up, UART_IER, up->ier);
  1012. }
  1013. return;
  1014. }
  1015. curr_transmitted_size = curr_dma_pos -
  1016. up->uart_dma.prev_rx_dma_pos;
  1017. up->port.icount.rx += curr_transmitted_size;
  1018. tty_insert_flip_string(up->port.state->port.tty,
  1019. up->uart_dma.rx_buf +
  1020. (up->uart_dma.prev_rx_dma_pos -
  1021. up->uart_dma.rx_buf_dma_phys),
  1022. curr_transmitted_size);
  1023. tty_flip_buffer_push(up->port.state->port.tty);
  1024. up->uart_dma.prev_rx_dma_pos = curr_dma_pos;
  1025. if (up->uart_dma.rx_buf_size +
  1026. up->uart_dma.rx_buf_dma_phys == curr_dma_pos) {
  1027. ret = serial_omap_start_rxdma(up);
  1028. if (ret < 0) {
  1029. serial_omap_stop_rxdma(up);
  1030. up->ier |= (UART_IER_RDI | UART_IER_RLSI);
  1031. serial_out(up, UART_IER, up->ier);
  1032. }
  1033. } else {
  1034. mod_timer(&up->uart_dma.rx_timer, jiffies +
  1035. usecs_to_jiffies(up->uart_dma.rx_poll_rate));
  1036. }
  1037. up->port_activity = jiffies;
  1038. }
  1039. static void uart_rx_dma_callback(int lch, u16 ch_status, void *data)
  1040. {
  1041. return;
  1042. }
  1043. static int serial_omap_start_rxdma(struct uart_omap_port *up)
  1044. {
  1045. int ret = 0;
  1046. if (up->uart_dma.rx_dma_channel == -1) {
  1047. pm_runtime_get_sync(&up->pdev->dev);
  1048. ret = omap_request_dma(up->uart_dma.uart_dma_rx,
  1049. "UART Rx DMA",
  1050. (void *)uart_rx_dma_callback, up,
  1051. &(up->uart_dma.rx_dma_channel));
  1052. if (ret < 0)
  1053. return ret;
  1054. omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0,
  1055. OMAP_DMA_AMODE_CONSTANT,
  1056. up->uart_dma.uart_base, 0, 0);
  1057. omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0,
  1058. OMAP_DMA_AMODE_POST_INC,
  1059. up->uart_dma.rx_buf_dma_phys, 0, 0);
  1060. omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel,
  1061. OMAP_DMA_DATA_TYPE_S8,
  1062. up->uart_dma.rx_buf_size, 1,
  1063. OMAP_DMA_SYNC_ELEMENT,
  1064. up->uart_dma.uart_dma_rx, 0);
  1065. }
  1066. up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys;
  1067. /* FIXME: Cache maintenance needed here? */
  1068. omap_start_dma(up->uart_dma.rx_dma_channel);
  1069. mod_timer(&up->uart_dma.rx_timer, jiffies +
  1070. usecs_to_jiffies(up->uart_dma.rx_poll_rate));
  1071. up->uart_dma.rx_dma_used = true;
  1072. return ret;
  1073. }
  1074. static void serial_omap_continue_tx(struct uart_omap_port *up)
  1075. {
  1076. struct circ_buf *xmit = &up->port.state->xmit;
  1077. unsigned int start = up->uart_dma.tx_buf_dma_phys
  1078. + (xmit->tail & (UART_XMIT_SIZE - 1));
  1079. if (uart_circ_empty(xmit))
  1080. return;
  1081. up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit);
  1082. /*
  1083. * It is a circular buffer. See if the buffer has wounded back.
  1084. * If yes it will have to be transferred in two separate dma
  1085. * transfers
  1086. */
  1087. if (start + up->uart_dma.tx_buf_size >=
  1088. up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE)
  1089. up->uart_dma.tx_buf_size =
  1090. (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start;
  1091. omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0,
  1092. OMAP_DMA_AMODE_CONSTANT,
  1093. up->uart_dma.uart_base, 0, 0);
  1094. omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0,
  1095. OMAP_DMA_AMODE_POST_INC, start, 0, 0);
  1096. omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel,
  1097. OMAP_DMA_DATA_TYPE_S8,
  1098. up->uart_dma.tx_buf_size, 1,
  1099. OMAP_DMA_SYNC_ELEMENT,
  1100. up->uart_dma.uart_dma_tx, 0);
  1101. /* FIXME: Cache maintenance needed here? */
  1102. omap_start_dma(up->uart_dma.tx_dma_channel);
  1103. }
  1104. static void uart_tx_dma_callback(int lch, u16 ch_status, void *data)
  1105. {
  1106. struct uart_omap_port *up = (struct uart_omap_port *)data;
  1107. struct circ_buf *xmit = &up->port.state->xmit;
  1108. xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \
  1109. (UART_XMIT_SIZE - 1);
  1110. up->port.icount.tx += up->uart_dma.tx_buf_size;
  1111. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  1112. uart_write_wakeup(&up->port);
  1113. if (uart_circ_empty(xmit)) {
  1114. spin_lock(&(up->uart_dma.tx_lock));
  1115. serial_omap_stop_tx(&up->port);
  1116. up->uart_dma.tx_dma_used = false;
  1117. spin_unlock(&(up->uart_dma.tx_lock));
  1118. } else {
  1119. omap_stop_dma(up->uart_dma.tx_dma_channel);
  1120. serial_omap_continue_tx(up);
  1121. }
  1122. up->port_activity = jiffies;
  1123. return;
  1124. }
  1125. static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
  1126. {
  1127. struct omap_uart_port_info *omap_up_info;
  1128. omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
  1129. if (!omap_up_info)
  1130. return NULL; /* out of memory */
  1131. of_property_read_u32(dev->of_node, "clock-frequency",
  1132. &omap_up_info->uartclk);
  1133. return omap_up_info;
  1134. }
  1135. static int serial_omap_probe(struct platform_device *pdev)
  1136. {
  1137. struct uart_omap_port *up;
  1138. struct resource *mem, *irq, *dma_tx, *dma_rx;
  1139. struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
  1140. int ret = -ENOSPC;
  1141. if (pdev->dev.of_node)
  1142. omap_up_info = of_get_uart_port_info(&pdev->dev);
  1143. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1144. if (!mem) {
  1145. dev_err(&pdev->dev, "no mem resource?\n");
  1146. return -ENODEV;
  1147. }
  1148. irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1149. if (!irq) {
  1150. dev_err(&pdev->dev, "no irq resource?\n");
  1151. return -ENODEV;
  1152. }
  1153. if (!request_mem_region(mem->start, resource_size(mem),
  1154. pdev->dev.driver->name)) {
  1155. dev_err(&pdev->dev, "memory region already claimed\n");
  1156. return -EBUSY;
  1157. }
  1158. dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
  1159. if (!dma_rx) {
  1160. ret = -EINVAL;
  1161. goto err;
  1162. }
  1163. dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
  1164. if (!dma_tx) {
  1165. ret = -EINVAL;
  1166. goto err;
  1167. }
  1168. up = kzalloc(sizeof(*up), GFP_KERNEL);
  1169. if (up == NULL) {
  1170. ret = -ENOMEM;
  1171. goto do_release_region;
  1172. }
  1173. up->pdev = pdev;
  1174. up->port.dev = &pdev->dev;
  1175. up->port.type = PORT_OMAP;
  1176. up->port.iotype = UPIO_MEM;
  1177. up->port.irq = irq->start;
  1178. up->port.regshift = 2;
  1179. up->port.fifosize = 64;
  1180. up->port.ops = &serial_omap_pops;
  1181. if (pdev->dev.of_node)
  1182. up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
  1183. else
  1184. up->port.line = pdev->id;
  1185. if (up->port.line < 0) {
  1186. dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
  1187. up->port.line);
  1188. ret = -ENODEV;
  1189. goto err;
  1190. }
  1191. sprintf(up->name, "OMAP UART%d", up->port.line);
  1192. up->port.mapbase = mem->start;
  1193. up->port.membase = ioremap(mem->start, resource_size(mem));
  1194. if (!up->port.membase) {
  1195. dev_err(&pdev->dev, "can't ioremap UART\n");
  1196. ret = -ENOMEM;
  1197. goto err;
  1198. }
  1199. up->port.flags = omap_up_info->flags;
  1200. up->port.uartclk = omap_up_info->uartclk;
  1201. if (!up->port.uartclk) {
  1202. up->port.uartclk = DEFAULT_CLK_SPEED;
  1203. dev_warn(&pdev->dev, "No clock speed specified: using default:"
  1204. "%d\n", DEFAULT_CLK_SPEED);
  1205. }
  1206. up->uart_dma.uart_base = mem->start;
  1207. up->errata = omap_up_info->errata;
  1208. if (omap_up_info->dma_enabled) {
  1209. up->uart_dma.uart_dma_tx = dma_tx->start;
  1210. up->uart_dma.uart_dma_rx = dma_rx->start;
  1211. up->use_dma = 1;
  1212. up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size;
  1213. up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout;
  1214. up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate;
  1215. spin_lock_init(&(up->uart_dma.tx_lock));
  1216. spin_lock_init(&(up->uart_dma.rx_lock));
  1217. up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE;
  1218. up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE;
  1219. }
  1220. up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
  1221. up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
  1222. pm_qos_add_request(&up->pm_qos_request,
  1223. PM_QOS_CPU_DMA_LATENCY, up->latency);
  1224. serial_omap_uart_wq = create_singlethread_workqueue(up->name);
  1225. INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
  1226. pm_runtime_use_autosuspend(&pdev->dev);
  1227. pm_runtime_set_autosuspend_delay(&pdev->dev,
  1228. omap_up_info->autosuspend_timeout);
  1229. pm_runtime_irq_safe(&pdev->dev);
  1230. pm_runtime_enable(&pdev->dev);
  1231. pm_runtime_get_sync(&pdev->dev);
  1232. ui[up->port.line] = up;
  1233. serial_omap_add_console_port(up);
  1234. ret = uart_add_one_port(&serial_omap_reg, &up->port);
  1235. if (ret != 0)
  1236. goto do_release_region;
  1237. pm_runtime_put(&pdev->dev);
  1238. platform_set_drvdata(pdev, up);
  1239. return 0;
  1240. err:
  1241. dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
  1242. pdev->id, __func__, ret);
  1243. do_release_region:
  1244. release_mem_region(mem->start, resource_size(mem));
  1245. return ret;
  1246. }
  1247. static int serial_omap_remove(struct platform_device *dev)
  1248. {
  1249. struct uart_omap_port *up = platform_get_drvdata(dev);
  1250. if (up) {
  1251. pm_runtime_disable(&up->pdev->dev);
  1252. uart_remove_one_port(&serial_omap_reg, &up->port);
  1253. pm_qos_remove_request(&up->pm_qos_request);
  1254. kfree(up);
  1255. }
  1256. platform_set_drvdata(dev, NULL);
  1257. return 0;
  1258. }
  1259. /*
  1260. * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
  1261. * The access to uart register after MDR1 Access
  1262. * causes UART to corrupt data.
  1263. *
  1264. * Need a delay =
  1265. * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
  1266. * give 10 times as much
  1267. */
  1268. static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
  1269. {
  1270. u8 timeout = 255;
  1271. serial_out(up, UART_OMAP_MDR1, mdr1);
  1272. udelay(2);
  1273. serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
  1274. UART_FCR_CLEAR_RCVR);
  1275. /*
  1276. * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
  1277. * TX_FIFO_E bit is 1.
  1278. */
  1279. while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
  1280. (UART_LSR_THRE | UART_LSR_DR))) {
  1281. timeout--;
  1282. if (!timeout) {
  1283. /* Should *never* happen. we warn and carry on */
  1284. dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n",
  1285. serial_in(up, UART_LSR));
  1286. break;
  1287. }
  1288. udelay(1);
  1289. }
  1290. }
  1291. static void serial_omap_restore_context(struct uart_omap_port *up)
  1292. {
  1293. if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
  1294. serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
  1295. else
  1296. serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
  1297. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
  1298. serial_out(up, UART_EFR, UART_EFR_ECB);
  1299. serial_out(up, UART_LCR, 0x0); /* Operational mode */
  1300. serial_out(up, UART_IER, 0x0);
  1301. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
  1302. serial_out(up, UART_DLL, up->dll);
  1303. serial_out(up, UART_DLM, up->dlh);
  1304. serial_out(up, UART_LCR, 0x0); /* Operational mode */
  1305. serial_out(up, UART_IER, up->ier);
  1306. serial_out(up, UART_FCR, up->fcr);
  1307. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
  1308. serial_out(up, UART_MCR, up->mcr);
  1309. serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
  1310. serial_out(up, UART_OMAP_SCR, up->scr);
  1311. serial_out(up, UART_EFR, up->efr);
  1312. serial_out(up, UART_LCR, up->lcr);
  1313. if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
  1314. serial_omap_mdr1_errataset(up, up->mdr1);
  1315. else
  1316. serial_out(up, UART_OMAP_MDR1, up->mdr1);
  1317. }
  1318. #ifdef CONFIG_PM_RUNTIME
  1319. static int serial_omap_runtime_suspend(struct device *dev)
  1320. {
  1321. struct uart_omap_port *up = dev_get_drvdata(dev);
  1322. struct omap_uart_port_info *pdata = dev->platform_data;
  1323. if (!up)
  1324. return -EINVAL;
  1325. if (!pdata || !pdata->enable_wakeup)
  1326. return 0;
  1327. if (pdata->get_context_loss_count)
  1328. up->context_loss_cnt = pdata->get_context_loss_count(dev);
  1329. if (device_may_wakeup(dev)) {
  1330. if (!up->wakeups_enabled) {
  1331. pdata->enable_wakeup(up->pdev, true);
  1332. up->wakeups_enabled = true;
  1333. }
  1334. } else {
  1335. if (up->wakeups_enabled) {
  1336. pdata->enable_wakeup(up->pdev, false);
  1337. up->wakeups_enabled = false;
  1338. }
  1339. }
  1340. /* Errata i291 */
  1341. if (up->use_dma && pdata->set_forceidle &&
  1342. (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
  1343. pdata->set_forceidle(up->pdev);
  1344. up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
  1345. schedule_work(&up->qos_work);
  1346. return 0;
  1347. }
  1348. static int serial_omap_runtime_resume(struct device *dev)
  1349. {
  1350. struct uart_omap_port *up = dev_get_drvdata(dev);
  1351. struct omap_uart_port_info *pdata = dev->platform_data;
  1352. if (up) {
  1353. if (pdata->get_context_loss_count) {
  1354. u32 loss_cnt = pdata->get_context_loss_count(dev);
  1355. if (up->context_loss_cnt != loss_cnt)
  1356. serial_omap_restore_context(up);
  1357. }
  1358. /* Errata i291 */
  1359. if (up->use_dma && pdata->set_noidle &&
  1360. (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE))
  1361. pdata->set_noidle(up->pdev);
  1362. up->latency = up->calc_latency;
  1363. schedule_work(&up->qos_work);
  1364. }
  1365. return 0;
  1366. }
  1367. #endif
  1368. static const struct dev_pm_ops serial_omap_dev_pm_ops = {
  1369. SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
  1370. SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
  1371. serial_omap_runtime_resume, NULL)
  1372. };
  1373. #if defined(CONFIG_OF)
  1374. static const struct of_device_id omap_serial_of_match[] = {
  1375. { .compatible = "ti,omap2-uart" },
  1376. { .compatible = "ti,omap3-uart" },
  1377. { .compatible = "ti,omap4-uart" },
  1378. {},
  1379. };
  1380. MODULE_DEVICE_TABLE(of, omap_serial_of_match);
  1381. #endif
  1382. static struct platform_driver serial_omap_driver = {
  1383. .probe = serial_omap_probe,
  1384. .remove = serial_omap_remove,
  1385. .driver = {
  1386. .name = DRIVER_NAME,
  1387. .pm = &serial_omap_dev_pm_ops,
  1388. .of_match_table = of_match_ptr(omap_serial_of_match),
  1389. },
  1390. };
  1391. static int __init serial_omap_init(void)
  1392. {
  1393. int ret;
  1394. ret = uart_register_driver(&serial_omap_reg);
  1395. if (ret != 0)
  1396. return ret;
  1397. ret = platform_driver_register(&serial_omap_driver);
  1398. if (ret != 0)
  1399. uart_unregister_driver(&serial_omap_reg);
  1400. return ret;
  1401. }
  1402. static void __exit serial_omap_exit(void)
  1403. {
  1404. platform_driver_unregister(&serial_omap_driver);
  1405. uart_unregister_driver(&serial_omap_reg);
  1406. }
  1407. module_init(serial_omap_init);
  1408. module_exit(serial_omap_exit);
  1409. MODULE_DESCRIPTION("OMAP High Speed UART driver");
  1410. MODULE_LICENSE("GPL");
  1411. MODULE_AUTHOR("Texas Instruments Inc");