rt2800pci.c 36 KB

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  1. /*
  2. Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
  3. Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
  4. Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  5. Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  6. Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  7. Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  8. Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  9. Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10. <http://rt2x00.serialmonkey.com>
  11. This program is free software; you can redistribute it and/or modify
  12. it under the terms of the GNU General Public License as published by
  13. the Free Software Foundation; either version 2 of the License, or
  14. (at your option) any later version.
  15. This program is distributed in the hope that it will be useful,
  16. but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. GNU General Public License for more details.
  19. You should have received a copy of the GNU General Public License
  20. along with this program; if not, write to the
  21. Free Software Foundation, Inc.,
  22. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23. */
  24. /*
  25. Module: rt2800pci
  26. Abstract: rt2800pci device specific routines.
  27. Supported chipsets: RT2800E & RT2800ED.
  28. */
  29. #include <linux/delay.h>
  30. #include <linux/etherdevice.h>
  31. #include <linux/init.h>
  32. #include <linux/kernel.h>
  33. #include <linux/module.h>
  34. #include <linux/pci.h>
  35. #include <linux/platform_device.h>
  36. #include <linux/eeprom_93cx6.h>
  37. #include "rt2x00.h"
  38. #include "rt2x00pci.h"
  39. #include "rt2x00soc.h"
  40. #include "rt2800lib.h"
  41. #include "rt2800.h"
  42. #include "rt2800pci.h"
  43. /*
  44. * Allow hardware encryption to be disabled.
  45. */
  46. static bool modparam_nohwcrypt = false;
  47. module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  48. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  49. static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
  50. {
  51. unsigned int i;
  52. u32 reg;
  53. /*
  54. * SOC devices don't support MCU requests.
  55. */
  56. if (rt2x00_is_soc(rt2x00dev))
  57. return;
  58. for (i = 0; i < 200; i++) {
  59. rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
  60. if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
  61. (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
  62. (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
  63. (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
  64. break;
  65. udelay(REGISTER_BUSY_DELAY);
  66. }
  67. if (i == 200)
  68. ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
  69. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  70. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  71. }
  72. #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
  73. static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  74. {
  75. void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
  76. memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
  77. iounmap(base_addr);
  78. }
  79. #else
  80. static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  81. {
  82. }
  83. #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
  84. #ifdef CONFIG_PCI
  85. static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
  86. {
  87. struct rt2x00_dev *rt2x00dev = eeprom->data;
  88. u32 reg;
  89. rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
  90. eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
  91. eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
  92. eeprom->reg_data_clock =
  93. !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
  94. eeprom->reg_chip_select =
  95. !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
  96. }
  97. static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
  98. {
  99. struct rt2x00_dev *rt2x00dev = eeprom->data;
  100. u32 reg = 0;
  101. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
  102. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
  103. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
  104. !!eeprom->reg_data_clock);
  105. rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
  106. !!eeprom->reg_chip_select);
  107. rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
  108. }
  109. static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
  110. {
  111. struct eeprom_93cx6 eeprom;
  112. u32 reg;
  113. rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
  114. eeprom.data = rt2x00dev;
  115. eeprom.register_read = rt2800pci_eepromregister_read;
  116. eeprom.register_write = rt2800pci_eepromregister_write;
  117. switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
  118. {
  119. case 0:
  120. eeprom.width = PCI_EEPROM_WIDTH_93C46;
  121. break;
  122. case 1:
  123. eeprom.width = PCI_EEPROM_WIDTH_93C66;
  124. break;
  125. default:
  126. eeprom.width = PCI_EEPROM_WIDTH_93C86;
  127. break;
  128. }
  129. eeprom.reg_data_in = 0;
  130. eeprom.reg_data_out = 0;
  131. eeprom.reg_data_clock = 0;
  132. eeprom.reg_chip_select = 0;
  133. eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
  134. EEPROM_SIZE / sizeof(u16));
  135. }
  136. static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
  137. {
  138. return rt2800_efuse_detect(rt2x00dev);
  139. }
  140. static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
  141. {
  142. rt2800_read_eeprom_efuse(rt2x00dev);
  143. }
  144. #else
  145. static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
  146. {
  147. }
  148. static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
  149. {
  150. return 0;
  151. }
  152. static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
  153. {
  154. }
  155. #endif /* CONFIG_PCI */
  156. /*
  157. * Queue handlers.
  158. */
  159. static void rt2800pci_start_queue(struct data_queue *queue)
  160. {
  161. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  162. u32 reg;
  163. switch (queue->qid) {
  164. case QID_RX:
  165. rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
  166. rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
  167. rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
  168. break;
  169. case QID_BEACON:
  170. rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  171. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
  172. rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
  173. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
  174. rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  175. rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
  176. rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
  177. rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
  178. break;
  179. default:
  180. break;
  181. }
  182. }
  183. static void rt2800pci_kick_queue(struct data_queue *queue)
  184. {
  185. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  186. struct queue_entry *entry;
  187. switch (queue->qid) {
  188. case QID_AC_VO:
  189. case QID_AC_VI:
  190. case QID_AC_BE:
  191. case QID_AC_BK:
  192. entry = rt2x00queue_get_entry(queue, Q_INDEX);
  193. rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
  194. entry->entry_idx);
  195. break;
  196. case QID_MGMT:
  197. entry = rt2x00queue_get_entry(queue, Q_INDEX);
  198. rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
  199. entry->entry_idx);
  200. break;
  201. default:
  202. break;
  203. }
  204. }
  205. static void rt2800pci_stop_queue(struct data_queue *queue)
  206. {
  207. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  208. u32 reg;
  209. switch (queue->qid) {
  210. case QID_RX:
  211. rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
  212. rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
  213. rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
  214. break;
  215. case QID_BEACON:
  216. rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  217. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
  218. rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
  219. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
  220. rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  221. rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
  222. rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
  223. rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
  224. /*
  225. * Wait for current invocation to finish. The tasklet
  226. * won't be scheduled anymore afterwards since we disabled
  227. * the TBTT and PRE TBTT timer.
  228. */
  229. tasklet_kill(&rt2x00dev->tbtt_tasklet);
  230. tasklet_kill(&rt2x00dev->pretbtt_tasklet);
  231. break;
  232. default:
  233. break;
  234. }
  235. }
  236. /*
  237. * Firmware functions
  238. */
  239. static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
  240. {
  241. return FIRMWARE_RT2860;
  242. }
  243. static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
  244. const u8 *data, const size_t len)
  245. {
  246. u32 reg;
  247. /*
  248. * enable Host program ram write selection
  249. */
  250. reg = 0;
  251. rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
  252. rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
  253. /*
  254. * Write firmware to device.
  255. */
  256. rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
  257. data, len);
  258. rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
  259. rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
  260. rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
  261. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
  262. return 0;
  263. }
  264. /*
  265. * Initialization functions.
  266. */
  267. static bool rt2800pci_get_entry_state(struct queue_entry *entry)
  268. {
  269. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  270. u32 word;
  271. if (entry->queue->qid == QID_RX) {
  272. rt2x00_desc_read(entry_priv->desc, 1, &word);
  273. return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
  274. } else {
  275. rt2x00_desc_read(entry_priv->desc, 1, &word);
  276. return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
  277. }
  278. }
  279. static void rt2800pci_clear_entry(struct queue_entry *entry)
  280. {
  281. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  282. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  283. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  284. u32 word;
  285. if (entry->queue->qid == QID_RX) {
  286. rt2x00_desc_read(entry_priv->desc, 0, &word);
  287. rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
  288. rt2x00_desc_write(entry_priv->desc, 0, word);
  289. rt2x00_desc_read(entry_priv->desc, 1, &word);
  290. rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
  291. rt2x00_desc_write(entry_priv->desc, 1, word);
  292. /*
  293. * Set RX IDX in register to inform hardware that we have
  294. * handled this entry and it is available for reuse again.
  295. */
  296. rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
  297. entry->entry_idx);
  298. } else {
  299. rt2x00_desc_read(entry_priv->desc, 1, &word);
  300. rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
  301. rt2x00_desc_write(entry_priv->desc, 1, word);
  302. }
  303. }
  304. static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
  305. {
  306. struct queue_entry_priv_pci *entry_priv;
  307. u32 reg;
  308. /*
  309. * Initialize registers.
  310. */
  311. entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
  312. rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
  313. rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
  314. rt2x00dev->tx[0].limit);
  315. rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
  316. rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
  317. entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
  318. rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
  319. rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
  320. rt2x00dev->tx[1].limit);
  321. rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
  322. rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
  323. entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
  324. rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
  325. rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
  326. rt2x00dev->tx[2].limit);
  327. rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
  328. rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
  329. entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
  330. rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
  331. rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
  332. rt2x00dev->tx[3].limit);
  333. rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
  334. rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
  335. entry_priv = rt2x00dev->rx->entries[0].priv_data;
  336. rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
  337. rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
  338. rt2x00dev->rx[0].limit);
  339. rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
  340. rt2x00dev->rx[0].limit - 1);
  341. rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
  342. /*
  343. * Enable global DMA configuration
  344. */
  345. rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
  346. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
  347. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
  348. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
  349. rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
  350. rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
  351. return 0;
  352. }
  353. /*
  354. * Device state switch handlers.
  355. */
  356. static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
  357. enum dev_state state)
  358. {
  359. u32 reg;
  360. unsigned long flags;
  361. /*
  362. * When interrupts are being enabled, the interrupt registers
  363. * should clear the register to assure a clean state.
  364. */
  365. if (state == STATE_RADIO_IRQ_ON) {
  366. rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
  367. rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
  368. }
  369. spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
  370. reg = 0;
  371. if (state == STATE_RADIO_IRQ_ON) {
  372. rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, 1);
  373. rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, 1);
  374. rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, 1);
  375. rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
  376. rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1);
  377. }
  378. rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
  379. spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
  380. if (state == STATE_RADIO_IRQ_OFF) {
  381. /*
  382. * Wait for possibly running tasklets to finish.
  383. */
  384. tasklet_kill(&rt2x00dev->txstatus_tasklet);
  385. tasklet_kill(&rt2x00dev->rxdone_tasklet);
  386. tasklet_kill(&rt2x00dev->autowake_tasklet);
  387. tasklet_kill(&rt2x00dev->tbtt_tasklet);
  388. tasklet_kill(&rt2x00dev->pretbtt_tasklet);
  389. }
  390. }
  391. static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
  392. {
  393. u32 reg;
  394. /*
  395. * Reset DMA indexes
  396. */
  397. rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
  398. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
  399. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
  400. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
  401. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
  402. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
  403. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
  404. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
  405. rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
  406. rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
  407. rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
  408. if (rt2x00_is_pcie(rt2x00dev) &&
  409. (rt2x00_rt(rt2x00dev, RT3572) ||
  410. rt2x00_rt(rt2x00dev, RT5390) ||
  411. rt2x00_rt(rt2x00dev, RT5392))) {
  412. rt2x00pci_register_read(rt2x00dev, AUX_CTRL, &reg);
  413. rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
  414. rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
  415. rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
  416. }
  417. rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
  418. reg = 0;
  419. rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
  420. rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
  421. rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
  422. rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
  423. return 0;
  424. }
  425. static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
  426. {
  427. int retval;
  428. if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
  429. rt2800pci_init_queues(rt2x00dev)))
  430. return -EIO;
  431. retval = rt2800_enable_radio(rt2x00dev);
  432. if (retval)
  433. return retval;
  434. /* After resume MCU_BOOT_SIGNAL will trash these. */
  435. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  436. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  437. rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
  438. rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
  439. rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
  440. rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
  441. return retval;
  442. }
  443. static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
  444. {
  445. if (rt2x00_is_soc(rt2x00dev)) {
  446. rt2800_disable_radio(rt2x00dev);
  447. rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
  448. rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
  449. }
  450. }
  451. static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
  452. enum dev_state state)
  453. {
  454. if (state == STATE_AWAKE) {
  455. rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
  456. 0, 0x02);
  457. rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
  458. } else if (state == STATE_SLEEP) {
  459. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
  460. 0xffffffff);
  461. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
  462. 0xffffffff);
  463. rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
  464. 0xff, 0x01);
  465. }
  466. return 0;
  467. }
  468. static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
  469. enum dev_state state)
  470. {
  471. int retval = 0;
  472. switch (state) {
  473. case STATE_RADIO_ON:
  474. retval = rt2800pci_enable_radio(rt2x00dev);
  475. break;
  476. case STATE_RADIO_OFF:
  477. /*
  478. * After the radio has been disabled, the device should
  479. * be put to sleep for powersaving.
  480. */
  481. rt2800pci_disable_radio(rt2x00dev);
  482. rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
  483. break;
  484. case STATE_RADIO_IRQ_ON:
  485. case STATE_RADIO_IRQ_OFF:
  486. rt2800pci_toggle_irq(rt2x00dev, state);
  487. break;
  488. case STATE_DEEP_SLEEP:
  489. case STATE_SLEEP:
  490. case STATE_STANDBY:
  491. case STATE_AWAKE:
  492. retval = rt2800pci_set_state(rt2x00dev, state);
  493. break;
  494. default:
  495. retval = -ENOTSUPP;
  496. break;
  497. }
  498. if (unlikely(retval))
  499. ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
  500. state, retval);
  501. return retval;
  502. }
  503. /*
  504. * TX descriptor initialization
  505. */
  506. static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
  507. {
  508. return (__le32 *) entry->skb->data;
  509. }
  510. static void rt2800pci_write_tx_desc(struct queue_entry *entry,
  511. struct txentry_desc *txdesc)
  512. {
  513. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  514. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  515. __le32 *txd = entry_priv->desc;
  516. u32 word;
  517. /*
  518. * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
  519. * must contains a TXWI structure + 802.11 header + padding + 802.11
  520. * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
  521. * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
  522. * data. It means that LAST_SEC0 is always 0.
  523. */
  524. /*
  525. * Initialize TX descriptor
  526. */
  527. word = 0;
  528. rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
  529. rt2x00_desc_write(txd, 0, word);
  530. word = 0;
  531. rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
  532. rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
  533. !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
  534. rt2x00_set_field32(&word, TXD_W1_BURST,
  535. test_bit(ENTRY_TXD_BURST, &txdesc->flags));
  536. rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
  537. rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
  538. rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
  539. rt2x00_desc_write(txd, 1, word);
  540. word = 0;
  541. rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
  542. skbdesc->skb_dma + TXWI_DESC_SIZE);
  543. rt2x00_desc_write(txd, 2, word);
  544. word = 0;
  545. rt2x00_set_field32(&word, TXD_W3_WIV,
  546. !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
  547. rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
  548. rt2x00_desc_write(txd, 3, word);
  549. /*
  550. * Register descriptor details in skb frame descriptor.
  551. */
  552. skbdesc->desc = txd;
  553. skbdesc->desc_len = TXD_DESC_SIZE;
  554. }
  555. /*
  556. * RX control handlers
  557. */
  558. static void rt2800pci_fill_rxdone(struct queue_entry *entry,
  559. struct rxdone_entry_desc *rxdesc)
  560. {
  561. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  562. __le32 *rxd = entry_priv->desc;
  563. u32 word;
  564. rt2x00_desc_read(rxd, 3, &word);
  565. if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
  566. rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
  567. /*
  568. * Unfortunately we don't know the cipher type used during
  569. * decryption. This prevents us from correct providing
  570. * correct statistics through debugfs.
  571. */
  572. rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
  573. if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
  574. /*
  575. * Hardware has stripped IV/EIV data from 802.11 frame during
  576. * decryption. Unfortunately the descriptor doesn't contain
  577. * any fields with the EIV/IV data either, so they can't
  578. * be restored by rt2x00lib.
  579. */
  580. rxdesc->flags |= RX_FLAG_IV_STRIPPED;
  581. /*
  582. * The hardware has already checked the Michael Mic and has
  583. * stripped it from the frame. Signal this to mac80211.
  584. */
  585. rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
  586. if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
  587. rxdesc->flags |= RX_FLAG_DECRYPTED;
  588. else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
  589. rxdesc->flags |= RX_FLAG_MMIC_ERROR;
  590. }
  591. if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
  592. rxdesc->dev_flags |= RXDONE_MY_BSS;
  593. if (rt2x00_get_field32(word, RXD_W3_L2PAD))
  594. rxdesc->dev_flags |= RXDONE_L2PAD;
  595. /*
  596. * Process the RXWI structure that is at the start of the buffer.
  597. */
  598. rt2800_process_rxwi(entry, rxdesc);
  599. }
  600. /*
  601. * Interrupt functions.
  602. */
  603. static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
  604. {
  605. struct ieee80211_conf conf = { .flags = 0 };
  606. struct rt2x00lib_conf libconf = { .conf = &conf };
  607. rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
  608. }
  609. static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
  610. {
  611. struct data_queue *queue;
  612. struct queue_entry *entry;
  613. u32 status;
  614. u8 qid;
  615. int max_tx_done = 16;
  616. while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
  617. qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
  618. if (unlikely(qid >= QID_RX)) {
  619. /*
  620. * Unknown queue, this shouldn't happen. Just drop
  621. * this tx status.
  622. */
  623. WARNING(rt2x00dev, "Got TX status report with "
  624. "unexpected pid %u, dropping\n", qid);
  625. break;
  626. }
  627. queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
  628. if (unlikely(queue == NULL)) {
  629. /*
  630. * The queue is NULL, this shouldn't happen. Stop
  631. * processing here and drop the tx status
  632. */
  633. WARNING(rt2x00dev, "Got TX status for an unavailable "
  634. "queue %u, dropping\n", qid);
  635. break;
  636. }
  637. if (unlikely(rt2x00queue_empty(queue))) {
  638. /*
  639. * The queue is empty. Stop processing here
  640. * and drop the tx status.
  641. */
  642. WARNING(rt2x00dev, "Got TX status for an empty "
  643. "queue %u, dropping\n", qid);
  644. break;
  645. }
  646. entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
  647. rt2800_txdone_entry(entry, status, rt2800pci_get_txwi(entry));
  648. if (--max_tx_done == 0)
  649. break;
  650. }
  651. return !max_tx_done;
  652. }
  653. static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
  654. struct rt2x00_field32 irq_field)
  655. {
  656. u32 reg;
  657. /*
  658. * Enable a single interrupt. The interrupt mask register
  659. * access needs locking.
  660. */
  661. spin_lock_irq(&rt2x00dev->irqmask_lock);
  662. rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
  663. rt2x00_set_field32(&reg, irq_field, 1);
  664. rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
  665. spin_unlock_irq(&rt2x00dev->irqmask_lock);
  666. }
  667. static void rt2800pci_txstatus_tasklet(unsigned long data)
  668. {
  669. struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
  670. if (rt2800pci_txdone(rt2x00dev))
  671. tasklet_schedule(&rt2x00dev->txstatus_tasklet);
  672. /*
  673. * No need to enable the tx status interrupt here as we always
  674. * leave it enabled to minimize the possibility of a tx status
  675. * register overflow. See comment in interrupt handler.
  676. */
  677. }
  678. static void rt2800pci_pretbtt_tasklet(unsigned long data)
  679. {
  680. struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
  681. rt2x00lib_pretbtt(rt2x00dev);
  682. if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  683. rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
  684. }
  685. static void rt2800pci_tbtt_tasklet(unsigned long data)
  686. {
  687. struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
  688. rt2x00lib_beacondone(rt2x00dev);
  689. if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  690. rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
  691. }
  692. static void rt2800pci_rxdone_tasklet(unsigned long data)
  693. {
  694. struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
  695. if (rt2x00pci_rxdone(rt2x00dev))
  696. tasklet_schedule(&rt2x00dev->rxdone_tasklet);
  697. else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  698. rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
  699. }
  700. static void rt2800pci_autowake_tasklet(unsigned long data)
  701. {
  702. struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
  703. rt2800pci_wakeup(rt2x00dev);
  704. if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  705. rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
  706. }
  707. static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
  708. {
  709. u32 status;
  710. int i;
  711. /*
  712. * The TX_FIFO_STATUS interrupt needs special care. We should
  713. * read TX_STA_FIFO but we should do it immediately as otherwise
  714. * the register can overflow and we would lose status reports.
  715. *
  716. * Hence, read the TX_STA_FIFO register and copy all tx status
  717. * reports into a kernel FIFO which is handled in the txstatus
  718. * tasklet. We use a tasklet to process the tx status reports
  719. * because we can schedule the tasklet multiple times (when the
  720. * interrupt fires again during tx status processing).
  721. *
  722. * Furthermore we don't disable the TX_FIFO_STATUS
  723. * interrupt here but leave it enabled so that the TX_STA_FIFO
  724. * can also be read while the tx status tasklet gets executed.
  725. *
  726. * Since we have only one producer and one consumer we don't
  727. * need to lock the kfifo.
  728. */
  729. for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
  730. rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
  731. if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
  732. break;
  733. if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
  734. WARNING(rt2x00dev, "TX status FIFO overrun,"
  735. "drop tx status report.\n");
  736. break;
  737. }
  738. }
  739. /* Schedule the tasklet for processing the tx status. */
  740. tasklet_schedule(&rt2x00dev->txstatus_tasklet);
  741. }
  742. static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
  743. {
  744. struct rt2x00_dev *rt2x00dev = dev_instance;
  745. u32 reg, mask;
  746. /* Read status and ACK all interrupts */
  747. rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
  748. rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
  749. if (!reg)
  750. return IRQ_NONE;
  751. if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  752. return IRQ_HANDLED;
  753. /*
  754. * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
  755. * for interrupts and interrupt masks we can just use the value of
  756. * INT_SOURCE_CSR to create the interrupt mask.
  757. */
  758. mask = ~reg;
  759. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
  760. rt2800pci_txstatus_interrupt(rt2x00dev);
  761. /*
  762. * Never disable the TX_FIFO_STATUS interrupt.
  763. */
  764. rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
  765. }
  766. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
  767. tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
  768. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
  769. tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
  770. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
  771. tasklet_schedule(&rt2x00dev->rxdone_tasklet);
  772. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
  773. tasklet_schedule(&rt2x00dev->autowake_tasklet);
  774. /*
  775. * Disable all interrupts for which a tasklet was scheduled right now,
  776. * the tasklet will reenable the appropriate interrupts.
  777. */
  778. spin_lock(&rt2x00dev->irqmask_lock);
  779. rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
  780. reg &= mask;
  781. rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
  782. spin_unlock(&rt2x00dev->irqmask_lock);
  783. return IRQ_HANDLED;
  784. }
  785. /*
  786. * Device probe functions.
  787. */
  788. static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
  789. {
  790. /*
  791. * Read EEPROM into buffer
  792. */
  793. if (rt2x00_is_soc(rt2x00dev))
  794. rt2800pci_read_eeprom_soc(rt2x00dev);
  795. else if (rt2800pci_efuse_detect(rt2x00dev))
  796. rt2800pci_read_eeprom_efuse(rt2x00dev);
  797. else
  798. rt2800pci_read_eeprom_pci(rt2x00dev);
  799. return rt2800_validate_eeprom(rt2x00dev);
  800. }
  801. static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
  802. {
  803. int retval;
  804. /*
  805. * Allocate eeprom data.
  806. */
  807. retval = rt2800pci_validate_eeprom(rt2x00dev);
  808. if (retval)
  809. return retval;
  810. retval = rt2800_init_eeprom(rt2x00dev);
  811. if (retval)
  812. return retval;
  813. /*
  814. * Initialize hw specifications.
  815. */
  816. retval = rt2800_probe_hw_mode(rt2x00dev);
  817. if (retval)
  818. return retval;
  819. /*
  820. * This device has multiple filters for control frames
  821. * and has a separate filter for PS Poll frames.
  822. */
  823. __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
  824. __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
  825. /*
  826. * This device has a pre tbtt interrupt and thus fetches
  827. * a new beacon directly prior to transmission.
  828. */
  829. __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
  830. /*
  831. * This device requires firmware.
  832. */
  833. if (!rt2x00_is_soc(rt2x00dev))
  834. __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
  835. __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
  836. __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
  837. __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
  838. __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
  839. if (!modparam_nohwcrypt)
  840. __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
  841. __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
  842. __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
  843. /*
  844. * Set the rssi offset.
  845. */
  846. rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
  847. return 0;
  848. }
  849. static const struct ieee80211_ops rt2800pci_mac80211_ops = {
  850. .tx = rt2x00mac_tx,
  851. .start = rt2x00mac_start,
  852. .stop = rt2x00mac_stop,
  853. .add_interface = rt2x00mac_add_interface,
  854. .remove_interface = rt2x00mac_remove_interface,
  855. .config = rt2x00mac_config,
  856. .configure_filter = rt2x00mac_configure_filter,
  857. .set_key = rt2x00mac_set_key,
  858. .sw_scan_start = rt2x00mac_sw_scan_start,
  859. .sw_scan_complete = rt2x00mac_sw_scan_complete,
  860. .get_stats = rt2x00mac_get_stats,
  861. .get_tkip_seq = rt2800_get_tkip_seq,
  862. .set_rts_threshold = rt2800_set_rts_threshold,
  863. .sta_add = rt2x00mac_sta_add,
  864. .sta_remove = rt2x00mac_sta_remove,
  865. .bss_info_changed = rt2x00mac_bss_info_changed,
  866. .conf_tx = rt2800_conf_tx,
  867. .get_tsf = rt2800_get_tsf,
  868. .rfkill_poll = rt2x00mac_rfkill_poll,
  869. .ampdu_action = rt2800_ampdu_action,
  870. .flush = rt2x00mac_flush,
  871. .get_survey = rt2800_get_survey,
  872. .get_ringparam = rt2x00mac_get_ringparam,
  873. .tx_frames_pending = rt2x00mac_tx_frames_pending,
  874. };
  875. static const struct rt2800_ops rt2800pci_rt2800_ops = {
  876. .register_read = rt2x00pci_register_read,
  877. .register_read_lock = rt2x00pci_register_read, /* same for PCI */
  878. .register_write = rt2x00pci_register_write,
  879. .register_write_lock = rt2x00pci_register_write, /* same for PCI */
  880. .register_multiread = rt2x00pci_register_multiread,
  881. .register_multiwrite = rt2x00pci_register_multiwrite,
  882. .regbusy_read = rt2x00pci_regbusy_read,
  883. .drv_write_firmware = rt2800pci_write_firmware,
  884. .drv_init_registers = rt2800pci_init_registers,
  885. .drv_get_txwi = rt2800pci_get_txwi,
  886. };
  887. static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
  888. .irq_handler = rt2800pci_interrupt,
  889. .txstatus_tasklet = rt2800pci_txstatus_tasklet,
  890. .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
  891. .tbtt_tasklet = rt2800pci_tbtt_tasklet,
  892. .rxdone_tasklet = rt2800pci_rxdone_tasklet,
  893. .autowake_tasklet = rt2800pci_autowake_tasklet,
  894. .probe_hw = rt2800pci_probe_hw,
  895. .get_firmware_name = rt2800pci_get_firmware_name,
  896. .check_firmware = rt2800_check_firmware,
  897. .load_firmware = rt2800_load_firmware,
  898. .initialize = rt2x00pci_initialize,
  899. .uninitialize = rt2x00pci_uninitialize,
  900. .get_entry_state = rt2800pci_get_entry_state,
  901. .clear_entry = rt2800pci_clear_entry,
  902. .set_device_state = rt2800pci_set_device_state,
  903. .rfkill_poll = rt2800_rfkill_poll,
  904. .link_stats = rt2800_link_stats,
  905. .reset_tuner = rt2800_reset_tuner,
  906. .link_tuner = rt2800_link_tuner,
  907. .gain_calibration = rt2800_gain_calibration,
  908. .vco_calibration = rt2800_vco_calibration,
  909. .start_queue = rt2800pci_start_queue,
  910. .kick_queue = rt2800pci_kick_queue,
  911. .stop_queue = rt2800pci_stop_queue,
  912. .flush_queue = rt2x00pci_flush_queue,
  913. .write_tx_desc = rt2800pci_write_tx_desc,
  914. .write_tx_data = rt2800_write_tx_data,
  915. .write_beacon = rt2800_write_beacon,
  916. .clear_beacon = rt2800_clear_beacon,
  917. .fill_rxdone = rt2800pci_fill_rxdone,
  918. .config_shared_key = rt2800_config_shared_key,
  919. .config_pairwise_key = rt2800_config_pairwise_key,
  920. .config_filter = rt2800_config_filter,
  921. .config_intf = rt2800_config_intf,
  922. .config_erp = rt2800_config_erp,
  923. .config_ant = rt2800_config_ant,
  924. .config = rt2800_config,
  925. .sta_add = rt2800_sta_add,
  926. .sta_remove = rt2800_sta_remove,
  927. };
  928. static const struct data_queue_desc rt2800pci_queue_rx = {
  929. .entry_num = 128,
  930. .data_size = AGGREGATION_SIZE,
  931. .desc_size = RXD_DESC_SIZE,
  932. .priv_size = sizeof(struct queue_entry_priv_pci),
  933. };
  934. static const struct data_queue_desc rt2800pci_queue_tx = {
  935. .entry_num = 64,
  936. .data_size = AGGREGATION_SIZE,
  937. .desc_size = TXD_DESC_SIZE,
  938. .priv_size = sizeof(struct queue_entry_priv_pci),
  939. };
  940. static const struct data_queue_desc rt2800pci_queue_bcn = {
  941. .entry_num = 8,
  942. .data_size = 0, /* No DMA required for beacons */
  943. .desc_size = TXWI_DESC_SIZE,
  944. .priv_size = sizeof(struct queue_entry_priv_pci),
  945. };
  946. static const struct rt2x00_ops rt2800pci_ops = {
  947. .name = KBUILD_MODNAME,
  948. .drv_data_size = sizeof(struct rt2800_drv_data),
  949. .max_sta_intf = 1,
  950. .max_ap_intf = 8,
  951. .eeprom_size = EEPROM_SIZE,
  952. .rf_size = RF_SIZE,
  953. .tx_queues = NUM_TX_QUEUES,
  954. .extra_tx_headroom = TXWI_DESC_SIZE,
  955. .rx = &rt2800pci_queue_rx,
  956. .tx = &rt2800pci_queue_tx,
  957. .bcn = &rt2800pci_queue_bcn,
  958. .lib = &rt2800pci_rt2x00_ops,
  959. .drv = &rt2800pci_rt2800_ops,
  960. .hw = &rt2800pci_mac80211_ops,
  961. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  962. .debugfs = &rt2800_rt2x00debug,
  963. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  964. };
  965. /*
  966. * RT2800pci module information.
  967. */
  968. #ifdef CONFIG_PCI
  969. static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
  970. { PCI_DEVICE(0x1814, 0x0601) },
  971. { PCI_DEVICE(0x1814, 0x0681) },
  972. { PCI_DEVICE(0x1814, 0x0701) },
  973. { PCI_DEVICE(0x1814, 0x0781) },
  974. { PCI_DEVICE(0x1814, 0x3090) },
  975. { PCI_DEVICE(0x1814, 0x3091) },
  976. { PCI_DEVICE(0x1814, 0x3092) },
  977. { PCI_DEVICE(0x1432, 0x7708) },
  978. { PCI_DEVICE(0x1432, 0x7727) },
  979. { PCI_DEVICE(0x1432, 0x7728) },
  980. { PCI_DEVICE(0x1432, 0x7738) },
  981. { PCI_DEVICE(0x1432, 0x7748) },
  982. { PCI_DEVICE(0x1432, 0x7758) },
  983. { PCI_DEVICE(0x1432, 0x7768) },
  984. { PCI_DEVICE(0x1462, 0x891a) },
  985. { PCI_DEVICE(0x1a3b, 0x1059) },
  986. #ifdef CONFIG_RT2800PCI_RT33XX
  987. { PCI_DEVICE(0x1814, 0x3390) },
  988. #endif
  989. #ifdef CONFIG_RT2800PCI_RT35XX
  990. { PCI_DEVICE(0x1432, 0x7711) },
  991. { PCI_DEVICE(0x1432, 0x7722) },
  992. { PCI_DEVICE(0x1814, 0x3060) },
  993. { PCI_DEVICE(0x1814, 0x3062) },
  994. { PCI_DEVICE(0x1814, 0x3562) },
  995. { PCI_DEVICE(0x1814, 0x3592) },
  996. { PCI_DEVICE(0x1814, 0x3593) },
  997. #endif
  998. #ifdef CONFIG_RT2800PCI_RT53XX
  999. { PCI_DEVICE(0x1814, 0x5390) },
  1000. { PCI_DEVICE(0x1814, 0x539a) },
  1001. { PCI_DEVICE(0x1814, 0x539f) },
  1002. #endif
  1003. { 0, }
  1004. };
  1005. #endif /* CONFIG_PCI */
  1006. MODULE_AUTHOR(DRV_PROJECT);
  1007. MODULE_VERSION(DRV_VERSION);
  1008. MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
  1009. MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
  1010. #ifdef CONFIG_PCI
  1011. MODULE_FIRMWARE(FIRMWARE_RT2860);
  1012. MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
  1013. #endif /* CONFIG_PCI */
  1014. MODULE_LICENSE("GPL");
  1015. #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
  1016. static int rt2800soc_probe(struct platform_device *pdev)
  1017. {
  1018. return rt2x00soc_probe(pdev, &rt2800pci_ops);
  1019. }
  1020. static struct platform_driver rt2800soc_driver = {
  1021. .driver = {
  1022. .name = "rt2800_wmac",
  1023. .owner = THIS_MODULE,
  1024. .mod_name = KBUILD_MODNAME,
  1025. },
  1026. .probe = rt2800soc_probe,
  1027. .remove = __devexit_p(rt2x00soc_remove),
  1028. .suspend = rt2x00soc_suspend,
  1029. .resume = rt2x00soc_resume,
  1030. };
  1031. #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
  1032. #ifdef CONFIG_PCI
  1033. static int rt2800pci_probe(struct pci_dev *pci_dev,
  1034. const struct pci_device_id *id)
  1035. {
  1036. return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
  1037. }
  1038. static struct pci_driver rt2800pci_driver = {
  1039. .name = KBUILD_MODNAME,
  1040. .id_table = rt2800pci_device_table,
  1041. .probe = rt2800pci_probe,
  1042. .remove = __devexit_p(rt2x00pci_remove),
  1043. .suspend = rt2x00pci_suspend,
  1044. .resume = rt2x00pci_resume,
  1045. };
  1046. #endif /* CONFIG_PCI */
  1047. static int __init rt2800pci_init(void)
  1048. {
  1049. int ret = 0;
  1050. #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
  1051. ret = platform_driver_register(&rt2800soc_driver);
  1052. if (ret)
  1053. return ret;
  1054. #endif
  1055. #ifdef CONFIG_PCI
  1056. ret = pci_register_driver(&rt2800pci_driver);
  1057. if (ret) {
  1058. #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
  1059. platform_driver_unregister(&rt2800soc_driver);
  1060. #endif
  1061. return ret;
  1062. }
  1063. #endif
  1064. return ret;
  1065. }
  1066. static void __exit rt2800pci_exit(void)
  1067. {
  1068. #ifdef CONFIG_PCI
  1069. pci_unregister_driver(&rt2800pci_driver);
  1070. #endif
  1071. #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
  1072. platform_driver_unregister(&rt2800soc_driver);
  1073. #endif
  1074. }
  1075. module_init(rt2800pci_init);
  1076. module_exit(rt2800pci_exit);