init.c 41 KB

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  1. /*
  2. * Copyright (c) 2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/moduleparam.h>
  17. #include <linux/errno.h>
  18. #include <linux/export.h>
  19. #include <linux/of.h>
  20. #include <linux/mmc/sdio_func.h>
  21. #include "core.h"
  22. #include "cfg80211.h"
  23. #include "target.h"
  24. #include "debug.h"
  25. #include "hif-ops.h"
  26. static const struct ath6kl_hw hw_list[] = {
  27. {
  28. .id = AR6003_HW_2_0_VERSION,
  29. .name = "ar6003 hw 2.0",
  30. .dataset_patch_addr = 0x57e884,
  31. .app_load_addr = 0x543180,
  32. .board_ext_data_addr = 0x57e500,
  33. .reserved_ram_size = 6912,
  34. .refclk_hz = 26000000,
  35. .uarttx_pin = 8,
  36. /* hw2.0 needs override address hardcoded */
  37. .app_start_override_addr = 0x944C00,
  38. .fw = {
  39. .dir = AR6003_HW_2_0_FW_DIR,
  40. .otp = AR6003_HW_2_0_OTP_FILE,
  41. .fw = AR6003_HW_2_0_FIRMWARE_FILE,
  42. .tcmd = AR6003_HW_2_0_TCMD_FIRMWARE_FILE,
  43. .patch = AR6003_HW_2_0_PATCH_FILE,
  44. },
  45. .fw_board = AR6003_HW_2_0_BOARD_DATA_FILE,
  46. .fw_default_board = AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE,
  47. },
  48. {
  49. .id = AR6003_HW_2_1_1_VERSION,
  50. .name = "ar6003 hw 2.1.1",
  51. .dataset_patch_addr = 0x57ff74,
  52. .app_load_addr = 0x1234,
  53. .board_ext_data_addr = 0x542330,
  54. .reserved_ram_size = 512,
  55. .refclk_hz = 26000000,
  56. .uarttx_pin = 8,
  57. .testscript_addr = 0x57ef74,
  58. .fw = {
  59. .dir = AR6003_HW_2_1_1_FW_DIR,
  60. .otp = AR6003_HW_2_1_1_OTP_FILE,
  61. .fw = AR6003_HW_2_1_1_FIRMWARE_FILE,
  62. .tcmd = AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE,
  63. .patch = AR6003_HW_2_1_1_PATCH_FILE,
  64. .utf = AR6003_HW_2_1_1_UTF_FIRMWARE_FILE,
  65. .testscript = AR6003_HW_2_1_1_TESTSCRIPT_FILE,
  66. },
  67. .fw_board = AR6003_HW_2_1_1_BOARD_DATA_FILE,
  68. .fw_default_board = AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE,
  69. },
  70. {
  71. .id = AR6004_HW_1_0_VERSION,
  72. .name = "ar6004 hw 1.0",
  73. .dataset_patch_addr = 0x57e884,
  74. .app_load_addr = 0x1234,
  75. .board_ext_data_addr = 0x437000,
  76. .reserved_ram_size = 19456,
  77. .board_addr = 0x433900,
  78. .refclk_hz = 26000000,
  79. .uarttx_pin = 11,
  80. .fw = {
  81. .dir = AR6004_HW_1_0_FW_DIR,
  82. .fw = AR6004_HW_1_0_FIRMWARE_FILE,
  83. },
  84. .fw_board = AR6004_HW_1_0_BOARD_DATA_FILE,
  85. .fw_default_board = AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE,
  86. },
  87. {
  88. .id = AR6004_HW_1_1_VERSION,
  89. .name = "ar6004 hw 1.1",
  90. .dataset_patch_addr = 0x57e884,
  91. .app_load_addr = 0x1234,
  92. .board_ext_data_addr = 0x437000,
  93. .reserved_ram_size = 11264,
  94. .board_addr = 0x43d400,
  95. .refclk_hz = 40000000,
  96. .uarttx_pin = 11,
  97. .fw = {
  98. .dir = AR6004_HW_1_1_FW_DIR,
  99. .fw = AR6004_HW_1_1_FIRMWARE_FILE,
  100. },
  101. .fw_board = AR6004_HW_1_1_BOARD_DATA_FILE,
  102. .fw_default_board = AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE,
  103. },
  104. };
  105. /*
  106. * Include definitions here that can be used to tune the WLAN module
  107. * behavior. Different customers can tune the behavior as per their needs,
  108. * here.
  109. */
  110. /*
  111. * This configuration item enable/disable keepalive support.
  112. * Keepalive support: In the absence of any data traffic to AP, null
  113. * frames will be sent to the AP at periodic interval, to keep the association
  114. * active. This configuration item defines the periodic interval.
  115. * Use value of zero to disable keepalive support
  116. * Default: 60 seconds
  117. */
  118. #define WLAN_CONFIG_KEEP_ALIVE_INTERVAL 60
  119. /*
  120. * This configuration item sets the value of disconnect timeout
  121. * Firmware delays sending the disconnec event to the host for this
  122. * timeout after is gets disconnected from the current AP.
  123. * If the firmware successly roams within the disconnect timeout
  124. * it sends a new connect event
  125. */
  126. #define WLAN_CONFIG_DISCONNECT_TIMEOUT 10
  127. #define ATH6KL_DATA_OFFSET 64
  128. struct sk_buff *ath6kl_buf_alloc(int size)
  129. {
  130. struct sk_buff *skb;
  131. u16 reserved;
  132. /* Add chacheline space at front and back of buffer */
  133. reserved = (2 * L1_CACHE_BYTES) + ATH6KL_DATA_OFFSET +
  134. sizeof(struct htc_packet) + ATH6KL_HTC_ALIGN_BYTES;
  135. skb = dev_alloc_skb(size + reserved);
  136. if (skb)
  137. skb_reserve(skb, reserved - L1_CACHE_BYTES);
  138. return skb;
  139. }
  140. void ath6kl_init_profile_info(struct ath6kl_vif *vif)
  141. {
  142. vif->ssid_len = 0;
  143. memset(vif->ssid, 0, sizeof(vif->ssid));
  144. vif->dot11_auth_mode = OPEN_AUTH;
  145. vif->auth_mode = NONE_AUTH;
  146. vif->prwise_crypto = NONE_CRYPT;
  147. vif->prwise_crypto_len = 0;
  148. vif->grp_crypto = NONE_CRYPT;
  149. vif->grp_crypto_len = 0;
  150. memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
  151. memset(vif->req_bssid, 0, sizeof(vif->req_bssid));
  152. memset(vif->bssid, 0, sizeof(vif->bssid));
  153. vif->bss_ch = 0;
  154. }
  155. static int ath6kl_set_host_app_area(struct ath6kl *ar)
  156. {
  157. u32 address, data;
  158. struct host_app_area host_app_area;
  159. /* Fetch the address of the host_app_area_s
  160. * instance in the host interest area */
  161. address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest));
  162. address = TARG_VTOP(ar->target_type, address);
  163. if (ath6kl_diag_read32(ar, address, &data))
  164. return -EIO;
  165. address = TARG_VTOP(ar->target_type, data);
  166. host_app_area.wmi_protocol_ver = cpu_to_le32(WMI_PROTOCOL_VERSION);
  167. if (ath6kl_diag_write(ar, address, (u8 *) &host_app_area,
  168. sizeof(struct host_app_area)))
  169. return -EIO;
  170. return 0;
  171. }
  172. static inline void set_ac2_ep_map(struct ath6kl *ar,
  173. u8 ac,
  174. enum htc_endpoint_id ep)
  175. {
  176. ar->ac2ep_map[ac] = ep;
  177. ar->ep2ac_map[ep] = ac;
  178. }
  179. /* connect to a service */
  180. static int ath6kl_connectservice(struct ath6kl *ar,
  181. struct htc_service_connect_req *con_req,
  182. char *desc)
  183. {
  184. int status;
  185. struct htc_service_connect_resp response;
  186. memset(&response, 0, sizeof(response));
  187. status = ath6kl_htc_conn_service(ar->htc_target, con_req, &response);
  188. if (status) {
  189. ath6kl_err("failed to connect to %s service status:%d\n",
  190. desc, status);
  191. return status;
  192. }
  193. switch (con_req->svc_id) {
  194. case WMI_CONTROL_SVC:
  195. if (test_bit(WMI_ENABLED, &ar->flag))
  196. ath6kl_wmi_set_control_ep(ar->wmi, response.endpoint);
  197. ar->ctrl_ep = response.endpoint;
  198. break;
  199. case WMI_DATA_BE_SVC:
  200. set_ac2_ep_map(ar, WMM_AC_BE, response.endpoint);
  201. break;
  202. case WMI_DATA_BK_SVC:
  203. set_ac2_ep_map(ar, WMM_AC_BK, response.endpoint);
  204. break;
  205. case WMI_DATA_VI_SVC:
  206. set_ac2_ep_map(ar, WMM_AC_VI, response.endpoint);
  207. break;
  208. case WMI_DATA_VO_SVC:
  209. set_ac2_ep_map(ar, WMM_AC_VO, response.endpoint);
  210. break;
  211. default:
  212. ath6kl_err("service id is not mapped %d\n", con_req->svc_id);
  213. return -EINVAL;
  214. }
  215. return 0;
  216. }
  217. static int ath6kl_init_service_ep(struct ath6kl *ar)
  218. {
  219. struct htc_service_connect_req connect;
  220. memset(&connect, 0, sizeof(connect));
  221. /* these fields are the same for all service endpoints */
  222. connect.ep_cb.rx = ath6kl_rx;
  223. connect.ep_cb.rx_refill = ath6kl_rx_refill;
  224. connect.ep_cb.tx_full = ath6kl_tx_queue_full;
  225. /*
  226. * Set the max queue depth so that our ath6kl_tx_queue_full handler
  227. * gets called.
  228. */
  229. connect.max_txq_depth = MAX_DEFAULT_SEND_QUEUE_DEPTH;
  230. connect.ep_cb.rx_refill_thresh = ATH6KL_MAX_RX_BUFFERS / 4;
  231. if (!connect.ep_cb.rx_refill_thresh)
  232. connect.ep_cb.rx_refill_thresh++;
  233. /* connect to control service */
  234. connect.svc_id = WMI_CONTROL_SVC;
  235. if (ath6kl_connectservice(ar, &connect, "WMI CONTROL"))
  236. return -EIO;
  237. connect.flags |= HTC_FLGS_TX_BNDL_PAD_EN;
  238. /*
  239. * Limit the HTC message size on the send path, although e can
  240. * receive A-MSDU frames of 4K, we will only send ethernet-sized
  241. * (802.3) frames on the send path.
  242. */
  243. connect.max_rxmsg_sz = WMI_MAX_TX_DATA_FRAME_LENGTH;
  244. /*
  245. * To reduce the amount of committed memory for larger A_MSDU
  246. * frames, use the recv-alloc threshold mechanism for larger
  247. * packets.
  248. */
  249. connect.ep_cb.rx_alloc_thresh = ATH6KL_BUFFER_SIZE;
  250. connect.ep_cb.rx_allocthresh = ath6kl_alloc_amsdu_rxbuf;
  251. /*
  252. * For the remaining data services set the connection flag to
  253. * reduce dribbling, if configured to do so.
  254. */
  255. connect.conn_flags |= HTC_CONN_FLGS_REDUCE_CRED_DRIB;
  256. connect.conn_flags &= ~HTC_CONN_FLGS_THRESH_MASK;
  257. connect.conn_flags |= HTC_CONN_FLGS_THRESH_LVL_HALF;
  258. connect.svc_id = WMI_DATA_BE_SVC;
  259. if (ath6kl_connectservice(ar, &connect, "WMI DATA BE"))
  260. return -EIO;
  261. /* connect to back-ground map this to WMI LOW_PRI */
  262. connect.svc_id = WMI_DATA_BK_SVC;
  263. if (ath6kl_connectservice(ar, &connect, "WMI DATA BK"))
  264. return -EIO;
  265. /* connect to Video service, map this to to HI PRI */
  266. connect.svc_id = WMI_DATA_VI_SVC;
  267. if (ath6kl_connectservice(ar, &connect, "WMI DATA VI"))
  268. return -EIO;
  269. /*
  270. * Connect to VO service, this is currently not mapped to a WMI
  271. * priority stream due to historical reasons. WMI originally
  272. * defined 3 priorities over 3 mailboxes We can change this when
  273. * WMI is reworked so that priorities are not dependent on
  274. * mailboxes.
  275. */
  276. connect.svc_id = WMI_DATA_VO_SVC;
  277. if (ath6kl_connectservice(ar, &connect, "WMI DATA VO"))
  278. return -EIO;
  279. return 0;
  280. }
  281. void ath6kl_init_control_info(struct ath6kl_vif *vif)
  282. {
  283. ath6kl_init_profile_info(vif);
  284. vif->def_txkey_index = 0;
  285. memset(vif->wep_key_list, 0, sizeof(vif->wep_key_list));
  286. vif->ch_hint = 0;
  287. }
  288. /*
  289. * Set HTC/Mbox operational parameters, this can only be called when the
  290. * target is in the BMI phase.
  291. */
  292. static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val,
  293. u8 htc_ctrl_buf)
  294. {
  295. int status;
  296. u32 blk_size;
  297. blk_size = ar->mbox_info.block_size;
  298. if (htc_ctrl_buf)
  299. blk_size |= ((u32)htc_ctrl_buf) << 16;
  300. /* set the host interest area for the block size */
  301. status = ath6kl_bmi_write(ar,
  302. ath6kl_get_hi_item_addr(ar,
  303. HI_ITEM(hi_mbox_io_block_sz)),
  304. (u8 *)&blk_size,
  305. 4);
  306. if (status) {
  307. ath6kl_err("bmi_write_memory for IO block size failed\n");
  308. goto out;
  309. }
  310. ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n",
  311. blk_size,
  312. ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz)));
  313. if (mbox_isr_yield_val) {
  314. /* set the host interest area for the mbox ISR yield limit */
  315. status = ath6kl_bmi_write(ar,
  316. ath6kl_get_hi_item_addr(ar,
  317. HI_ITEM(hi_mbox_isr_yield_limit)),
  318. (u8 *)&mbox_isr_yield_val,
  319. 4);
  320. if (status) {
  321. ath6kl_err("bmi_write_memory for yield limit failed\n");
  322. goto out;
  323. }
  324. }
  325. out:
  326. return status;
  327. }
  328. static int ath6kl_target_config_wlan_params(struct ath6kl *ar, int idx)
  329. {
  330. int status = 0;
  331. int ret;
  332. /*
  333. * Configure the device for rx dot11 header rules. "0,0" are the
  334. * default values. Required if checksum offload is needed. Set
  335. * RxMetaVersion to 2.
  336. */
  337. if (ath6kl_wmi_set_rx_frame_format_cmd(ar->wmi, idx,
  338. ar->rx_meta_ver, 0, 0)) {
  339. ath6kl_err("unable to set the rx frame format\n");
  340. status = -EIO;
  341. }
  342. if (ar->conf_flags & ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN)
  343. if ((ath6kl_wmi_pmparams_cmd(ar->wmi, idx, 0, 1, 0, 0, 1,
  344. IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN)) != 0) {
  345. ath6kl_err("unable to set power save fail event policy\n");
  346. status = -EIO;
  347. }
  348. if (!(ar->conf_flags & ATH6KL_CONF_IGNORE_ERP_BARKER))
  349. if ((ath6kl_wmi_set_lpreamble_cmd(ar->wmi, idx, 0,
  350. WMI_DONOT_IGNORE_BARKER_IN_ERP)) != 0) {
  351. ath6kl_err("unable to set barker preamble policy\n");
  352. status = -EIO;
  353. }
  354. if (ath6kl_wmi_set_keepalive_cmd(ar->wmi, idx,
  355. WLAN_CONFIG_KEEP_ALIVE_INTERVAL)) {
  356. ath6kl_err("unable to set keep alive interval\n");
  357. status = -EIO;
  358. }
  359. if (ath6kl_wmi_disctimeout_cmd(ar->wmi, idx,
  360. WLAN_CONFIG_DISCONNECT_TIMEOUT)) {
  361. ath6kl_err("unable to set disconnect timeout\n");
  362. status = -EIO;
  363. }
  364. if (!(ar->conf_flags & ATH6KL_CONF_ENABLE_TX_BURST))
  365. if (ath6kl_wmi_set_wmm_txop(ar->wmi, idx, WMI_TXOP_DISABLED)) {
  366. ath6kl_err("unable to set txop bursting\n");
  367. status = -EIO;
  368. }
  369. if (ar->p2p && (ar->vif_max == 1 || idx)) {
  370. ret = ath6kl_wmi_info_req_cmd(ar->wmi, idx,
  371. P2P_FLAG_CAPABILITIES_REQ |
  372. P2P_FLAG_MACADDR_REQ |
  373. P2P_FLAG_HMODEL_REQ);
  374. if (ret) {
  375. ath6kl_dbg(ATH6KL_DBG_TRC, "failed to request P2P "
  376. "capabilities (%d) - assuming P2P not "
  377. "supported\n", ret);
  378. ar->p2p = false;
  379. }
  380. }
  381. if (ar->p2p && (ar->vif_max == 1 || idx)) {
  382. /* Enable Probe Request reporting for P2P */
  383. ret = ath6kl_wmi_probe_report_req_cmd(ar->wmi, idx, true);
  384. if (ret) {
  385. ath6kl_dbg(ATH6KL_DBG_TRC, "failed to enable Probe "
  386. "Request reporting (%d)\n", ret);
  387. }
  388. }
  389. return status;
  390. }
  391. int ath6kl_configure_target(struct ath6kl *ar)
  392. {
  393. u32 param, ram_reserved_size;
  394. u8 fw_iftype, fw_mode = 0, fw_submode = 0;
  395. int i, status;
  396. param = !!(ar->conf_flags & ATH6KL_CONF_UART_DEBUG);
  397. if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar,
  398. HI_ITEM(hi_serial_enable)), (u8 *)&param, 4)) {
  399. ath6kl_err("bmi_write_memory for uart debug failed\n");
  400. return -EIO;
  401. }
  402. /*
  403. * Note: Even though the firmware interface type is
  404. * chosen as BSS_STA for all three interfaces, can
  405. * be configured to IBSS/AP as long as the fw submode
  406. * remains normal mode (0 - AP, STA and IBSS). But
  407. * due to an target assert in firmware only one interface is
  408. * configured for now.
  409. */
  410. fw_iftype = HI_OPTION_FW_MODE_BSS_STA;
  411. for (i = 0; i < ar->vif_max; i++)
  412. fw_mode |= fw_iftype << (i * HI_OPTION_FW_MODE_BITS);
  413. /*
  414. * By default, submodes :
  415. * vif[0] - AP/STA/IBSS
  416. * vif[1] - "P2P dev"/"P2P GO"/"P2P Client"
  417. * vif[2] - "P2P dev"/"P2P GO"/"P2P Client"
  418. */
  419. for (i = 0; i < ar->max_norm_iface; i++)
  420. fw_submode |= HI_OPTION_FW_SUBMODE_NONE <<
  421. (i * HI_OPTION_FW_SUBMODE_BITS);
  422. for (i = ar->max_norm_iface; i < ar->vif_max; i++)
  423. fw_submode |= HI_OPTION_FW_SUBMODE_P2PDEV <<
  424. (i * HI_OPTION_FW_SUBMODE_BITS);
  425. if (ar->p2p && ar->vif_max == 1)
  426. fw_submode = HI_OPTION_FW_SUBMODE_P2PDEV;
  427. param = HTC_PROTOCOL_VERSION;
  428. if (ath6kl_bmi_write(ar,
  429. ath6kl_get_hi_item_addr(ar,
  430. HI_ITEM(hi_app_host_interest)),
  431. (u8 *)&param, 4) != 0) {
  432. ath6kl_err("bmi_write_memory for htc version failed\n");
  433. return -EIO;
  434. }
  435. /* set the firmware mode to STA/IBSS/AP */
  436. param = 0;
  437. if (ath6kl_bmi_read(ar,
  438. ath6kl_get_hi_item_addr(ar,
  439. HI_ITEM(hi_option_flag)),
  440. (u8 *)&param, 4) != 0) {
  441. ath6kl_err("bmi_read_memory for setting fwmode failed\n");
  442. return -EIO;
  443. }
  444. param |= (ar->vif_max << HI_OPTION_NUM_DEV_SHIFT);
  445. param |= fw_mode << HI_OPTION_FW_MODE_SHIFT;
  446. param |= fw_submode << HI_OPTION_FW_SUBMODE_SHIFT;
  447. param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  448. param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  449. if (ath6kl_bmi_write(ar,
  450. ath6kl_get_hi_item_addr(ar,
  451. HI_ITEM(hi_option_flag)),
  452. (u8 *)&param,
  453. 4) != 0) {
  454. ath6kl_err("bmi_write_memory for setting fwmode failed\n");
  455. return -EIO;
  456. }
  457. ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n");
  458. /*
  459. * Hardcode the address use for the extended board data
  460. * Ideally this should be pre-allocate by the OS at boot time
  461. * But since it is a new feature and board data is loaded
  462. * at init time, we have to workaround this from host.
  463. * It is difficult to patch the firmware boot code,
  464. * but possible in theory.
  465. */
  466. param = ar->hw.board_ext_data_addr;
  467. ram_reserved_size = ar->hw.reserved_ram_size;
  468. if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar,
  469. HI_ITEM(hi_board_ext_data)),
  470. (u8 *)&param, 4) != 0) {
  471. ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n");
  472. return -EIO;
  473. }
  474. if (ath6kl_bmi_write(ar, ath6kl_get_hi_item_addr(ar,
  475. HI_ITEM(hi_end_ram_reserve_sz)),
  476. (u8 *)&ram_reserved_size, 4) != 0) {
  477. ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n");
  478. return -EIO;
  479. }
  480. /* set the block size for the target */
  481. if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0))
  482. /* use default number of control buffers */
  483. return -EIO;
  484. /* Configure GPIO AR600x UART */
  485. param = ar->hw.uarttx_pin;
  486. status = ath6kl_bmi_write(ar,
  487. ath6kl_get_hi_item_addr(ar,
  488. HI_ITEM(hi_dbg_uart_txpin)),
  489. (u8 *)&param, 4);
  490. if (status)
  491. return status;
  492. /* Configure target refclk_hz */
  493. param = ar->hw.refclk_hz;
  494. status = ath6kl_bmi_write(ar,
  495. ath6kl_get_hi_item_addr(ar,
  496. HI_ITEM(hi_refclk_hz)),
  497. (u8 *)&param, 4);
  498. if (status)
  499. return status;
  500. return 0;
  501. }
  502. /* firmware upload */
  503. static int ath6kl_get_fw(struct ath6kl *ar, const char *filename,
  504. u8 **fw, size_t *fw_len)
  505. {
  506. const struct firmware *fw_entry;
  507. int ret;
  508. ret = request_firmware(&fw_entry, filename, ar->dev);
  509. if (ret)
  510. return ret;
  511. *fw_len = fw_entry->size;
  512. *fw = kmemdup(fw_entry->data, fw_entry->size, GFP_KERNEL);
  513. if (*fw == NULL)
  514. ret = -ENOMEM;
  515. release_firmware(fw_entry);
  516. return ret;
  517. }
  518. #ifdef CONFIG_OF
  519. /*
  520. * Check the device tree for a board-id and use it to construct
  521. * the pathname to the firmware file. Used (for now) to find a
  522. * fallback to the "bdata.bin" file--typically a symlink to the
  523. * appropriate board-specific file.
  524. */
  525. static bool check_device_tree(struct ath6kl *ar)
  526. {
  527. static const char *board_id_prop = "atheros,board-id";
  528. struct device_node *node;
  529. char board_filename[64];
  530. const char *board_id;
  531. int ret;
  532. for_each_compatible_node(node, NULL, "atheros,ath6kl") {
  533. board_id = of_get_property(node, board_id_prop, NULL);
  534. if (board_id == NULL) {
  535. ath6kl_warn("No \"%s\" property on %s node.\n",
  536. board_id_prop, node->name);
  537. continue;
  538. }
  539. snprintf(board_filename, sizeof(board_filename),
  540. "%s/bdata.%s.bin", ar->hw.fw.dir, board_id);
  541. ret = ath6kl_get_fw(ar, board_filename, &ar->fw_board,
  542. &ar->fw_board_len);
  543. if (ret) {
  544. ath6kl_err("Failed to get DT board file %s: %d\n",
  545. board_filename, ret);
  546. continue;
  547. }
  548. return true;
  549. }
  550. return false;
  551. }
  552. #else
  553. static bool check_device_tree(struct ath6kl *ar)
  554. {
  555. return false;
  556. }
  557. #endif /* CONFIG_OF */
  558. static int ath6kl_fetch_board_file(struct ath6kl *ar)
  559. {
  560. const char *filename;
  561. int ret;
  562. if (ar->fw_board != NULL)
  563. return 0;
  564. if (WARN_ON(ar->hw.fw_board == NULL))
  565. return -EINVAL;
  566. filename = ar->hw.fw_board;
  567. ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
  568. &ar->fw_board_len);
  569. if (ret == 0) {
  570. /* managed to get proper board file */
  571. return 0;
  572. }
  573. if (check_device_tree(ar)) {
  574. /* got board file from device tree */
  575. return 0;
  576. }
  577. /* there was no proper board file, try to use default instead */
  578. ath6kl_warn("Failed to get board file %s (%d), trying to find default board file.\n",
  579. filename, ret);
  580. filename = ar->hw.fw_default_board;
  581. ret = ath6kl_get_fw(ar, filename, &ar->fw_board,
  582. &ar->fw_board_len);
  583. if (ret) {
  584. ath6kl_err("Failed to get default board file %s: %d\n",
  585. filename, ret);
  586. return ret;
  587. }
  588. ath6kl_warn("WARNING! No proper board file was not found, instead using a default board file.\n");
  589. ath6kl_warn("Most likely your hardware won't work as specified. Install correct board file!\n");
  590. return 0;
  591. }
  592. static int ath6kl_fetch_otp_file(struct ath6kl *ar)
  593. {
  594. char filename[100];
  595. int ret;
  596. if (ar->fw_otp != NULL)
  597. return 0;
  598. if (ar->hw.fw.otp == NULL) {
  599. ath6kl_dbg(ATH6KL_DBG_BOOT,
  600. "no OTP file configured for this hw\n");
  601. return 0;
  602. }
  603. snprintf(filename, sizeof(filename), "%s/%s",
  604. ar->hw.fw.dir, ar->hw.fw.otp);
  605. ret = ath6kl_get_fw(ar, filename, &ar->fw_otp,
  606. &ar->fw_otp_len);
  607. if (ret) {
  608. ath6kl_err("Failed to get OTP file %s: %d\n",
  609. filename, ret);
  610. return ret;
  611. }
  612. return 0;
  613. }
  614. static int ath6kl_fetch_testmode_file(struct ath6kl *ar)
  615. {
  616. char filename[100];
  617. int ret;
  618. if (ar->testmode == 0)
  619. return 0;
  620. ath6kl_dbg(ATH6KL_DBG_BOOT, "testmode %d\n", ar->testmode);
  621. if (ar->testmode == 2) {
  622. if (ar->hw.fw.utf == NULL) {
  623. ath6kl_warn("testmode 2 not supported\n");
  624. return -EOPNOTSUPP;
  625. }
  626. snprintf(filename, sizeof(filename), "%s/%s",
  627. ar->hw.fw.dir, ar->hw.fw.utf);
  628. } else {
  629. if (ar->hw.fw.tcmd == NULL) {
  630. ath6kl_warn("testmode 1 not supported\n");
  631. return -EOPNOTSUPP;
  632. }
  633. snprintf(filename, sizeof(filename), "%s/%s",
  634. ar->hw.fw.dir, ar->hw.fw.tcmd);
  635. }
  636. set_bit(TESTMODE, &ar->flag);
  637. ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
  638. if (ret) {
  639. ath6kl_err("Failed to get testmode %d firmware file %s: %d\n",
  640. ar->testmode, filename, ret);
  641. return ret;
  642. }
  643. return 0;
  644. }
  645. static int ath6kl_fetch_fw_file(struct ath6kl *ar)
  646. {
  647. char filename[100];
  648. int ret;
  649. if (ar->fw != NULL)
  650. return 0;
  651. /* FIXME: remove WARN_ON() as we won't support FW API 1 for long */
  652. if (WARN_ON(ar->hw.fw.fw == NULL))
  653. return -EINVAL;
  654. snprintf(filename, sizeof(filename), "%s/%s",
  655. ar->hw.fw.dir, ar->hw.fw.fw);
  656. ret = ath6kl_get_fw(ar, filename, &ar->fw, &ar->fw_len);
  657. if (ret) {
  658. ath6kl_err("Failed to get firmware file %s: %d\n",
  659. filename, ret);
  660. return ret;
  661. }
  662. return 0;
  663. }
  664. static int ath6kl_fetch_patch_file(struct ath6kl *ar)
  665. {
  666. char filename[100];
  667. int ret;
  668. if (ar->fw_patch != NULL)
  669. return 0;
  670. if (ar->hw.fw.patch == NULL)
  671. return 0;
  672. snprintf(filename, sizeof(filename), "%s/%s",
  673. ar->hw.fw.dir, ar->hw.fw.patch);
  674. ret = ath6kl_get_fw(ar, filename, &ar->fw_patch,
  675. &ar->fw_patch_len);
  676. if (ret) {
  677. ath6kl_err("Failed to get patch file %s: %d\n",
  678. filename, ret);
  679. return ret;
  680. }
  681. return 0;
  682. }
  683. static int ath6kl_fetch_testscript_file(struct ath6kl *ar)
  684. {
  685. char filename[100];
  686. int ret;
  687. if (ar->testmode != 2)
  688. return 0;
  689. if (ar->fw_testscript != NULL)
  690. return 0;
  691. if (ar->hw.fw.testscript == NULL)
  692. return 0;
  693. snprintf(filename, sizeof(filename), "%s/%s",
  694. ar->hw.fw.dir, ar->hw.fw.testscript);
  695. ret = ath6kl_get_fw(ar, filename, &ar->fw_testscript,
  696. &ar->fw_testscript_len);
  697. if (ret) {
  698. ath6kl_err("Failed to get testscript file %s: %d\n",
  699. filename, ret);
  700. return ret;
  701. }
  702. return 0;
  703. }
  704. static int ath6kl_fetch_fw_api1(struct ath6kl *ar)
  705. {
  706. int ret;
  707. ret = ath6kl_fetch_otp_file(ar);
  708. if (ret)
  709. return ret;
  710. ret = ath6kl_fetch_fw_file(ar);
  711. if (ret)
  712. return ret;
  713. ret = ath6kl_fetch_patch_file(ar);
  714. if (ret)
  715. return ret;
  716. ret = ath6kl_fetch_testscript_file(ar);
  717. if (ret)
  718. return ret;
  719. return 0;
  720. }
  721. static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
  722. {
  723. size_t magic_len, len, ie_len;
  724. const struct firmware *fw;
  725. struct ath6kl_fw_ie *hdr;
  726. char filename[100];
  727. const u8 *data;
  728. int ret, ie_id, i, index, bit;
  729. __le32 *val;
  730. snprintf(filename, sizeof(filename), "%s/%s", ar->hw.fw.dir, name);
  731. ret = request_firmware(&fw, filename, ar->dev);
  732. if (ret)
  733. return ret;
  734. data = fw->data;
  735. len = fw->size;
  736. /* magic also includes the null byte, check that as well */
  737. magic_len = strlen(ATH6KL_FIRMWARE_MAGIC) + 1;
  738. if (len < magic_len) {
  739. ret = -EINVAL;
  740. goto out;
  741. }
  742. if (memcmp(data, ATH6KL_FIRMWARE_MAGIC, magic_len) != 0) {
  743. ret = -EINVAL;
  744. goto out;
  745. }
  746. len -= magic_len;
  747. data += magic_len;
  748. /* loop elements */
  749. while (len > sizeof(struct ath6kl_fw_ie)) {
  750. /* hdr is unaligned! */
  751. hdr = (struct ath6kl_fw_ie *) data;
  752. ie_id = le32_to_cpup(&hdr->id);
  753. ie_len = le32_to_cpup(&hdr->len);
  754. len -= sizeof(*hdr);
  755. data += sizeof(*hdr);
  756. if (len < ie_len) {
  757. ret = -EINVAL;
  758. goto out;
  759. }
  760. switch (ie_id) {
  761. case ATH6KL_FW_IE_OTP_IMAGE:
  762. ath6kl_dbg(ATH6KL_DBG_BOOT, "found otp image ie (%zd B)\n",
  763. ie_len);
  764. ar->fw_otp = kmemdup(data, ie_len, GFP_KERNEL);
  765. if (ar->fw_otp == NULL) {
  766. ret = -ENOMEM;
  767. goto out;
  768. }
  769. ar->fw_otp_len = ie_len;
  770. break;
  771. case ATH6KL_FW_IE_FW_IMAGE:
  772. ath6kl_dbg(ATH6KL_DBG_BOOT, "found fw image ie (%zd B)\n",
  773. ie_len);
  774. /* in testmode we already might have a fw file */
  775. if (ar->fw != NULL)
  776. break;
  777. ar->fw = kmemdup(data, ie_len, GFP_KERNEL);
  778. if (ar->fw == NULL) {
  779. ret = -ENOMEM;
  780. goto out;
  781. }
  782. ar->fw_len = ie_len;
  783. break;
  784. case ATH6KL_FW_IE_PATCH_IMAGE:
  785. ath6kl_dbg(ATH6KL_DBG_BOOT, "found patch image ie (%zd B)\n",
  786. ie_len);
  787. ar->fw_patch = kmemdup(data, ie_len, GFP_KERNEL);
  788. if (ar->fw_patch == NULL) {
  789. ret = -ENOMEM;
  790. goto out;
  791. }
  792. ar->fw_patch_len = ie_len;
  793. break;
  794. case ATH6KL_FW_IE_RESERVED_RAM_SIZE:
  795. val = (__le32 *) data;
  796. ar->hw.reserved_ram_size = le32_to_cpup(val);
  797. ath6kl_dbg(ATH6KL_DBG_BOOT,
  798. "found reserved ram size ie 0x%d\n",
  799. ar->hw.reserved_ram_size);
  800. break;
  801. case ATH6KL_FW_IE_CAPABILITIES:
  802. if (ie_len < DIV_ROUND_UP(ATH6KL_FW_CAPABILITY_MAX, 8))
  803. break;
  804. ath6kl_dbg(ATH6KL_DBG_BOOT,
  805. "found firmware capabilities ie (%zd B)\n",
  806. ie_len);
  807. for (i = 0; i < ATH6KL_FW_CAPABILITY_MAX; i++) {
  808. index = i / 8;
  809. bit = i % 8;
  810. if (data[index] & (1 << bit))
  811. __set_bit(i, ar->fw_capabilities);
  812. }
  813. ath6kl_dbg_dump(ATH6KL_DBG_BOOT, "capabilities", "",
  814. ar->fw_capabilities,
  815. sizeof(ar->fw_capabilities));
  816. break;
  817. case ATH6KL_FW_IE_PATCH_ADDR:
  818. if (ie_len != sizeof(*val))
  819. break;
  820. val = (__le32 *) data;
  821. ar->hw.dataset_patch_addr = le32_to_cpup(val);
  822. ath6kl_dbg(ATH6KL_DBG_BOOT,
  823. "found patch address ie 0x%x\n",
  824. ar->hw.dataset_patch_addr);
  825. break;
  826. case ATH6KL_FW_IE_BOARD_ADDR:
  827. if (ie_len != sizeof(*val))
  828. break;
  829. val = (__le32 *) data;
  830. ar->hw.board_addr = le32_to_cpup(val);
  831. ath6kl_dbg(ATH6KL_DBG_BOOT,
  832. "found board address ie 0x%x\n",
  833. ar->hw.board_addr);
  834. break;
  835. case ATH6KL_FW_IE_VIF_MAX:
  836. if (ie_len != sizeof(*val))
  837. break;
  838. val = (__le32 *) data;
  839. ar->vif_max = min_t(unsigned int, le32_to_cpup(val),
  840. ATH6KL_VIF_MAX);
  841. if (ar->vif_max > 1 && !ar->p2p)
  842. ar->max_norm_iface = 2;
  843. ath6kl_dbg(ATH6KL_DBG_BOOT,
  844. "found vif max ie %d\n", ar->vif_max);
  845. break;
  846. default:
  847. ath6kl_dbg(ATH6KL_DBG_BOOT, "Unknown fw ie: %u\n",
  848. le32_to_cpup(&hdr->id));
  849. break;
  850. }
  851. len -= ie_len;
  852. data += ie_len;
  853. };
  854. ret = 0;
  855. out:
  856. release_firmware(fw);
  857. return ret;
  858. }
  859. int ath6kl_init_fetch_firmwares(struct ath6kl *ar)
  860. {
  861. int ret;
  862. ret = ath6kl_fetch_board_file(ar);
  863. if (ret)
  864. return ret;
  865. ret = ath6kl_fetch_testmode_file(ar);
  866. if (ret)
  867. return ret;
  868. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API3_FILE);
  869. if (ret == 0) {
  870. ar->fw_api = 3;
  871. goto out;
  872. }
  873. ret = ath6kl_fetch_fw_apin(ar, ATH6KL_FW_API2_FILE);
  874. if (ret == 0) {
  875. ar->fw_api = 2;
  876. goto out;
  877. }
  878. ret = ath6kl_fetch_fw_api1(ar);
  879. if (ret)
  880. return ret;
  881. ar->fw_api = 1;
  882. out:
  883. ath6kl_dbg(ATH6KL_DBG_BOOT, "using fw api %d\n", ar->fw_api);
  884. return 0;
  885. }
  886. static int ath6kl_upload_board_file(struct ath6kl *ar)
  887. {
  888. u32 board_address, board_ext_address, param;
  889. u32 board_data_size, board_ext_data_size;
  890. int ret;
  891. if (WARN_ON(ar->fw_board == NULL))
  892. return -ENOENT;
  893. /*
  894. * Determine where in Target RAM to write Board Data.
  895. * For AR6004, host determine Target RAM address for
  896. * writing board data.
  897. */
  898. if (ar->hw.board_addr != 0) {
  899. board_address = ar->hw.board_addr;
  900. ath6kl_bmi_write(ar,
  901. ath6kl_get_hi_item_addr(ar,
  902. HI_ITEM(hi_board_data)),
  903. (u8 *) &board_address, 4);
  904. } else {
  905. ath6kl_bmi_read(ar,
  906. ath6kl_get_hi_item_addr(ar,
  907. HI_ITEM(hi_board_data)),
  908. (u8 *) &board_address, 4);
  909. }
  910. /* determine where in target ram to write extended board data */
  911. ath6kl_bmi_read(ar,
  912. ath6kl_get_hi_item_addr(ar,
  913. HI_ITEM(hi_board_ext_data)),
  914. (u8 *) &board_ext_address, 4);
  915. if (ar->target_type == TARGET_TYPE_AR6003 &&
  916. board_ext_address == 0) {
  917. ath6kl_err("Failed to get board file target address.\n");
  918. return -EINVAL;
  919. }
  920. switch (ar->target_type) {
  921. case TARGET_TYPE_AR6003:
  922. board_data_size = AR6003_BOARD_DATA_SZ;
  923. board_ext_data_size = AR6003_BOARD_EXT_DATA_SZ;
  924. break;
  925. case TARGET_TYPE_AR6004:
  926. board_data_size = AR6004_BOARD_DATA_SZ;
  927. board_ext_data_size = AR6004_BOARD_EXT_DATA_SZ;
  928. break;
  929. default:
  930. WARN_ON(1);
  931. return -EINVAL;
  932. break;
  933. }
  934. if (board_ext_address &&
  935. ar->fw_board_len == (board_data_size + board_ext_data_size)) {
  936. /* write extended board data */
  937. ath6kl_dbg(ATH6KL_DBG_BOOT,
  938. "writing extended board data to 0x%x (%d B)\n",
  939. board_ext_address, board_ext_data_size);
  940. ret = ath6kl_bmi_write(ar, board_ext_address,
  941. ar->fw_board + board_data_size,
  942. board_ext_data_size);
  943. if (ret) {
  944. ath6kl_err("Failed to write extended board data: %d\n",
  945. ret);
  946. return ret;
  947. }
  948. /* record that extended board data is initialized */
  949. param = (board_ext_data_size << 16) | 1;
  950. ath6kl_bmi_write(ar,
  951. ath6kl_get_hi_item_addr(ar,
  952. HI_ITEM(hi_board_ext_data_config)),
  953. (unsigned char *) &param, 4);
  954. }
  955. if (ar->fw_board_len < board_data_size) {
  956. ath6kl_err("Too small board file: %zu\n", ar->fw_board_len);
  957. ret = -EINVAL;
  958. return ret;
  959. }
  960. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing board file to 0x%x (%d B)\n",
  961. board_address, board_data_size);
  962. ret = ath6kl_bmi_write(ar, board_address, ar->fw_board,
  963. board_data_size);
  964. if (ret) {
  965. ath6kl_err("Board file bmi write failed: %d\n", ret);
  966. return ret;
  967. }
  968. /* record the fact that Board Data IS initialized */
  969. param = 1;
  970. ath6kl_bmi_write(ar,
  971. ath6kl_get_hi_item_addr(ar,
  972. HI_ITEM(hi_board_data_initialized)),
  973. (u8 *)&param, 4);
  974. return ret;
  975. }
  976. static int ath6kl_upload_otp(struct ath6kl *ar)
  977. {
  978. u32 address, param;
  979. bool from_hw = false;
  980. int ret;
  981. if (ar->fw_otp == NULL)
  982. return 0;
  983. address = ar->hw.app_load_addr;
  984. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing otp to 0x%x (%zd B)\n", address,
  985. ar->fw_otp_len);
  986. ret = ath6kl_bmi_fast_download(ar, address, ar->fw_otp,
  987. ar->fw_otp_len);
  988. if (ret) {
  989. ath6kl_err("Failed to upload OTP file: %d\n", ret);
  990. return ret;
  991. }
  992. /* read firmware start address */
  993. ret = ath6kl_bmi_read(ar,
  994. ath6kl_get_hi_item_addr(ar,
  995. HI_ITEM(hi_app_start)),
  996. (u8 *) &address, sizeof(address));
  997. if (ret) {
  998. ath6kl_err("Failed to read hi_app_start: %d\n", ret);
  999. return ret;
  1000. }
  1001. if (ar->hw.app_start_override_addr == 0) {
  1002. ar->hw.app_start_override_addr = address;
  1003. from_hw = true;
  1004. }
  1005. ath6kl_dbg(ATH6KL_DBG_BOOT, "app_start_override_addr%s 0x%x\n",
  1006. from_hw ? " (from hw)" : "",
  1007. ar->hw.app_start_override_addr);
  1008. /* execute the OTP code */
  1009. ath6kl_dbg(ATH6KL_DBG_BOOT, "executing OTP at 0x%x\n",
  1010. ar->hw.app_start_override_addr);
  1011. param = 0;
  1012. ath6kl_bmi_execute(ar, ar->hw.app_start_override_addr, &param);
  1013. return ret;
  1014. }
  1015. static int ath6kl_upload_firmware(struct ath6kl *ar)
  1016. {
  1017. u32 address;
  1018. int ret;
  1019. if (WARN_ON(ar->fw == NULL))
  1020. return 0;
  1021. address = ar->hw.app_load_addr;
  1022. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing firmware to 0x%x (%zd B)\n",
  1023. address, ar->fw_len);
  1024. ret = ath6kl_bmi_fast_download(ar, address, ar->fw, ar->fw_len);
  1025. if (ret) {
  1026. ath6kl_err("Failed to write firmware: %d\n", ret);
  1027. return ret;
  1028. }
  1029. /*
  1030. * Set starting address for firmware
  1031. * Don't need to setup app_start override addr on AR6004
  1032. */
  1033. if (ar->target_type != TARGET_TYPE_AR6004) {
  1034. address = ar->hw.app_start_override_addr;
  1035. ath6kl_bmi_set_app_start(ar, address);
  1036. }
  1037. return ret;
  1038. }
  1039. static int ath6kl_upload_patch(struct ath6kl *ar)
  1040. {
  1041. u32 address, param;
  1042. int ret;
  1043. if (ar->fw_patch == NULL)
  1044. return 0;
  1045. address = ar->hw.dataset_patch_addr;
  1046. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing patch to 0x%x (%zd B)\n",
  1047. address, ar->fw_patch_len);
  1048. ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len);
  1049. if (ret) {
  1050. ath6kl_err("Failed to write patch file: %d\n", ret);
  1051. return ret;
  1052. }
  1053. param = address;
  1054. ath6kl_bmi_write(ar,
  1055. ath6kl_get_hi_item_addr(ar,
  1056. HI_ITEM(hi_dset_list_head)),
  1057. (unsigned char *) &param, 4);
  1058. return 0;
  1059. }
  1060. static int ath6kl_upload_testscript(struct ath6kl *ar)
  1061. {
  1062. u32 address, param;
  1063. int ret;
  1064. if (ar->testmode != 2)
  1065. return 0;
  1066. if (ar->fw_testscript == NULL)
  1067. return 0;
  1068. address = ar->hw.testscript_addr;
  1069. ath6kl_dbg(ATH6KL_DBG_BOOT, "writing testscript to 0x%x (%zd B)\n",
  1070. address, ar->fw_testscript_len);
  1071. ret = ath6kl_bmi_write(ar, address, ar->fw_testscript,
  1072. ar->fw_testscript_len);
  1073. if (ret) {
  1074. ath6kl_err("Failed to write testscript file: %d\n", ret);
  1075. return ret;
  1076. }
  1077. param = address;
  1078. ath6kl_bmi_write(ar,
  1079. ath6kl_get_hi_item_addr(ar,
  1080. HI_ITEM(hi_ota_testscript)),
  1081. (unsigned char *) &param, 4);
  1082. param = 4096;
  1083. ath6kl_bmi_write(ar,
  1084. ath6kl_get_hi_item_addr(ar,
  1085. HI_ITEM(hi_end_ram_reserve_sz)),
  1086. (unsigned char *) &param, 4);
  1087. param = 1;
  1088. ath6kl_bmi_write(ar,
  1089. ath6kl_get_hi_item_addr(ar,
  1090. HI_ITEM(hi_test_apps_related)),
  1091. (unsigned char *) &param, 4);
  1092. return 0;
  1093. }
  1094. static int ath6kl_init_upload(struct ath6kl *ar)
  1095. {
  1096. u32 param, options, sleep, address;
  1097. int status = 0;
  1098. if (ar->target_type != TARGET_TYPE_AR6003 &&
  1099. ar->target_type != TARGET_TYPE_AR6004)
  1100. return -EINVAL;
  1101. /* temporarily disable system sleep */
  1102. address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
  1103. status = ath6kl_bmi_reg_read(ar, address, &param);
  1104. if (status)
  1105. return status;
  1106. options = param;
  1107. param |= ATH6KL_OPTION_SLEEP_DISABLE;
  1108. status = ath6kl_bmi_reg_write(ar, address, param);
  1109. if (status)
  1110. return status;
  1111. address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
  1112. status = ath6kl_bmi_reg_read(ar, address, &param);
  1113. if (status)
  1114. return status;
  1115. sleep = param;
  1116. param |= SM(SYSTEM_SLEEP_DISABLE, 1);
  1117. status = ath6kl_bmi_reg_write(ar, address, param);
  1118. if (status)
  1119. return status;
  1120. ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n",
  1121. options, sleep);
  1122. /* program analog PLL register */
  1123. /* no need to control 40/44MHz clock on AR6004 */
  1124. if (ar->target_type != TARGET_TYPE_AR6004) {
  1125. status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER,
  1126. 0xF9104001);
  1127. if (status)
  1128. return status;
  1129. /* Run at 80/88MHz by default */
  1130. param = SM(CPU_CLOCK_STANDARD, 1);
  1131. address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS;
  1132. status = ath6kl_bmi_reg_write(ar, address, param);
  1133. if (status)
  1134. return status;
  1135. }
  1136. param = 0;
  1137. address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS;
  1138. param = SM(LPO_CAL_ENABLE, 1);
  1139. status = ath6kl_bmi_reg_write(ar, address, param);
  1140. if (status)
  1141. return status;
  1142. /* WAR to avoid SDIO CRC err */
  1143. if (ar->version.target_ver == AR6003_HW_2_0_VERSION) {
  1144. ath6kl_err("temporary war to avoid sdio crc error\n");
  1145. param = 0x20;
  1146. address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
  1147. status = ath6kl_bmi_reg_write(ar, address, param);
  1148. if (status)
  1149. return status;
  1150. address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS;
  1151. status = ath6kl_bmi_reg_write(ar, address, param);
  1152. if (status)
  1153. return status;
  1154. address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS;
  1155. status = ath6kl_bmi_reg_write(ar, address, param);
  1156. if (status)
  1157. return status;
  1158. address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS;
  1159. status = ath6kl_bmi_reg_write(ar, address, param);
  1160. if (status)
  1161. return status;
  1162. }
  1163. /* write EEPROM data to Target RAM */
  1164. status = ath6kl_upload_board_file(ar);
  1165. if (status)
  1166. return status;
  1167. /* transfer One time Programmable data */
  1168. status = ath6kl_upload_otp(ar);
  1169. if (status)
  1170. return status;
  1171. /* Download Target firmware */
  1172. status = ath6kl_upload_firmware(ar);
  1173. if (status)
  1174. return status;
  1175. status = ath6kl_upload_patch(ar);
  1176. if (status)
  1177. return status;
  1178. /* Download the test script */
  1179. status = ath6kl_upload_testscript(ar);
  1180. if (status)
  1181. return status;
  1182. /* Restore system sleep */
  1183. address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
  1184. status = ath6kl_bmi_reg_write(ar, address, sleep);
  1185. if (status)
  1186. return status;
  1187. address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
  1188. param = options | 0x20;
  1189. status = ath6kl_bmi_reg_write(ar, address, param);
  1190. if (status)
  1191. return status;
  1192. return status;
  1193. }
  1194. int ath6kl_init_hw_params(struct ath6kl *ar)
  1195. {
  1196. const struct ath6kl_hw *uninitialized_var(hw);
  1197. int i;
  1198. for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
  1199. hw = &hw_list[i];
  1200. if (hw->id == ar->version.target_ver)
  1201. break;
  1202. }
  1203. if (i == ARRAY_SIZE(hw_list)) {
  1204. ath6kl_err("Unsupported hardware version: 0x%x\n",
  1205. ar->version.target_ver);
  1206. return -EINVAL;
  1207. }
  1208. ar->hw = *hw;
  1209. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1210. "target_ver 0x%x target_type 0x%x dataset_patch 0x%x app_load_addr 0x%x\n",
  1211. ar->version.target_ver, ar->target_type,
  1212. ar->hw.dataset_patch_addr, ar->hw.app_load_addr);
  1213. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1214. "app_start_override_addr 0x%x board_ext_data_addr 0x%x reserved_ram_size 0x%x",
  1215. ar->hw.app_start_override_addr, ar->hw.board_ext_data_addr,
  1216. ar->hw.reserved_ram_size);
  1217. ath6kl_dbg(ATH6KL_DBG_BOOT,
  1218. "refclk_hz %d uarttx_pin %d",
  1219. ar->hw.refclk_hz, ar->hw.uarttx_pin);
  1220. return 0;
  1221. }
  1222. static const char *ath6kl_init_get_hif_name(enum ath6kl_hif_type type)
  1223. {
  1224. switch (type) {
  1225. case ATH6KL_HIF_TYPE_SDIO:
  1226. return "sdio";
  1227. case ATH6KL_HIF_TYPE_USB:
  1228. return "usb";
  1229. }
  1230. return NULL;
  1231. }
  1232. int ath6kl_init_hw_start(struct ath6kl *ar)
  1233. {
  1234. long timeleft;
  1235. int ret, i;
  1236. ath6kl_dbg(ATH6KL_DBG_BOOT, "hw start\n");
  1237. ret = ath6kl_hif_power_on(ar);
  1238. if (ret)
  1239. return ret;
  1240. ret = ath6kl_configure_target(ar);
  1241. if (ret)
  1242. goto err_power_off;
  1243. ret = ath6kl_init_upload(ar);
  1244. if (ret)
  1245. goto err_power_off;
  1246. /* Do we need to finish the BMI phase */
  1247. /* FIXME: return error from ath6kl_bmi_done() */
  1248. if (ath6kl_bmi_done(ar)) {
  1249. ret = -EIO;
  1250. goto err_power_off;
  1251. }
  1252. /*
  1253. * The reason we have to wait for the target here is that the
  1254. * driver layer has to init BMI in order to set the host block
  1255. * size.
  1256. */
  1257. if (ath6kl_htc_wait_target(ar->htc_target)) {
  1258. ret = -EIO;
  1259. goto err_power_off;
  1260. }
  1261. if (ath6kl_init_service_ep(ar)) {
  1262. ret = -EIO;
  1263. goto err_cleanup_scatter;
  1264. }
  1265. /* setup credit distribution */
  1266. ath6kl_credit_setup(ar->htc_target, &ar->credit_state_info);
  1267. /* start HTC */
  1268. ret = ath6kl_htc_start(ar->htc_target);
  1269. if (ret) {
  1270. /* FIXME: call this */
  1271. ath6kl_cookie_cleanup(ar);
  1272. goto err_cleanup_scatter;
  1273. }
  1274. /* Wait for Wmi event to be ready */
  1275. timeleft = wait_event_interruptible_timeout(ar->event_wq,
  1276. test_bit(WMI_READY,
  1277. &ar->flag),
  1278. WMI_TIMEOUT);
  1279. ath6kl_dbg(ATH6KL_DBG_BOOT, "firmware booted\n");
  1280. if (test_and_clear_bit(FIRST_BOOT, &ar->flag)) {
  1281. ath6kl_info("%s %s fw %s api %d%s\n",
  1282. ar->hw.name,
  1283. ath6kl_init_get_hif_name(ar->hif_type),
  1284. ar->wiphy->fw_version,
  1285. ar->fw_api,
  1286. test_bit(TESTMODE, &ar->flag) ? " testmode" : "");
  1287. }
  1288. if (ar->version.abi_ver != ATH6KL_ABI_VERSION) {
  1289. ath6kl_err("abi version mismatch: host(0x%x), target(0x%x)\n",
  1290. ATH6KL_ABI_VERSION, ar->version.abi_ver);
  1291. ret = -EIO;
  1292. goto err_htc_stop;
  1293. }
  1294. if (!timeleft || signal_pending(current)) {
  1295. ath6kl_err("wmi is not ready or wait was interrupted\n");
  1296. ret = -EIO;
  1297. goto err_htc_stop;
  1298. }
  1299. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: wmi is ready\n", __func__);
  1300. /* communicate the wmi protocol verision to the target */
  1301. /* FIXME: return error */
  1302. if ((ath6kl_set_host_app_area(ar)) != 0)
  1303. ath6kl_err("unable to set the host app area\n");
  1304. for (i = 0; i < ar->vif_max; i++) {
  1305. ret = ath6kl_target_config_wlan_params(ar, i);
  1306. if (ret)
  1307. goto err_htc_stop;
  1308. }
  1309. ar->state = ATH6KL_STATE_ON;
  1310. return 0;
  1311. err_htc_stop:
  1312. ath6kl_htc_stop(ar->htc_target);
  1313. err_cleanup_scatter:
  1314. ath6kl_hif_cleanup_scatter(ar);
  1315. err_power_off:
  1316. ath6kl_hif_power_off(ar);
  1317. return ret;
  1318. }
  1319. int ath6kl_init_hw_stop(struct ath6kl *ar)
  1320. {
  1321. int ret;
  1322. ath6kl_dbg(ATH6KL_DBG_BOOT, "hw stop\n");
  1323. ath6kl_htc_stop(ar->htc_target);
  1324. ath6kl_hif_stop(ar);
  1325. ath6kl_bmi_reset(ar);
  1326. ret = ath6kl_hif_power_off(ar);
  1327. if (ret)
  1328. ath6kl_warn("failed to power off hif: %d\n", ret);
  1329. ar->state = ATH6KL_STATE_OFF;
  1330. return 0;
  1331. }
  1332. /* FIXME: move this to cfg80211.c and rename to ath6kl_cfg80211_vif_stop() */
  1333. void ath6kl_cleanup_vif(struct ath6kl_vif *vif, bool wmi_ready)
  1334. {
  1335. static u8 bcast_mac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
  1336. bool discon_issued;
  1337. netif_stop_queue(vif->ndev);
  1338. clear_bit(WLAN_ENABLED, &vif->flags);
  1339. if (wmi_ready) {
  1340. discon_issued = test_bit(CONNECTED, &vif->flags) ||
  1341. test_bit(CONNECT_PEND, &vif->flags);
  1342. ath6kl_disconnect(vif);
  1343. del_timer(&vif->disconnect_timer);
  1344. if (discon_issued)
  1345. ath6kl_disconnect_event(vif, DISCONNECT_CMD,
  1346. (vif->nw_type & AP_NETWORK) ?
  1347. bcast_mac : vif->bssid,
  1348. 0, NULL, 0);
  1349. }
  1350. if (vif->scan_req) {
  1351. cfg80211_scan_done(vif->scan_req, true);
  1352. vif->scan_req = NULL;
  1353. }
  1354. }
  1355. void ath6kl_stop_txrx(struct ath6kl *ar)
  1356. {
  1357. struct ath6kl_vif *vif, *tmp_vif;
  1358. int i;
  1359. set_bit(DESTROY_IN_PROGRESS, &ar->flag);
  1360. if (down_interruptible(&ar->sem)) {
  1361. ath6kl_err("down_interruptible failed\n");
  1362. return;
  1363. }
  1364. for (i = 0; i < AP_MAX_NUM_STA; i++)
  1365. aggr_reset_state(ar->sta_list[i].aggr_conn);
  1366. spin_lock_bh(&ar->list_lock);
  1367. list_for_each_entry_safe(vif, tmp_vif, &ar->vif_list, list) {
  1368. list_del(&vif->list);
  1369. spin_unlock_bh(&ar->list_lock);
  1370. ath6kl_cleanup_vif(vif, test_bit(WMI_READY, &ar->flag));
  1371. rtnl_lock();
  1372. ath6kl_cfg80211_vif_cleanup(vif);
  1373. rtnl_unlock();
  1374. spin_lock_bh(&ar->list_lock);
  1375. }
  1376. spin_unlock_bh(&ar->list_lock);
  1377. clear_bit(WMI_READY, &ar->flag);
  1378. /*
  1379. * After wmi_shudown all WMI events will be dropped. We
  1380. * need to cleanup the buffers allocated in AP mode and
  1381. * give disconnect notification to stack, which usually
  1382. * happens in the disconnect_event. Simulate the disconnect
  1383. * event by calling the function directly. Sometimes
  1384. * disconnect_event will be received when the debug logs
  1385. * are collected.
  1386. */
  1387. ath6kl_wmi_shutdown(ar->wmi);
  1388. clear_bit(WMI_ENABLED, &ar->flag);
  1389. if (ar->htc_target) {
  1390. ath6kl_dbg(ATH6KL_DBG_TRC, "%s: shut down htc\n", __func__);
  1391. ath6kl_htc_stop(ar->htc_target);
  1392. }
  1393. /*
  1394. * Try to reset the device if we can. The driver may have been
  1395. * configure NOT to reset the target during a debug session.
  1396. */
  1397. ath6kl_dbg(ATH6KL_DBG_TRC,
  1398. "attempting to reset target on instance destroy\n");
  1399. ath6kl_reset_device(ar, ar->target_type, true, true);
  1400. clear_bit(WLAN_ENABLED, &ar->flag);
  1401. }
  1402. EXPORT_SYMBOL(ath6kl_stop_txrx);