resource_tracker.c 67 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069
  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/mlx4/cmd.h>
  42. #include <linux/mlx4/qp.h>
  43. #include "mlx4.h"
  44. #include "fw.h"
  45. #define MLX4_MAC_VALID (1ull << 63)
  46. #define MLX4_MAC_MASK 0x7fffffffffffffffULL
  47. #define ETH_ALEN 6
  48. struct mac_res {
  49. struct list_head list;
  50. u64 mac;
  51. u8 port;
  52. };
  53. struct res_common {
  54. struct list_head list;
  55. u32 res_id;
  56. int owner;
  57. int state;
  58. int from_state;
  59. int to_state;
  60. int removing;
  61. };
  62. enum {
  63. RES_ANY_BUSY = 1
  64. };
  65. struct res_gid {
  66. struct list_head list;
  67. u8 gid[16];
  68. enum mlx4_protocol prot;
  69. };
  70. enum res_qp_states {
  71. RES_QP_BUSY = RES_ANY_BUSY,
  72. /* QP number was allocated */
  73. RES_QP_RESERVED,
  74. /* ICM memory for QP context was mapped */
  75. RES_QP_MAPPED,
  76. /* QP is in hw ownership */
  77. RES_QP_HW
  78. };
  79. static inline const char *qp_states_str(enum res_qp_states state)
  80. {
  81. switch (state) {
  82. case RES_QP_BUSY: return "RES_QP_BUSY";
  83. case RES_QP_RESERVED: return "RES_QP_RESERVED";
  84. case RES_QP_MAPPED: return "RES_QP_MAPPED";
  85. case RES_QP_HW: return "RES_QP_HW";
  86. default: return "Unknown";
  87. }
  88. }
  89. struct res_qp {
  90. struct res_common com;
  91. struct res_mtt *mtt;
  92. struct res_cq *rcq;
  93. struct res_cq *scq;
  94. struct res_srq *srq;
  95. struct list_head mcg_list;
  96. spinlock_t mcg_spl;
  97. int local_qpn;
  98. };
  99. enum res_mtt_states {
  100. RES_MTT_BUSY = RES_ANY_BUSY,
  101. RES_MTT_ALLOCATED,
  102. };
  103. static inline const char *mtt_states_str(enum res_mtt_states state)
  104. {
  105. switch (state) {
  106. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  107. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  108. default: return "Unknown";
  109. }
  110. }
  111. struct res_mtt {
  112. struct res_common com;
  113. int order;
  114. atomic_t ref_count;
  115. };
  116. enum res_mpt_states {
  117. RES_MPT_BUSY = RES_ANY_BUSY,
  118. RES_MPT_RESERVED,
  119. RES_MPT_MAPPED,
  120. RES_MPT_HW,
  121. };
  122. struct res_mpt {
  123. struct res_common com;
  124. struct res_mtt *mtt;
  125. int key;
  126. };
  127. enum res_eq_states {
  128. RES_EQ_BUSY = RES_ANY_BUSY,
  129. RES_EQ_RESERVED,
  130. RES_EQ_HW,
  131. };
  132. struct res_eq {
  133. struct res_common com;
  134. struct res_mtt *mtt;
  135. };
  136. enum res_cq_states {
  137. RES_CQ_BUSY = RES_ANY_BUSY,
  138. RES_CQ_ALLOCATED,
  139. RES_CQ_HW,
  140. };
  141. struct res_cq {
  142. struct res_common com;
  143. struct res_mtt *mtt;
  144. atomic_t ref_count;
  145. };
  146. enum res_srq_states {
  147. RES_SRQ_BUSY = RES_ANY_BUSY,
  148. RES_SRQ_ALLOCATED,
  149. RES_SRQ_HW,
  150. };
  151. static inline const char *srq_states_str(enum res_srq_states state)
  152. {
  153. switch (state) {
  154. case RES_SRQ_BUSY: return "RES_SRQ_BUSY";
  155. case RES_SRQ_ALLOCATED: return "RES_SRQ_ALLOCATED";
  156. case RES_SRQ_HW: return "RES_SRQ_HW";
  157. default: return "Unknown";
  158. }
  159. }
  160. struct res_srq {
  161. struct res_common com;
  162. struct res_mtt *mtt;
  163. struct res_cq *cq;
  164. atomic_t ref_count;
  165. };
  166. enum res_counter_states {
  167. RES_COUNTER_BUSY = RES_ANY_BUSY,
  168. RES_COUNTER_ALLOCATED,
  169. };
  170. static inline const char *counter_states_str(enum res_counter_states state)
  171. {
  172. switch (state) {
  173. case RES_COUNTER_BUSY: return "RES_COUNTER_BUSY";
  174. case RES_COUNTER_ALLOCATED: return "RES_COUNTER_ALLOCATED";
  175. default: return "Unknown";
  176. }
  177. }
  178. struct res_counter {
  179. struct res_common com;
  180. int port;
  181. };
  182. /* For Debug uses */
  183. static const char *ResourceType(enum mlx4_resource rt)
  184. {
  185. switch (rt) {
  186. case RES_QP: return "RES_QP";
  187. case RES_CQ: return "RES_CQ";
  188. case RES_SRQ: return "RES_SRQ";
  189. case RES_MPT: return "RES_MPT";
  190. case RES_MTT: return "RES_MTT";
  191. case RES_MAC: return "RES_MAC";
  192. case RES_EQ: return "RES_EQ";
  193. case RES_COUNTER: return "RES_COUNTER";
  194. default: return "Unknown resource type !!!";
  195. };
  196. }
  197. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  198. {
  199. struct mlx4_priv *priv = mlx4_priv(dev);
  200. int i;
  201. int t;
  202. priv->mfunc.master.res_tracker.slave_list =
  203. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  204. GFP_KERNEL);
  205. if (!priv->mfunc.master.res_tracker.slave_list)
  206. return -ENOMEM;
  207. for (i = 0 ; i < dev->num_slaves; i++) {
  208. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  209. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  210. slave_list[i].res_list[t]);
  211. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  212. }
  213. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  214. dev->num_slaves);
  215. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  216. INIT_RADIX_TREE(&priv->mfunc.master.res_tracker.res_tree[i],
  217. GFP_ATOMIC|__GFP_NOWARN);
  218. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  219. return 0 ;
  220. }
  221. void mlx4_free_resource_tracker(struct mlx4_dev *dev)
  222. {
  223. struct mlx4_priv *priv = mlx4_priv(dev);
  224. int i;
  225. if (priv->mfunc.master.res_tracker.slave_list) {
  226. for (i = 0 ; i < dev->num_slaves; i++)
  227. mlx4_delete_all_resources_for_slave(dev, i);
  228. kfree(priv->mfunc.master.res_tracker.slave_list);
  229. }
  230. }
  231. static void update_ud_gid(struct mlx4_dev *dev,
  232. struct mlx4_qp_context *qp_ctx, u8 slave)
  233. {
  234. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  235. if (MLX4_QP_ST_UD == ts)
  236. qp_ctx->pri_path.mgid_index = 0x80 | slave;
  237. mlx4_dbg(dev, "slave %d, new gid index: 0x%x ",
  238. slave, qp_ctx->pri_path.mgid_index);
  239. }
  240. static int mpt_mask(struct mlx4_dev *dev)
  241. {
  242. return dev->caps.num_mpts - 1;
  243. }
  244. static void *find_res(struct mlx4_dev *dev, int res_id,
  245. enum mlx4_resource type)
  246. {
  247. struct mlx4_priv *priv = mlx4_priv(dev);
  248. return radix_tree_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  249. res_id);
  250. }
  251. static int get_res(struct mlx4_dev *dev, int slave, int res_id,
  252. enum mlx4_resource type,
  253. void *res)
  254. {
  255. struct res_common *r;
  256. int err = 0;
  257. spin_lock_irq(mlx4_tlock(dev));
  258. r = find_res(dev, res_id, type);
  259. if (!r) {
  260. err = -ENONET;
  261. goto exit;
  262. }
  263. if (r->state == RES_ANY_BUSY) {
  264. err = -EBUSY;
  265. goto exit;
  266. }
  267. if (r->owner != slave) {
  268. err = -EPERM;
  269. goto exit;
  270. }
  271. r->from_state = r->state;
  272. r->state = RES_ANY_BUSY;
  273. mlx4_dbg(dev, "res %s id 0x%x to busy\n",
  274. ResourceType(type), r->res_id);
  275. if (res)
  276. *((struct res_common **)res) = r;
  277. exit:
  278. spin_unlock_irq(mlx4_tlock(dev));
  279. return err;
  280. }
  281. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  282. enum mlx4_resource type,
  283. int res_id, int *slave)
  284. {
  285. struct res_common *r;
  286. int err = -ENOENT;
  287. int id = res_id;
  288. if (type == RES_QP)
  289. id &= 0x7fffff;
  290. spin_lock(mlx4_tlock(dev));
  291. r = find_res(dev, id, type);
  292. if (r) {
  293. *slave = r->owner;
  294. err = 0;
  295. }
  296. spin_unlock(mlx4_tlock(dev));
  297. return err;
  298. }
  299. static void put_res(struct mlx4_dev *dev, int slave, int res_id,
  300. enum mlx4_resource type)
  301. {
  302. struct res_common *r;
  303. spin_lock_irq(mlx4_tlock(dev));
  304. r = find_res(dev, res_id, type);
  305. if (r)
  306. r->state = r->from_state;
  307. spin_unlock_irq(mlx4_tlock(dev));
  308. }
  309. static struct res_common *alloc_qp_tr(int id)
  310. {
  311. struct res_qp *ret;
  312. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  313. if (!ret)
  314. return NULL;
  315. ret->com.res_id = id;
  316. ret->com.state = RES_QP_RESERVED;
  317. INIT_LIST_HEAD(&ret->mcg_list);
  318. spin_lock_init(&ret->mcg_spl);
  319. return &ret->com;
  320. }
  321. static struct res_common *alloc_mtt_tr(int id, int order)
  322. {
  323. struct res_mtt *ret;
  324. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  325. if (!ret)
  326. return NULL;
  327. ret->com.res_id = id;
  328. ret->order = order;
  329. ret->com.state = RES_MTT_ALLOCATED;
  330. atomic_set(&ret->ref_count, 0);
  331. return &ret->com;
  332. }
  333. static struct res_common *alloc_mpt_tr(int id, int key)
  334. {
  335. struct res_mpt *ret;
  336. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  337. if (!ret)
  338. return NULL;
  339. ret->com.res_id = id;
  340. ret->com.state = RES_MPT_RESERVED;
  341. ret->key = key;
  342. return &ret->com;
  343. }
  344. static struct res_common *alloc_eq_tr(int id)
  345. {
  346. struct res_eq *ret;
  347. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  348. if (!ret)
  349. return NULL;
  350. ret->com.res_id = id;
  351. ret->com.state = RES_EQ_RESERVED;
  352. return &ret->com;
  353. }
  354. static struct res_common *alloc_cq_tr(int id)
  355. {
  356. struct res_cq *ret;
  357. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  358. if (!ret)
  359. return NULL;
  360. ret->com.res_id = id;
  361. ret->com.state = RES_CQ_ALLOCATED;
  362. atomic_set(&ret->ref_count, 0);
  363. return &ret->com;
  364. }
  365. static struct res_common *alloc_srq_tr(int id)
  366. {
  367. struct res_srq *ret;
  368. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  369. if (!ret)
  370. return NULL;
  371. ret->com.res_id = id;
  372. ret->com.state = RES_SRQ_ALLOCATED;
  373. atomic_set(&ret->ref_count, 0);
  374. return &ret->com;
  375. }
  376. static struct res_common *alloc_counter_tr(int id)
  377. {
  378. struct res_counter *ret;
  379. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  380. if (!ret)
  381. return NULL;
  382. ret->com.res_id = id;
  383. ret->com.state = RES_COUNTER_ALLOCATED;
  384. return &ret->com;
  385. }
  386. static struct res_common *alloc_tr(int id, enum mlx4_resource type, int slave,
  387. int extra)
  388. {
  389. struct res_common *ret;
  390. switch (type) {
  391. case RES_QP:
  392. ret = alloc_qp_tr(id);
  393. break;
  394. case RES_MPT:
  395. ret = alloc_mpt_tr(id, extra);
  396. break;
  397. case RES_MTT:
  398. ret = alloc_mtt_tr(id, extra);
  399. break;
  400. case RES_EQ:
  401. ret = alloc_eq_tr(id);
  402. break;
  403. case RES_CQ:
  404. ret = alloc_cq_tr(id);
  405. break;
  406. case RES_SRQ:
  407. ret = alloc_srq_tr(id);
  408. break;
  409. case RES_MAC:
  410. printk(KERN_ERR "implementation missing\n");
  411. return NULL;
  412. case RES_COUNTER:
  413. ret = alloc_counter_tr(id);
  414. break;
  415. default:
  416. return NULL;
  417. }
  418. if (ret)
  419. ret->owner = slave;
  420. return ret;
  421. }
  422. static int add_res_range(struct mlx4_dev *dev, int slave, int base, int count,
  423. enum mlx4_resource type, int extra)
  424. {
  425. int i;
  426. int err;
  427. struct mlx4_priv *priv = mlx4_priv(dev);
  428. struct res_common **res_arr;
  429. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  430. struct radix_tree_root *root = &tracker->res_tree[type];
  431. res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
  432. if (!res_arr)
  433. return -ENOMEM;
  434. for (i = 0; i < count; ++i) {
  435. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  436. if (!res_arr[i]) {
  437. for (--i; i >= 0; --i)
  438. kfree(res_arr[i]);
  439. kfree(res_arr);
  440. return -ENOMEM;
  441. }
  442. }
  443. spin_lock_irq(mlx4_tlock(dev));
  444. for (i = 0; i < count; ++i) {
  445. if (find_res(dev, base + i, type)) {
  446. err = -EEXIST;
  447. goto undo;
  448. }
  449. err = radix_tree_insert(root, base + i, res_arr[i]);
  450. if (err)
  451. goto undo;
  452. list_add_tail(&res_arr[i]->list,
  453. &tracker->slave_list[slave].res_list[type]);
  454. }
  455. spin_unlock_irq(mlx4_tlock(dev));
  456. kfree(res_arr);
  457. return 0;
  458. undo:
  459. for (--i; i >= base; --i)
  460. radix_tree_delete(&tracker->res_tree[type], i);
  461. spin_unlock_irq(mlx4_tlock(dev));
  462. for (i = 0; i < count; ++i)
  463. kfree(res_arr[i]);
  464. kfree(res_arr);
  465. return err;
  466. }
  467. static int remove_qp_ok(struct res_qp *res)
  468. {
  469. if (res->com.state == RES_QP_BUSY)
  470. return -EBUSY;
  471. else if (res->com.state != RES_QP_RESERVED)
  472. return -EPERM;
  473. return 0;
  474. }
  475. static int remove_mtt_ok(struct res_mtt *res, int order)
  476. {
  477. if (res->com.state == RES_MTT_BUSY ||
  478. atomic_read(&res->ref_count)) {
  479. printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
  480. __func__, __LINE__,
  481. mtt_states_str(res->com.state),
  482. atomic_read(&res->ref_count));
  483. return -EBUSY;
  484. } else if (res->com.state != RES_MTT_ALLOCATED)
  485. return -EPERM;
  486. else if (res->order != order)
  487. return -EINVAL;
  488. return 0;
  489. }
  490. static int remove_mpt_ok(struct res_mpt *res)
  491. {
  492. if (res->com.state == RES_MPT_BUSY)
  493. return -EBUSY;
  494. else if (res->com.state != RES_MPT_RESERVED)
  495. return -EPERM;
  496. return 0;
  497. }
  498. static int remove_eq_ok(struct res_eq *res)
  499. {
  500. if (res->com.state == RES_MPT_BUSY)
  501. return -EBUSY;
  502. else if (res->com.state != RES_MPT_RESERVED)
  503. return -EPERM;
  504. return 0;
  505. }
  506. static int remove_counter_ok(struct res_counter *res)
  507. {
  508. if (res->com.state == RES_COUNTER_BUSY)
  509. return -EBUSY;
  510. else if (res->com.state != RES_COUNTER_ALLOCATED)
  511. return -EPERM;
  512. return 0;
  513. }
  514. static int remove_cq_ok(struct res_cq *res)
  515. {
  516. if (res->com.state == RES_CQ_BUSY)
  517. return -EBUSY;
  518. else if (res->com.state != RES_CQ_ALLOCATED)
  519. return -EPERM;
  520. return 0;
  521. }
  522. static int remove_srq_ok(struct res_srq *res)
  523. {
  524. if (res->com.state == RES_SRQ_BUSY)
  525. return -EBUSY;
  526. else if (res->com.state != RES_SRQ_ALLOCATED)
  527. return -EPERM;
  528. return 0;
  529. }
  530. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  531. {
  532. switch (type) {
  533. case RES_QP:
  534. return remove_qp_ok((struct res_qp *)res);
  535. case RES_CQ:
  536. return remove_cq_ok((struct res_cq *)res);
  537. case RES_SRQ:
  538. return remove_srq_ok((struct res_srq *)res);
  539. case RES_MPT:
  540. return remove_mpt_ok((struct res_mpt *)res);
  541. case RES_MTT:
  542. return remove_mtt_ok((struct res_mtt *)res, extra);
  543. case RES_MAC:
  544. return -ENOSYS;
  545. case RES_EQ:
  546. return remove_eq_ok((struct res_eq *)res);
  547. case RES_COUNTER:
  548. return remove_counter_ok((struct res_counter *)res);
  549. default:
  550. return -EINVAL;
  551. }
  552. }
  553. static int rem_res_range(struct mlx4_dev *dev, int slave, int base, int count,
  554. enum mlx4_resource type, int extra)
  555. {
  556. int i;
  557. int err;
  558. struct mlx4_priv *priv = mlx4_priv(dev);
  559. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  560. struct res_common *r;
  561. spin_lock_irq(mlx4_tlock(dev));
  562. for (i = base; i < base + count; ++i) {
  563. r = radix_tree_lookup(&tracker->res_tree[type], i);
  564. if (!r) {
  565. err = -ENOENT;
  566. goto out;
  567. }
  568. if (r->owner != slave) {
  569. err = -EPERM;
  570. goto out;
  571. }
  572. err = remove_ok(r, type, extra);
  573. if (err)
  574. goto out;
  575. }
  576. for (i = base; i < base + count; ++i) {
  577. r = radix_tree_lookup(&tracker->res_tree[type], i);
  578. radix_tree_delete(&tracker->res_tree[type], i);
  579. list_del(&r->list);
  580. kfree(r);
  581. }
  582. err = 0;
  583. out:
  584. spin_unlock_irq(mlx4_tlock(dev));
  585. return err;
  586. }
  587. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  588. enum res_qp_states state, struct res_qp **qp,
  589. int alloc)
  590. {
  591. struct mlx4_priv *priv = mlx4_priv(dev);
  592. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  593. struct res_qp *r;
  594. int err = 0;
  595. spin_lock_irq(mlx4_tlock(dev));
  596. r = radix_tree_lookup(&tracker->res_tree[RES_QP], qpn);
  597. if (!r)
  598. err = -ENOENT;
  599. else if (r->com.owner != slave)
  600. err = -EPERM;
  601. else {
  602. switch (state) {
  603. case RES_QP_BUSY:
  604. mlx4_dbg(dev, "%s: failed RES_QP, 0x%x\n",
  605. __func__, r->com.res_id);
  606. err = -EBUSY;
  607. break;
  608. case RES_QP_RESERVED:
  609. if (r->com.state == RES_QP_MAPPED && !alloc)
  610. break;
  611. mlx4_dbg(dev, "failed RES_QP, 0x%x\n", r->com.res_id);
  612. err = -EINVAL;
  613. break;
  614. case RES_QP_MAPPED:
  615. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  616. r->com.state == RES_QP_HW)
  617. break;
  618. else {
  619. mlx4_dbg(dev, "failed RES_QP, 0x%x\n",
  620. r->com.res_id);
  621. err = -EINVAL;
  622. }
  623. break;
  624. case RES_QP_HW:
  625. if (r->com.state != RES_QP_MAPPED)
  626. err = -EINVAL;
  627. break;
  628. default:
  629. err = -EINVAL;
  630. }
  631. if (!err) {
  632. r->com.from_state = r->com.state;
  633. r->com.to_state = state;
  634. r->com.state = RES_QP_BUSY;
  635. if (qp)
  636. *qp = (struct res_qp *)r;
  637. }
  638. }
  639. spin_unlock_irq(mlx4_tlock(dev));
  640. return err;
  641. }
  642. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  643. enum res_mpt_states state, struct res_mpt **mpt)
  644. {
  645. struct mlx4_priv *priv = mlx4_priv(dev);
  646. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  647. struct res_mpt *r;
  648. int err = 0;
  649. spin_lock_irq(mlx4_tlock(dev));
  650. r = radix_tree_lookup(&tracker->res_tree[RES_MPT], index);
  651. if (!r)
  652. err = -ENOENT;
  653. else if (r->com.owner != slave)
  654. err = -EPERM;
  655. else {
  656. switch (state) {
  657. case RES_MPT_BUSY:
  658. err = -EINVAL;
  659. break;
  660. case RES_MPT_RESERVED:
  661. if (r->com.state != RES_MPT_MAPPED)
  662. err = -EINVAL;
  663. break;
  664. case RES_MPT_MAPPED:
  665. if (r->com.state != RES_MPT_RESERVED &&
  666. r->com.state != RES_MPT_HW)
  667. err = -EINVAL;
  668. break;
  669. case RES_MPT_HW:
  670. if (r->com.state != RES_MPT_MAPPED)
  671. err = -EINVAL;
  672. break;
  673. default:
  674. err = -EINVAL;
  675. }
  676. if (!err) {
  677. r->com.from_state = r->com.state;
  678. r->com.to_state = state;
  679. r->com.state = RES_MPT_BUSY;
  680. if (mpt)
  681. *mpt = (struct res_mpt *)r;
  682. }
  683. }
  684. spin_unlock_irq(mlx4_tlock(dev));
  685. return err;
  686. }
  687. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  688. enum res_eq_states state, struct res_eq **eq)
  689. {
  690. struct mlx4_priv *priv = mlx4_priv(dev);
  691. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  692. struct res_eq *r;
  693. int err = 0;
  694. spin_lock_irq(mlx4_tlock(dev));
  695. r = radix_tree_lookup(&tracker->res_tree[RES_EQ], index);
  696. if (!r)
  697. err = -ENOENT;
  698. else if (r->com.owner != slave)
  699. err = -EPERM;
  700. else {
  701. switch (state) {
  702. case RES_EQ_BUSY:
  703. err = -EINVAL;
  704. break;
  705. case RES_EQ_RESERVED:
  706. if (r->com.state != RES_EQ_HW)
  707. err = -EINVAL;
  708. break;
  709. case RES_EQ_HW:
  710. if (r->com.state != RES_EQ_RESERVED)
  711. err = -EINVAL;
  712. break;
  713. default:
  714. err = -EINVAL;
  715. }
  716. if (!err) {
  717. r->com.from_state = r->com.state;
  718. r->com.to_state = state;
  719. r->com.state = RES_EQ_BUSY;
  720. if (eq)
  721. *eq = r;
  722. }
  723. }
  724. spin_unlock_irq(mlx4_tlock(dev));
  725. return err;
  726. }
  727. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  728. enum res_cq_states state, struct res_cq **cq)
  729. {
  730. struct mlx4_priv *priv = mlx4_priv(dev);
  731. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  732. struct res_cq *r;
  733. int err;
  734. spin_lock_irq(mlx4_tlock(dev));
  735. r = radix_tree_lookup(&tracker->res_tree[RES_CQ], cqn);
  736. if (!r)
  737. err = -ENOENT;
  738. else if (r->com.owner != slave)
  739. err = -EPERM;
  740. else {
  741. switch (state) {
  742. case RES_CQ_BUSY:
  743. err = -EBUSY;
  744. break;
  745. case RES_CQ_ALLOCATED:
  746. if (r->com.state != RES_CQ_HW)
  747. err = -EINVAL;
  748. else if (atomic_read(&r->ref_count))
  749. err = -EBUSY;
  750. else
  751. err = 0;
  752. break;
  753. case RES_CQ_HW:
  754. if (r->com.state != RES_CQ_ALLOCATED)
  755. err = -EINVAL;
  756. else
  757. err = 0;
  758. break;
  759. default:
  760. err = -EINVAL;
  761. }
  762. if (!err) {
  763. r->com.from_state = r->com.state;
  764. r->com.to_state = state;
  765. r->com.state = RES_CQ_BUSY;
  766. if (cq)
  767. *cq = r;
  768. }
  769. }
  770. spin_unlock_irq(mlx4_tlock(dev));
  771. return err;
  772. }
  773. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  774. enum res_cq_states state, struct res_srq **srq)
  775. {
  776. struct mlx4_priv *priv = mlx4_priv(dev);
  777. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  778. struct res_srq *r;
  779. int err = 0;
  780. spin_lock_irq(mlx4_tlock(dev));
  781. r = radix_tree_lookup(&tracker->res_tree[RES_SRQ], index);
  782. if (!r)
  783. err = -ENOENT;
  784. else if (r->com.owner != slave)
  785. err = -EPERM;
  786. else {
  787. switch (state) {
  788. case RES_SRQ_BUSY:
  789. err = -EINVAL;
  790. break;
  791. case RES_SRQ_ALLOCATED:
  792. if (r->com.state != RES_SRQ_HW)
  793. err = -EINVAL;
  794. else if (atomic_read(&r->ref_count))
  795. err = -EBUSY;
  796. break;
  797. case RES_SRQ_HW:
  798. if (r->com.state != RES_SRQ_ALLOCATED)
  799. err = -EINVAL;
  800. break;
  801. default:
  802. err = -EINVAL;
  803. }
  804. if (!err) {
  805. r->com.from_state = r->com.state;
  806. r->com.to_state = state;
  807. r->com.state = RES_SRQ_BUSY;
  808. if (srq)
  809. *srq = r;
  810. }
  811. }
  812. spin_unlock_irq(mlx4_tlock(dev));
  813. return err;
  814. }
  815. static void res_abort_move(struct mlx4_dev *dev, int slave,
  816. enum mlx4_resource type, int id)
  817. {
  818. struct mlx4_priv *priv = mlx4_priv(dev);
  819. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  820. struct res_common *r;
  821. spin_lock_irq(mlx4_tlock(dev));
  822. r = radix_tree_lookup(&tracker->res_tree[type], id);
  823. if (r && (r->owner == slave))
  824. r->state = r->from_state;
  825. spin_unlock_irq(mlx4_tlock(dev));
  826. }
  827. static void res_end_move(struct mlx4_dev *dev, int slave,
  828. enum mlx4_resource type, int id)
  829. {
  830. struct mlx4_priv *priv = mlx4_priv(dev);
  831. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  832. struct res_common *r;
  833. spin_lock_irq(mlx4_tlock(dev));
  834. r = radix_tree_lookup(&tracker->res_tree[type], id);
  835. if (r && (r->owner == slave))
  836. r->state = r->to_state;
  837. spin_unlock_irq(mlx4_tlock(dev));
  838. }
  839. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  840. {
  841. return mlx4_is_qp_reserved(dev, qpn);
  842. }
  843. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  844. u64 in_param, u64 *out_param)
  845. {
  846. int err;
  847. int count;
  848. int align;
  849. int base;
  850. int qpn;
  851. switch (op) {
  852. case RES_OP_RESERVE:
  853. count = get_param_l(&in_param);
  854. align = get_param_h(&in_param);
  855. err = __mlx4_qp_reserve_range(dev, count, align, &base);
  856. if (err)
  857. return err;
  858. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  859. if (err) {
  860. __mlx4_qp_release_range(dev, base, count);
  861. return err;
  862. }
  863. set_param_l(out_param, base);
  864. break;
  865. case RES_OP_MAP_ICM:
  866. qpn = get_param_l(&in_param) & 0x7fffff;
  867. if (valid_reserved(dev, slave, qpn)) {
  868. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  869. if (err)
  870. return err;
  871. }
  872. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  873. NULL, 1);
  874. if (err)
  875. return err;
  876. if (!valid_reserved(dev, slave, qpn)) {
  877. err = __mlx4_qp_alloc_icm(dev, qpn);
  878. if (err) {
  879. res_abort_move(dev, slave, RES_QP, qpn);
  880. return err;
  881. }
  882. }
  883. res_end_move(dev, slave, RES_QP, qpn);
  884. break;
  885. default:
  886. err = -EINVAL;
  887. break;
  888. }
  889. return err;
  890. }
  891. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  892. u64 in_param, u64 *out_param)
  893. {
  894. int err = -EINVAL;
  895. int base;
  896. int order;
  897. if (op != RES_OP_RESERVE_AND_MAP)
  898. return err;
  899. order = get_param_l(&in_param);
  900. base = __mlx4_alloc_mtt_range(dev, order);
  901. if (base == -1)
  902. return -ENOMEM;
  903. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  904. if (err)
  905. __mlx4_free_mtt_range(dev, base, order);
  906. else
  907. set_param_l(out_param, base);
  908. return err;
  909. }
  910. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  911. u64 in_param, u64 *out_param)
  912. {
  913. int err = -EINVAL;
  914. int index;
  915. int id;
  916. struct res_mpt *mpt;
  917. switch (op) {
  918. case RES_OP_RESERVE:
  919. index = __mlx4_mr_reserve(dev);
  920. if (index == -1)
  921. break;
  922. id = index & mpt_mask(dev);
  923. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  924. if (err) {
  925. __mlx4_mr_release(dev, index);
  926. break;
  927. }
  928. set_param_l(out_param, index);
  929. break;
  930. case RES_OP_MAP_ICM:
  931. index = get_param_l(&in_param);
  932. id = index & mpt_mask(dev);
  933. err = mr_res_start_move_to(dev, slave, id,
  934. RES_MPT_MAPPED, &mpt);
  935. if (err)
  936. return err;
  937. err = __mlx4_mr_alloc_icm(dev, mpt->key);
  938. if (err) {
  939. res_abort_move(dev, slave, RES_MPT, id);
  940. return err;
  941. }
  942. res_end_move(dev, slave, RES_MPT, id);
  943. break;
  944. }
  945. return err;
  946. }
  947. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  948. u64 in_param, u64 *out_param)
  949. {
  950. int cqn;
  951. int err;
  952. switch (op) {
  953. case RES_OP_RESERVE_AND_MAP:
  954. err = __mlx4_cq_alloc_icm(dev, &cqn);
  955. if (err)
  956. break;
  957. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  958. if (err) {
  959. __mlx4_cq_free_icm(dev, cqn);
  960. break;
  961. }
  962. set_param_l(out_param, cqn);
  963. break;
  964. default:
  965. err = -EINVAL;
  966. }
  967. return err;
  968. }
  969. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  970. u64 in_param, u64 *out_param)
  971. {
  972. int srqn;
  973. int err;
  974. switch (op) {
  975. case RES_OP_RESERVE_AND_MAP:
  976. err = __mlx4_srq_alloc_icm(dev, &srqn);
  977. if (err)
  978. break;
  979. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  980. if (err) {
  981. __mlx4_srq_free_icm(dev, srqn);
  982. break;
  983. }
  984. set_param_l(out_param, srqn);
  985. break;
  986. default:
  987. err = -EINVAL;
  988. }
  989. return err;
  990. }
  991. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
  992. {
  993. struct mlx4_priv *priv = mlx4_priv(dev);
  994. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  995. struct mac_res *res;
  996. res = kzalloc(sizeof *res, GFP_KERNEL);
  997. if (!res)
  998. return -ENOMEM;
  999. res->mac = mac;
  1000. res->port = (u8) port;
  1001. list_add_tail(&res->list,
  1002. &tracker->slave_list[slave].res_list[RES_MAC]);
  1003. return 0;
  1004. }
  1005. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1006. int port)
  1007. {
  1008. struct mlx4_priv *priv = mlx4_priv(dev);
  1009. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1010. struct list_head *mac_list =
  1011. &tracker->slave_list[slave].res_list[RES_MAC];
  1012. struct mac_res *res, *tmp;
  1013. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1014. if (res->mac == mac && res->port == (u8) port) {
  1015. list_del(&res->list);
  1016. kfree(res);
  1017. break;
  1018. }
  1019. }
  1020. }
  1021. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1022. {
  1023. struct mlx4_priv *priv = mlx4_priv(dev);
  1024. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1025. struct list_head *mac_list =
  1026. &tracker->slave_list[slave].res_list[RES_MAC];
  1027. struct mac_res *res, *tmp;
  1028. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1029. list_del(&res->list);
  1030. __mlx4_unregister_mac(dev, res->port, res->mac);
  1031. kfree(res);
  1032. }
  1033. }
  1034. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1035. u64 in_param, u64 *out_param)
  1036. {
  1037. int err = -EINVAL;
  1038. int port;
  1039. u64 mac;
  1040. if (op != RES_OP_RESERVE_AND_MAP)
  1041. return err;
  1042. port = get_param_l(out_param);
  1043. mac = in_param;
  1044. err = __mlx4_register_mac(dev, port, mac);
  1045. if (err >= 0) {
  1046. set_param_l(out_param, err);
  1047. err = 0;
  1048. }
  1049. if (!err) {
  1050. err = mac_add_to_slave(dev, slave, mac, port);
  1051. if (err)
  1052. __mlx4_unregister_mac(dev, port, mac);
  1053. }
  1054. return err;
  1055. }
  1056. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1057. u64 in_param, u64 *out_param)
  1058. {
  1059. return 0;
  1060. }
  1061. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1062. struct mlx4_vhcr *vhcr,
  1063. struct mlx4_cmd_mailbox *inbox,
  1064. struct mlx4_cmd_mailbox *outbox,
  1065. struct mlx4_cmd_info *cmd)
  1066. {
  1067. int err;
  1068. int alop = vhcr->op_modifier;
  1069. switch (vhcr->in_modifier) {
  1070. case RES_QP:
  1071. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1072. vhcr->in_param, &vhcr->out_param);
  1073. break;
  1074. case RES_MTT:
  1075. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1076. vhcr->in_param, &vhcr->out_param);
  1077. break;
  1078. case RES_MPT:
  1079. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1080. vhcr->in_param, &vhcr->out_param);
  1081. break;
  1082. case RES_CQ:
  1083. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1084. vhcr->in_param, &vhcr->out_param);
  1085. break;
  1086. case RES_SRQ:
  1087. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1088. vhcr->in_param, &vhcr->out_param);
  1089. break;
  1090. case RES_MAC:
  1091. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1092. vhcr->in_param, &vhcr->out_param);
  1093. break;
  1094. case RES_VLAN:
  1095. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1096. vhcr->in_param, &vhcr->out_param);
  1097. break;
  1098. default:
  1099. err = -EINVAL;
  1100. break;
  1101. }
  1102. return err;
  1103. }
  1104. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1105. u64 in_param)
  1106. {
  1107. int err;
  1108. int count;
  1109. int base;
  1110. int qpn;
  1111. switch (op) {
  1112. case RES_OP_RESERVE:
  1113. base = get_param_l(&in_param) & 0x7fffff;
  1114. count = get_param_h(&in_param);
  1115. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  1116. if (err)
  1117. break;
  1118. __mlx4_qp_release_range(dev, base, count);
  1119. break;
  1120. case RES_OP_MAP_ICM:
  1121. qpn = get_param_l(&in_param) & 0x7fffff;
  1122. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  1123. NULL, 0);
  1124. if (err)
  1125. return err;
  1126. if (!valid_reserved(dev, slave, qpn))
  1127. __mlx4_qp_free_icm(dev, qpn);
  1128. res_end_move(dev, slave, RES_QP, qpn);
  1129. if (valid_reserved(dev, slave, qpn))
  1130. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1131. break;
  1132. default:
  1133. err = -EINVAL;
  1134. break;
  1135. }
  1136. return err;
  1137. }
  1138. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1139. u64 in_param, u64 *out_param)
  1140. {
  1141. int err = -EINVAL;
  1142. int base;
  1143. int order;
  1144. if (op != RES_OP_RESERVE_AND_MAP)
  1145. return err;
  1146. base = get_param_l(&in_param);
  1147. order = get_param_h(&in_param);
  1148. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  1149. if (!err)
  1150. __mlx4_free_mtt_range(dev, base, order);
  1151. return err;
  1152. }
  1153. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1154. u64 in_param)
  1155. {
  1156. int err = -EINVAL;
  1157. int index;
  1158. int id;
  1159. struct res_mpt *mpt;
  1160. switch (op) {
  1161. case RES_OP_RESERVE:
  1162. index = get_param_l(&in_param);
  1163. id = index & mpt_mask(dev);
  1164. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1165. if (err)
  1166. break;
  1167. index = mpt->key;
  1168. put_res(dev, slave, id, RES_MPT);
  1169. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  1170. if (err)
  1171. break;
  1172. __mlx4_mr_release(dev, index);
  1173. break;
  1174. case RES_OP_MAP_ICM:
  1175. index = get_param_l(&in_param);
  1176. id = index & mpt_mask(dev);
  1177. err = mr_res_start_move_to(dev, slave, id,
  1178. RES_MPT_RESERVED, &mpt);
  1179. if (err)
  1180. return err;
  1181. __mlx4_mr_free_icm(dev, mpt->key);
  1182. res_end_move(dev, slave, RES_MPT, id);
  1183. return err;
  1184. break;
  1185. default:
  1186. err = -EINVAL;
  1187. break;
  1188. }
  1189. return err;
  1190. }
  1191. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1192. u64 in_param, u64 *out_param)
  1193. {
  1194. int cqn;
  1195. int err;
  1196. switch (op) {
  1197. case RES_OP_RESERVE_AND_MAP:
  1198. cqn = get_param_l(&in_param);
  1199. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1200. if (err)
  1201. break;
  1202. __mlx4_cq_free_icm(dev, cqn);
  1203. break;
  1204. default:
  1205. err = -EINVAL;
  1206. break;
  1207. }
  1208. return err;
  1209. }
  1210. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1211. u64 in_param, u64 *out_param)
  1212. {
  1213. int srqn;
  1214. int err;
  1215. switch (op) {
  1216. case RES_OP_RESERVE_AND_MAP:
  1217. srqn = get_param_l(&in_param);
  1218. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1219. if (err)
  1220. break;
  1221. __mlx4_srq_free_icm(dev, srqn);
  1222. break;
  1223. default:
  1224. err = -EINVAL;
  1225. break;
  1226. }
  1227. return err;
  1228. }
  1229. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1230. u64 in_param, u64 *out_param)
  1231. {
  1232. int port;
  1233. int err = 0;
  1234. switch (op) {
  1235. case RES_OP_RESERVE_AND_MAP:
  1236. port = get_param_l(out_param);
  1237. mac_del_from_slave(dev, slave, in_param, port);
  1238. __mlx4_unregister_mac(dev, port, in_param);
  1239. break;
  1240. default:
  1241. err = -EINVAL;
  1242. break;
  1243. }
  1244. return err;
  1245. }
  1246. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1247. u64 in_param, u64 *out_param)
  1248. {
  1249. return 0;
  1250. }
  1251. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  1252. struct mlx4_vhcr *vhcr,
  1253. struct mlx4_cmd_mailbox *inbox,
  1254. struct mlx4_cmd_mailbox *outbox,
  1255. struct mlx4_cmd_info *cmd)
  1256. {
  1257. int err = -EINVAL;
  1258. int alop = vhcr->op_modifier;
  1259. switch (vhcr->in_modifier) {
  1260. case RES_QP:
  1261. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  1262. vhcr->in_param);
  1263. break;
  1264. case RES_MTT:
  1265. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  1266. vhcr->in_param, &vhcr->out_param);
  1267. break;
  1268. case RES_MPT:
  1269. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  1270. vhcr->in_param);
  1271. break;
  1272. case RES_CQ:
  1273. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  1274. vhcr->in_param, &vhcr->out_param);
  1275. break;
  1276. case RES_SRQ:
  1277. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  1278. vhcr->in_param, &vhcr->out_param);
  1279. break;
  1280. case RES_MAC:
  1281. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  1282. vhcr->in_param, &vhcr->out_param);
  1283. break;
  1284. case RES_VLAN:
  1285. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  1286. vhcr->in_param, &vhcr->out_param);
  1287. break;
  1288. default:
  1289. break;
  1290. }
  1291. return err;
  1292. }
  1293. /* ugly but other choices are uglier */
  1294. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  1295. {
  1296. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  1297. }
  1298. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  1299. {
  1300. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  1301. }
  1302. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  1303. {
  1304. return be32_to_cpu(mpt->mtt_sz);
  1305. }
  1306. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  1307. {
  1308. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  1309. }
  1310. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  1311. {
  1312. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  1313. }
  1314. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  1315. {
  1316. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  1317. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  1318. int log_sq_sride = qpc->sq_size_stride & 7;
  1319. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  1320. int log_rq_stride = qpc->rq_size_stride & 7;
  1321. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  1322. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  1323. int xrc = (be32_to_cpu(qpc->local_qpn) >> 23) & 1;
  1324. int sq_size;
  1325. int rq_size;
  1326. int total_pages;
  1327. int total_mem;
  1328. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  1329. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  1330. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  1331. total_mem = sq_size + rq_size;
  1332. total_pages =
  1333. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  1334. page_shift);
  1335. return total_pages;
  1336. }
  1337. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  1338. int size, struct res_mtt *mtt)
  1339. {
  1340. int res_start = mtt->com.res_id;
  1341. int res_size = (1 << mtt->order);
  1342. if (start < res_start || start + size > res_start + res_size)
  1343. return -EPERM;
  1344. return 0;
  1345. }
  1346. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1347. struct mlx4_vhcr *vhcr,
  1348. struct mlx4_cmd_mailbox *inbox,
  1349. struct mlx4_cmd_mailbox *outbox,
  1350. struct mlx4_cmd_info *cmd)
  1351. {
  1352. int err;
  1353. int index = vhcr->in_modifier;
  1354. struct res_mtt *mtt;
  1355. struct res_mpt *mpt;
  1356. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  1357. int phys;
  1358. int id;
  1359. id = index & mpt_mask(dev);
  1360. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  1361. if (err)
  1362. return err;
  1363. phys = mr_phys_mpt(inbox->buf);
  1364. if (!phys) {
  1365. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1366. if (err)
  1367. goto ex_abort;
  1368. err = check_mtt_range(dev, slave, mtt_base,
  1369. mr_get_mtt_size(inbox->buf), mtt);
  1370. if (err)
  1371. goto ex_put;
  1372. mpt->mtt = mtt;
  1373. }
  1374. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1375. if (err)
  1376. goto ex_put;
  1377. if (!phys) {
  1378. atomic_inc(&mtt->ref_count);
  1379. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1380. }
  1381. res_end_move(dev, slave, RES_MPT, id);
  1382. return 0;
  1383. ex_put:
  1384. if (!phys)
  1385. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1386. ex_abort:
  1387. res_abort_move(dev, slave, RES_MPT, id);
  1388. return err;
  1389. }
  1390. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1391. struct mlx4_vhcr *vhcr,
  1392. struct mlx4_cmd_mailbox *inbox,
  1393. struct mlx4_cmd_mailbox *outbox,
  1394. struct mlx4_cmd_info *cmd)
  1395. {
  1396. int err;
  1397. int index = vhcr->in_modifier;
  1398. struct res_mpt *mpt;
  1399. int id;
  1400. id = index & mpt_mask(dev);
  1401. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  1402. if (err)
  1403. return err;
  1404. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1405. if (err)
  1406. goto ex_abort;
  1407. if (mpt->mtt)
  1408. atomic_dec(&mpt->mtt->ref_count);
  1409. res_end_move(dev, slave, RES_MPT, id);
  1410. return 0;
  1411. ex_abort:
  1412. res_abort_move(dev, slave, RES_MPT, id);
  1413. return err;
  1414. }
  1415. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1416. struct mlx4_vhcr *vhcr,
  1417. struct mlx4_cmd_mailbox *inbox,
  1418. struct mlx4_cmd_mailbox *outbox,
  1419. struct mlx4_cmd_info *cmd)
  1420. {
  1421. int err;
  1422. int index = vhcr->in_modifier;
  1423. struct res_mpt *mpt;
  1424. int id;
  1425. id = index & mpt_mask(dev);
  1426. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1427. if (err)
  1428. return err;
  1429. if (mpt->com.from_state != RES_MPT_HW) {
  1430. err = -EBUSY;
  1431. goto out;
  1432. }
  1433. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1434. out:
  1435. put_res(dev, slave, id, RES_MPT);
  1436. return err;
  1437. }
  1438. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  1439. {
  1440. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  1441. }
  1442. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  1443. {
  1444. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  1445. }
  1446. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  1447. {
  1448. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  1449. }
  1450. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  1451. struct mlx4_vhcr *vhcr,
  1452. struct mlx4_cmd_mailbox *inbox,
  1453. struct mlx4_cmd_mailbox *outbox,
  1454. struct mlx4_cmd_info *cmd)
  1455. {
  1456. int err;
  1457. int qpn = vhcr->in_modifier & 0x7fffff;
  1458. struct res_mtt *mtt;
  1459. struct res_qp *qp;
  1460. struct mlx4_qp_context *qpc = inbox->buf + 8;
  1461. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  1462. int mtt_size = qp_get_mtt_size(qpc);
  1463. struct res_cq *rcq;
  1464. struct res_cq *scq;
  1465. int rcqn = qp_get_rcqn(qpc);
  1466. int scqn = qp_get_scqn(qpc);
  1467. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  1468. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  1469. struct res_srq *srq;
  1470. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  1471. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  1472. if (err)
  1473. return err;
  1474. qp->local_qpn = local_qpn;
  1475. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1476. if (err)
  1477. goto ex_abort;
  1478. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1479. if (err)
  1480. goto ex_put_mtt;
  1481. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  1482. if (err)
  1483. goto ex_put_mtt;
  1484. if (scqn != rcqn) {
  1485. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  1486. if (err)
  1487. goto ex_put_rcq;
  1488. } else
  1489. scq = rcq;
  1490. if (use_srq) {
  1491. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1492. if (err)
  1493. goto ex_put_scq;
  1494. }
  1495. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1496. if (err)
  1497. goto ex_put_srq;
  1498. atomic_inc(&mtt->ref_count);
  1499. qp->mtt = mtt;
  1500. atomic_inc(&rcq->ref_count);
  1501. qp->rcq = rcq;
  1502. atomic_inc(&scq->ref_count);
  1503. qp->scq = scq;
  1504. if (scqn != rcqn)
  1505. put_res(dev, slave, scqn, RES_CQ);
  1506. if (use_srq) {
  1507. atomic_inc(&srq->ref_count);
  1508. put_res(dev, slave, srqn, RES_SRQ);
  1509. qp->srq = srq;
  1510. }
  1511. put_res(dev, slave, rcqn, RES_CQ);
  1512. put_res(dev, slave, mtt_base, RES_MTT);
  1513. res_end_move(dev, slave, RES_QP, qpn);
  1514. return 0;
  1515. ex_put_srq:
  1516. if (use_srq)
  1517. put_res(dev, slave, srqn, RES_SRQ);
  1518. ex_put_scq:
  1519. if (scqn != rcqn)
  1520. put_res(dev, slave, scqn, RES_CQ);
  1521. ex_put_rcq:
  1522. put_res(dev, slave, rcqn, RES_CQ);
  1523. ex_put_mtt:
  1524. put_res(dev, slave, mtt_base, RES_MTT);
  1525. ex_abort:
  1526. res_abort_move(dev, slave, RES_QP, qpn);
  1527. return err;
  1528. }
  1529. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  1530. {
  1531. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  1532. }
  1533. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  1534. {
  1535. int log_eq_size = eqc->log_eq_size & 0x1f;
  1536. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  1537. if (log_eq_size + 5 < page_shift)
  1538. return 1;
  1539. return 1 << (log_eq_size + 5 - page_shift);
  1540. }
  1541. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  1542. {
  1543. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  1544. }
  1545. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  1546. {
  1547. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  1548. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  1549. if (log_cq_size + 5 < page_shift)
  1550. return 1;
  1551. return 1 << (log_cq_size + 5 - page_shift);
  1552. }
  1553. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1554. struct mlx4_vhcr *vhcr,
  1555. struct mlx4_cmd_mailbox *inbox,
  1556. struct mlx4_cmd_mailbox *outbox,
  1557. struct mlx4_cmd_info *cmd)
  1558. {
  1559. int err;
  1560. int eqn = vhcr->in_modifier;
  1561. int res_id = (slave << 8) | eqn;
  1562. struct mlx4_eq_context *eqc = inbox->buf;
  1563. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  1564. int mtt_size = eq_get_mtt_size(eqc);
  1565. struct res_eq *eq;
  1566. struct res_mtt *mtt;
  1567. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1568. if (err)
  1569. return err;
  1570. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  1571. if (err)
  1572. goto out_add;
  1573. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1574. if (err)
  1575. goto out_move;
  1576. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1577. if (err)
  1578. goto out_put;
  1579. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1580. if (err)
  1581. goto out_put;
  1582. atomic_inc(&mtt->ref_count);
  1583. eq->mtt = mtt;
  1584. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1585. res_end_move(dev, slave, RES_EQ, res_id);
  1586. return 0;
  1587. out_put:
  1588. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1589. out_move:
  1590. res_abort_move(dev, slave, RES_EQ, res_id);
  1591. out_add:
  1592. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1593. return err;
  1594. }
  1595. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  1596. int len, struct res_mtt **res)
  1597. {
  1598. struct mlx4_priv *priv = mlx4_priv(dev);
  1599. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1600. struct res_mtt *mtt;
  1601. int err = -EINVAL;
  1602. spin_lock_irq(mlx4_tlock(dev));
  1603. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  1604. com.list) {
  1605. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  1606. *res = mtt;
  1607. mtt->com.from_state = mtt->com.state;
  1608. mtt->com.state = RES_MTT_BUSY;
  1609. err = 0;
  1610. break;
  1611. }
  1612. }
  1613. spin_unlock_irq(mlx4_tlock(dev));
  1614. return err;
  1615. }
  1616. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  1617. struct mlx4_vhcr *vhcr,
  1618. struct mlx4_cmd_mailbox *inbox,
  1619. struct mlx4_cmd_mailbox *outbox,
  1620. struct mlx4_cmd_info *cmd)
  1621. {
  1622. struct mlx4_mtt mtt;
  1623. __be64 *page_list = inbox->buf;
  1624. u64 *pg_list = (u64 *)page_list;
  1625. int i;
  1626. struct res_mtt *rmtt = NULL;
  1627. int start = be64_to_cpu(page_list[0]);
  1628. int npages = vhcr->in_modifier;
  1629. int err;
  1630. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  1631. if (err)
  1632. return err;
  1633. /* Call the SW implementation of write_mtt:
  1634. * - Prepare a dummy mtt struct
  1635. * - Translate inbox contents to simple addresses in host endianess */
  1636. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  1637. we don't really use it */
  1638. mtt.order = 0;
  1639. mtt.page_shift = 0;
  1640. for (i = 0; i < npages; ++i)
  1641. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  1642. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  1643. ((u64 *)page_list + 2));
  1644. if (rmtt)
  1645. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  1646. return err;
  1647. }
  1648. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1649. struct mlx4_vhcr *vhcr,
  1650. struct mlx4_cmd_mailbox *inbox,
  1651. struct mlx4_cmd_mailbox *outbox,
  1652. struct mlx4_cmd_info *cmd)
  1653. {
  1654. int eqn = vhcr->in_modifier;
  1655. int res_id = eqn | (slave << 8);
  1656. struct res_eq *eq;
  1657. int err;
  1658. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  1659. if (err)
  1660. return err;
  1661. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  1662. if (err)
  1663. goto ex_abort;
  1664. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1665. if (err)
  1666. goto ex_put;
  1667. atomic_dec(&eq->mtt->ref_count);
  1668. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1669. res_end_move(dev, slave, RES_EQ, res_id);
  1670. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1671. return 0;
  1672. ex_put:
  1673. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1674. ex_abort:
  1675. res_abort_move(dev, slave, RES_EQ, res_id);
  1676. return err;
  1677. }
  1678. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  1679. {
  1680. struct mlx4_priv *priv = mlx4_priv(dev);
  1681. struct mlx4_slave_event_eq_info *event_eq;
  1682. struct mlx4_cmd_mailbox *mailbox;
  1683. u32 in_modifier = 0;
  1684. int err;
  1685. int res_id;
  1686. struct res_eq *req;
  1687. if (!priv->mfunc.master.slave_state)
  1688. return -EINVAL;
  1689. event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
  1690. /* Create the event only if the slave is registered */
  1691. if (event_eq->eqn < 0)
  1692. return 0;
  1693. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1694. res_id = (slave << 8) | event_eq->eqn;
  1695. err = get_res(dev, slave, res_id, RES_EQ, &req);
  1696. if (err)
  1697. goto unlock;
  1698. if (req->com.from_state != RES_EQ_HW) {
  1699. err = -EINVAL;
  1700. goto put;
  1701. }
  1702. mailbox = mlx4_alloc_cmd_mailbox(dev);
  1703. if (IS_ERR(mailbox)) {
  1704. err = PTR_ERR(mailbox);
  1705. goto put;
  1706. }
  1707. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  1708. ++event_eq->token;
  1709. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  1710. }
  1711. memcpy(mailbox->buf, (u8 *) eqe, 28);
  1712. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
  1713. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  1714. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  1715. MLX4_CMD_NATIVE);
  1716. put_res(dev, slave, res_id, RES_EQ);
  1717. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1718. mlx4_free_cmd_mailbox(dev, mailbox);
  1719. return err;
  1720. put:
  1721. put_res(dev, slave, res_id, RES_EQ);
  1722. unlock:
  1723. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1724. return err;
  1725. }
  1726. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1727. struct mlx4_vhcr *vhcr,
  1728. struct mlx4_cmd_mailbox *inbox,
  1729. struct mlx4_cmd_mailbox *outbox,
  1730. struct mlx4_cmd_info *cmd)
  1731. {
  1732. int eqn = vhcr->in_modifier;
  1733. int res_id = eqn | (slave << 8);
  1734. struct res_eq *eq;
  1735. int err;
  1736. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  1737. if (err)
  1738. return err;
  1739. if (eq->com.from_state != RES_EQ_HW) {
  1740. err = -EINVAL;
  1741. goto ex_put;
  1742. }
  1743. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1744. ex_put:
  1745. put_res(dev, slave, res_id, RES_EQ);
  1746. return err;
  1747. }
  1748. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1749. struct mlx4_vhcr *vhcr,
  1750. struct mlx4_cmd_mailbox *inbox,
  1751. struct mlx4_cmd_mailbox *outbox,
  1752. struct mlx4_cmd_info *cmd)
  1753. {
  1754. int err;
  1755. int cqn = vhcr->in_modifier;
  1756. struct mlx4_cq_context *cqc = inbox->buf;
  1757. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1758. struct res_cq *cq;
  1759. struct res_mtt *mtt;
  1760. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  1761. if (err)
  1762. return err;
  1763. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1764. if (err)
  1765. goto out_move;
  1766. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  1767. if (err)
  1768. goto out_put;
  1769. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1770. if (err)
  1771. goto out_put;
  1772. atomic_inc(&mtt->ref_count);
  1773. cq->mtt = mtt;
  1774. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1775. res_end_move(dev, slave, RES_CQ, cqn);
  1776. return 0;
  1777. out_put:
  1778. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1779. out_move:
  1780. res_abort_move(dev, slave, RES_CQ, cqn);
  1781. return err;
  1782. }
  1783. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1784. struct mlx4_vhcr *vhcr,
  1785. struct mlx4_cmd_mailbox *inbox,
  1786. struct mlx4_cmd_mailbox *outbox,
  1787. struct mlx4_cmd_info *cmd)
  1788. {
  1789. int err;
  1790. int cqn = vhcr->in_modifier;
  1791. struct res_cq *cq;
  1792. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  1793. if (err)
  1794. return err;
  1795. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1796. if (err)
  1797. goto out_move;
  1798. atomic_dec(&cq->mtt->ref_count);
  1799. res_end_move(dev, slave, RES_CQ, cqn);
  1800. return 0;
  1801. out_move:
  1802. res_abort_move(dev, slave, RES_CQ, cqn);
  1803. return err;
  1804. }
  1805. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1806. struct mlx4_vhcr *vhcr,
  1807. struct mlx4_cmd_mailbox *inbox,
  1808. struct mlx4_cmd_mailbox *outbox,
  1809. struct mlx4_cmd_info *cmd)
  1810. {
  1811. int cqn = vhcr->in_modifier;
  1812. struct res_cq *cq;
  1813. int err;
  1814. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  1815. if (err)
  1816. return err;
  1817. if (cq->com.from_state != RES_CQ_HW)
  1818. goto ex_put;
  1819. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1820. ex_put:
  1821. put_res(dev, slave, cqn, RES_CQ);
  1822. return err;
  1823. }
  1824. static int handle_resize(struct mlx4_dev *dev, int slave,
  1825. struct mlx4_vhcr *vhcr,
  1826. struct mlx4_cmd_mailbox *inbox,
  1827. struct mlx4_cmd_mailbox *outbox,
  1828. struct mlx4_cmd_info *cmd,
  1829. struct res_cq *cq)
  1830. {
  1831. int err;
  1832. struct res_mtt *orig_mtt;
  1833. struct res_mtt *mtt;
  1834. struct mlx4_cq_context *cqc = inbox->buf;
  1835. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1836. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  1837. if (err)
  1838. return err;
  1839. if (orig_mtt != cq->mtt) {
  1840. err = -EINVAL;
  1841. goto ex_put;
  1842. }
  1843. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1844. if (err)
  1845. goto ex_put;
  1846. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  1847. if (err)
  1848. goto ex_put1;
  1849. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1850. if (err)
  1851. goto ex_put1;
  1852. atomic_dec(&orig_mtt->ref_count);
  1853. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  1854. atomic_inc(&mtt->ref_count);
  1855. cq->mtt = mtt;
  1856. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1857. return 0;
  1858. ex_put1:
  1859. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1860. ex_put:
  1861. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  1862. return err;
  1863. }
  1864. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1865. struct mlx4_vhcr *vhcr,
  1866. struct mlx4_cmd_mailbox *inbox,
  1867. struct mlx4_cmd_mailbox *outbox,
  1868. struct mlx4_cmd_info *cmd)
  1869. {
  1870. int cqn = vhcr->in_modifier;
  1871. struct res_cq *cq;
  1872. int err;
  1873. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  1874. if (err)
  1875. return err;
  1876. if (cq->com.from_state != RES_CQ_HW)
  1877. goto ex_put;
  1878. if (vhcr->op_modifier == 0) {
  1879. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  1880. if (err)
  1881. goto ex_put;
  1882. }
  1883. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1884. ex_put:
  1885. put_res(dev, slave, cqn, RES_CQ);
  1886. return err;
  1887. }
  1888. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  1889. {
  1890. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  1891. int log_rq_stride = srqc->logstride & 7;
  1892. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  1893. if (log_srq_size + log_rq_stride + 4 < page_shift)
  1894. return 1;
  1895. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  1896. }
  1897. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1898. struct mlx4_vhcr *vhcr,
  1899. struct mlx4_cmd_mailbox *inbox,
  1900. struct mlx4_cmd_mailbox *outbox,
  1901. struct mlx4_cmd_info *cmd)
  1902. {
  1903. int err;
  1904. int srqn = vhcr->in_modifier;
  1905. struct res_mtt *mtt;
  1906. struct res_srq *srq;
  1907. struct mlx4_srq_context *srqc = inbox->buf;
  1908. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  1909. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  1910. return -EINVAL;
  1911. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  1912. if (err)
  1913. return err;
  1914. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1915. if (err)
  1916. goto ex_abort;
  1917. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  1918. mtt);
  1919. if (err)
  1920. goto ex_put_mtt;
  1921. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1922. if (err)
  1923. goto ex_put_mtt;
  1924. atomic_inc(&mtt->ref_count);
  1925. srq->mtt = mtt;
  1926. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1927. res_end_move(dev, slave, RES_SRQ, srqn);
  1928. return 0;
  1929. ex_put_mtt:
  1930. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1931. ex_abort:
  1932. res_abort_move(dev, slave, RES_SRQ, srqn);
  1933. return err;
  1934. }
  1935. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1936. struct mlx4_vhcr *vhcr,
  1937. struct mlx4_cmd_mailbox *inbox,
  1938. struct mlx4_cmd_mailbox *outbox,
  1939. struct mlx4_cmd_info *cmd)
  1940. {
  1941. int err;
  1942. int srqn = vhcr->in_modifier;
  1943. struct res_srq *srq;
  1944. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  1945. if (err)
  1946. return err;
  1947. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1948. if (err)
  1949. goto ex_abort;
  1950. atomic_dec(&srq->mtt->ref_count);
  1951. if (srq->cq)
  1952. atomic_dec(&srq->cq->ref_count);
  1953. res_end_move(dev, slave, RES_SRQ, srqn);
  1954. return 0;
  1955. ex_abort:
  1956. res_abort_move(dev, slave, RES_SRQ, srqn);
  1957. return err;
  1958. }
  1959. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1960. struct mlx4_vhcr *vhcr,
  1961. struct mlx4_cmd_mailbox *inbox,
  1962. struct mlx4_cmd_mailbox *outbox,
  1963. struct mlx4_cmd_info *cmd)
  1964. {
  1965. int err;
  1966. int srqn = vhcr->in_modifier;
  1967. struct res_srq *srq;
  1968. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1969. if (err)
  1970. return err;
  1971. if (srq->com.from_state != RES_SRQ_HW) {
  1972. err = -EBUSY;
  1973. goto out;
  1974. }
  1975. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1976. out:
  1977. put_res(dev, slave, srqn, RES_SRQ);
  1978. return err;
  1979. }
  1980. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1981. struct mlx4_vhcr *vhcr,
  1982. struct mlx4_cmd_mailbox *inbox,
  1983. struct mlx4_cmd_mailbox *outbox,
  1984. struct mlx4_cmd_info *cmd)
  1985. {
  1986. int err;
  1987. int srqn = vhcr->in_modifier;
  1988. struct res_srq *srq;
  1989. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1990. if (err)
  1991. return err;
  1992. if (srq->com.from_state != RES_SRQ_HW) {
  1993. err = -EBUSY;
  1994. goto out;
  1995. }
  1996. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1997. out:
  1998. put_res(dev, slave, srqn, RES_SRQ);
  1999. return err;
  2000. }
  2001. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  2002. struct mlx4_vhcr *vhcr,
  2003. struct mlx4_cmd_mailbox *inbox,
  2004. struct mlx4_cmd_mailbox *outbox,
  2005. struct mlx4_cmd_info *cmd)
  2006. {
  2007. int err;
  2008. int qpn = vhcr->in_modifier & 0x7fffff;
  2009. struct res_qp *qp;
  2010. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2011. if (err)
  2012. return err;
  2013. if (qp->com.from_state != RES_QP_HW) {
  2014. err = -EBUSY;
  2015. goto out;
  2016. }
  2017. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2018. out:
  2019. put_res(dev, slave, qpn, RES_QP);
  2020. return err;
  2021. }
  2022. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  2023. struct mlx4_vhcr *vhcr,
  2024. struct mlx4_cmd_mailbox *inbox,
  2025. struct mlx4_cmd_mailbox *outbox,
  2026. struct mlx4_cmd_info *cmd)
  2027. {
  2028. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2029. update_ud_gid(dev, qpc, (u8)slave);
  2030. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2031. }
  2032. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  2033. struct mlx4_vhcr *vhcr,
  2034. struct mlx4_cmd_mailbox *inbox,
  2035. struct mlx4_cmd_mailbox *outbox,
  2036. struct mlx4_cmd_info *cmd)
  2037. {
  2038. int err;
  2039. int qpn = vhcr->in_modifier & 0x7fffff;
  2040. struct res_qp *qp;
  2041. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  2042. if (err)
  2043. return err;
  2044. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2045. if (err)
  2046. goto ex_abort;
  2047. atomic_dec(&qp->mtt->ref_count);
  2048. atomic_dec(&qp->rcq->ref_count);
  2049. atomic_dec(&qp->scq->ref_count);
  2050. if (qp->srq)
  2051. atomic_dec(&qp->srq->ref_count);
  2052. res_end_move(dev, slave, RES_QP, qpn);
  2053. return 0;
  2054. ex_abort:
  2055. res_abort_move(dev, slave, RES_QP, qpn);
  2056. return err;
  2057. }
  2058. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  2059. struct res_qp *rqp, u8 *gid)
  2060. {
  2061. struct res_gid *res;
  2062. list_for_each_entry(res, &rqp->mcg_list, list) {
  2063. if (!memcmp(res->gid, gid, 16))
  2064. return res;
  2065. }
  2066. return NULL;
  2067. }
  2068. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2069. u8 *gid, enum mlx4_protocol prot)
  2070. {
  2071. struct res_gid *res;
  2072. int err;
  2073. res = kzalloc(sizeof *res, GFP_KERNEL);
  2074. if (!res)
  2075. return -ENOMEM;
  2076. spin_lock_irq(&rqp->mcg_spl);
  2077. if (find_gid(dev, slave, rqp, gid)) {
  2078. kfree(res);
  2079. err = -EEXIST;
  2080. } else {
  2081. memcpy(res->gid, gid, 16);
  2082. res->prot = prot;
  2083. list_add_tail(&res->list, &rqp->mcg_list);
  2084. err = 0;
  2085. }
  2086. spin_unlock_irq(&rqp->mcg_spl);
  2087. return err;
  2088. }
  2089. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2090. u8 *gid, enum mlx4_protocol prot)
  2091. {
  2092. struct res_gid *res;
  2093. int err;
  2094. spin_lock_irq(&rqp->mcg_spl);
  2095. res = find_gid(dev, slave, rqp, gid);
  2096. if (!res || res->prot != prot)
  2097. err = -EINVAL;
  2098. else {
  2099. list_del(&res->list);
  2100. kfree(res);
  2101. err = 0;
  2102. }
  2103. spin_unlock_irq(&rqp->mcg_spl);
  2104. return err;
  2105. }
  2106. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2107. struct mlx4_vhcr *vhcr,
  2108. struct mlx4_cmd_mailbox *inbox,
  2109. struct mlx4_cmd_mailbox *outbox,
  2110. struct mlx4_cmd_info *cmd)
  2111. {
  2112. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2113. u8 *gid = inbox->buf;
  2114. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  2115. int err, err1;
  2116. int qpn;
  2117. struct res_qp *rqp;
  2118. int attach = vhcr->op_modifier;
  2119. int block_loopback = vhcr->in_modifier >> 31;
  2120. u8 steer_type_mask = 2;
  2121. enum mlx4_steer_type type = gid[7] & steer_type_mask;
  2122. qpn = vhcr->in_modifier & 0xffffff;
  2123. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2124. if (err)
  2125. return err;
  2126. qp.qpn = qpn;
  2127. if (attach) {
  2128. err = add_mcg_res(dev, slave, rqp, gid, prot);
  2129. if (err)
  2130. goto ex_put;
  2131. err = mlx4_qp_attach_common(dev, &qp, gid,
  2132. block_loopback, prot, type);
  2133. if (err)
  2134. goto ex_rem;
  2135. } else {
  2136. err = rem_mcg_res(dev, slave, rqp, gid, prot);
  2137. if (err)
  2138. goto ex_put;
  2139. err = mlx4_qp_detach_common(dev, &qp, gid, prot, type);
  2140. }
  2141. put_res(dev, slave, qpn, RES_QP);
  2142. return 0;
  2143. ex_rem:
  2144. /* ignore error return below, already in error */
  2145. err1 = rem_mcg_res(dev, slave, rqp, gid, prot);
  2146. ex_put:
  2147. put_res(dev, slave, qpn, RES_QP);
  2148. return err;
  2149. }
  2150. enum {
  2151. BUSY_MAX_RETRIES = 10
  2152. };
  2153. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  2154. struct mlx4_vhcr *vhcr,
  2155. struct mlx4_cmd_mailbox *inbox,
  2156. struct mlx4_cmd_mailbox *outbox,
  2157. struct mlx4_cmd_info *cmd)
  2158. {
  2159. int err;
  2160. int index = vhcr->in_modifier & 0xffff;
  2161. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  2162. if (err)
  2163. return err;
  2164. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2165. put_res(dev, slave, index, RES_COUNTER);
  2166. return err;
  2167. }
  2168. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  2169. {
  2170. struct res_gid *rgid;
  2171. struct res_gid *tmp;
  2172. int err;
  2173. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2174. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  2175. qp.qpn = rqp->local_qpn;
  2176. err = mlx4_qp_detach_common(dev, &qp, rgid->gid, rgid->prot,
  2177. MLX4_MC_STEER);
  2178. list_del(&rgid->list);
  2179. kfree(rgid);
  2180. }
  2181. }
  2182. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  2183. enum mlx4_resource type, int print)
  2184. {
  2185. struct mlx4_priv *priv = mlx4_priv(dev);
  2186. struct mlx4_resource_tracker *tracker =
  2187. &priv->mfunc.master.res_tracker;
  2188. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  2189. struct res_common *r;
  2190. struct res_common *tmp;
  2191. int busy;
  2192. busy = 0;
  2193. spin_lock_irq(mlx4_tlock(dev));
  2194. list_for_each_entry_safe(r, tmp, rlist, list) {
  2195. if (r->owner == slave) {
  2196. if (!r->removing) {
  2197. if (r->state == RES_ANY_BUSY) {
  2198. if (print)
  2199. mlx4_dbg(dev,
  2200. "%s id 0x%x is busy\n",
  2201. ResourceType(type),
  2202. r->res_id);
  2203. ++busy;
  2204. } else {
  2205. r->from_state = r->state;
  2206. r->state = RES_ANY_BUSY;
  2207. r->removing = 1;
  2208. }
  2209. }
  2210. }
  2211. }
  2212. spin_unlock_irq(mlx4_tlock(dev));
  2213. return busy;
  2214. }
  2215. static int move_all_busy(struct mlx4_dev *dev, int slave,
  2216. enum mlx4_resource type)
  2217. {
  2218. unsigned long begin;
  2219. int busy;
  2220. begin = jiffies;
  2221. do {
  2222. busy = _move_all_busy(dev, slave, type, 0);
  2223. if (time_after(jiffies, begin + 5 * HZ))
  2224. break;
  2225. if (busy)
  2226. cond_resched();
  2227. } while (busy);
  2228. if (busy)
  2229. busy = _move_all_busy(dev, slave, type, 1);
  2230. return busy;
  2231. }
  2232. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  2233. {
  2234. struct mlx4_priv *priv = mlx4_priv(dev);
  2235. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2236. struct list_head *qp_list =
  2237. &tracker->slave_list[slave].res_list[RES_QP];
  2238. struct res_qp *qp;
  2239. struct res_qp *tmp;
  2240. int state;
  2241. u64 in_param;
  2242. int qpn;
  2243. int err;
  2244. err = move_all_busy(dev, slave, RES_QP);
  2245. if (err)
  2246. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
  2247. "for slave %d\n", slave);
  2248. spin_lock_irq(mlx4_tlock(dev));
  2249. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  2250. spin_unlock_irq(mlx4_tlock(dev));
  2251. if (qp->com.owner == slave) {
  2252. qpn = qp->com.res_id;
  2253. detach_qp(dev, slave, qp);
  2254. state = qp->com.from_state;
  2255. while (state != 0) {
  2256. switch (state) {
  2257. case RES_QP_RESERVED:
  2258. spin_lock_irq(mlx4_tlock(dev));
  2259. radix_tree_delete(&tracker->res_tree[RES_QP],
  2260. qp->com.res_id);
  2261. list_del(&qp->com.list);
  2262. spin_unlock_irq(mlx4_tlock(dev));
  2263. kfree(qp);
  2264. state = 0;
  2265. break;
  2266. case RES_QP_MAPPED:
  2267. if (!valid_reserved(dev, slave, qpn))
  2268. __mlx4_qp_free_icm(dev, qpn);
  2269. state = RES_QP_RESERVED;
  2270. break;
  2271. case RES_QP_HW:
  2272. in_param = slave;
  2273. err = mlx4_cmd(dev, in_param,
  2274. qp->local_qpn, 2,
  2275. MLX4_CMD_2RST_QP,
  2276. MLX4_CMD_TIME_CLASS_A,
  2277. MLX4_CMD_NATIVE);
  2278. if (err)
  2279. mlx4_dbg(dev, "rem_slave_qps: failed"
  2280. " to move slave %d qpn %d to"
  2281. " reset\n", slave,
  2282. qp->local_qpn);
  2283. atomic_dec(&qp->rcq->ref_count);
  2284. atomic_dec(&qp->scq->ref_count);
  2285. atomic_dec(&qp->mtt->ref_count);
  2286. if (qp->srq)
  2287. atomic_dec(&qp->srq->ref_count);
  2288. state = RES_QP_MAPPED;
  2289. break;
  2290. default:
  2291. state = 0;
  2292. }
  2293. }
  2294. }
  2295. spin_lock_irq(mlx4_tlock(dev));
  2296. }
  2297. spin_unlock_irq(mlx4_tlock(dev));
  2298. }
  2299. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  2300. {
  2301. struct mlx4_priv *priv = mlx4_priv(dev);
  2302. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2303. struct list_head *srq_list =
  2304. &tracker->slave_list[slave].res_list[RES_SRQ];
  2305. struct res_srq *srq;
  2306. struct res_srq *tmp;
  2307. int state;
  2308. u64 in_param;
  2309. LIST_HEAD(tlist);
  2310. int srqn;
  2311. int err;
  2312. err = move_all_busy(dev, slave, RES_SRQ);
  2313. if (err)
  2314. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
  2315. "busy for slave %d\n", slave);
  2316. spin_lock_irq(mlx4_tlock(dev));
  2317. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  2318. spin_unlock_irq(mlx4_tlock(dev));
  2319. if (srq->com.owner == slave) {
  2320. srqn = srq->com.res_id;
  2321. state = srq->com.from_state;
  2322. while (state != 0) {
  2323. switch (state) {
  2324. case RES_SRQ_ALLOCATED:
  2325. __mlx4_srq_free_icm(dev, srqn);
  2326. spin_lock_irq(mlx4_tlock(dev));
  2327. radix_tree_delete(&tracker->res_tree[RES_SRQ],
  2328. srqn);
  2329. list_del(&srq->com.list);
  2330. spin_unlock_irq(mlx4_tlock(dev));
  2331. kfree(srq);
  2332. state = 0;
  2333. break;
  2334. case RES_SRQ_HW:
  2335. in_param = slave;
  2336. err = mlx4_cmd(dev, in_param, srqn, 1,
  2337. MLX4_CMD_HW2SW_SRQ,
  2338. MLX4_CMD_TIME_CLASS_A,
  2339. MLX4_CMD_NATIVE);
  2340. if (err)
  2341. mlx4_dbg(dev, "rem_slave_srqs: failed"
  2342. " to move slave %d srq %d to"
  2343. " SW ownership\n",
  2344. slave, srqn);
  2345. atomic_dec(&srq->mtt->ref_count);
  2346. if (srq->cq)
  2347. atomic_dec(&srq->cq->ref_count);
  2348. state = RES_SRQ_ALLOCATED;
  2349. break;
  2350. default:
  2351. state = 0;
  2352. }
  2353. }
  2354. }
  2355. spin_lock_irq(mlx4_tlock(dev));
  2356. }
  2357. spin_unlock_irq(mlx4_tlock(dev));
  2358. }
  2359. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  2360. {
  2361. struct mlx4_priv *priv = mlx4_priv(dev);
  2362. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2363. struct list_head *cq_list =
  2364. &tracker->slave_list[slave].res_list[RES_CQ];
  2365. struct res_cq *cq;
  2366. struct res_cq *tmp;
  2367. int state;
  2368. u64 in_param;
  2369. LIST_HEAD(tlist);
  2370. int cqn;
  2371. int err;
  2372. err = move_all_busy(dev, slave, RES_CQ);
  2373. if (err)
  2374. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
  2375. "busy for slave %d\n", slave);
  2376. spin_lock_irq(mlx4_tlock(dev));
  2377. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  2378. spin_unlock_irq(mlx4_tlock(dev));
  2379. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  2380. cqn = cq->com.res_id;
  2381. state = cq->com.from_state;
  2382. while (state != 0) {
  2383. switch (state) {
  2384. case RES_CQ_ALLOCATED:
  2385. __mlx4_cq_free_icm(dev, cqn);
  2386. spin_lock_irq(mlx4_tlock(dev));
  2387. radix_tree_delete(&tracker->res_tree[RES_CQ],
  2388. cqn);
  2389. list_del(&cq->com.list);
  2390. spin_unlock_irq(mlx4_tlock(dev));
  2391. kfree(cq);
  2392. state = 0;
  2393. break;
  2394. case RES_CQ_HW:
  2395. in_param = slave;
  2396. err = mlx4_cmd(dev, in_param, cqn, 1,
  2397. MLX4_CMD_HW2SW_CQ,
  2398. MLX4_CMD_TIME_CLASS_A,
  2399. MLX4_CMD_NATIVE);
  2400. if (err)
  2401. mlx4_dbg(dev, "rem_slave_cqs: failed"
  2402. " to move slave %d cq %d to"
  2403. " SW ownership\n",
  2404. slave, cqn);
  2405. atomic_dec(&cq->mtt->ref_count);
  2406. state = RES_CQ_ALLOCATED;
  2407. break;
  2408. default:
  2409. state = 0;
  2410. }
  2411. }
  2412. }
  2413. spin_lock_irq(mlx4_tlock(dev));
  2414. }
  2415. spin_unlock_irq(mlx4_tlock(dev));
  2416. }
  2417. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  2418. {
  2419. struct mlx4_priv *priv = mlx4_priv(dev);
  2420. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2421. struct list_head *mpt_list =
  2422. &tracker->slave_list[slave].res_list[RES_MPT];
  2423. struct res_mpt *mpt;
  2424. struct res_mpt *tmp;
  2425. int state;
  2426. u64 in_param;
  2427. LIST_HEAD(tlist);
  2428. int mptn;
  2429. int err;
  2430. err = move_all_busy(dev, slave, RES_MPT);
  2431. if (err)
  2432. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
  2433. "busy for slave %d\n", slave);
  2434. spin_lock_irq(mlx4_tlock(dev));
  2435. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  2436. spin_unlock_irq(mlx4_tlock(dev));
  2437. if (mpt->com.owner == slave) {
  2438. mptn = mpt->com.res_id;
  2439. state = mpt->com.from_state;
  2440. while (state != 0) {
  2441. switch (state) {
  2442. case RES_MPT_RESERVED:
  2443. __mlx4_mr_release(dev, mpt->key);
  2444. spin_lock_irq(mlx4_tlock(dev));
  2445. radix_tree_delete(&tracker->res_tree[RES_MPT],
  2446. mptn);
  2447. list_del(&mpt->com.list);
  2448. spin_unlock_irq(mlx4_tlock(dev));
  2449. kfree(mpt);
  2450. state = 0;
  2451. break;
  2452. case RES_MPT_MAPPED:
  2453. __mlx4_mr_free_icm(dev, mpt->key);
  2454. state = RES_MPT_RESERVED;
  2455. break;
  2456. case RES_MPT_HW:
  2457. in_param = slave;
  2458. err = mlx4_cmd(dev, in_param, mptn, 0,
  2459. MLX4_CMD_HW2SW_MPT,
  2460. MLX4_CMD_TIME_CLASS_A,
  2461. MLX4_CMD_NATIVE);
  2462. if (err)
  2463. mlx4_dbg(dev, "rem_slave_mrs: failed"
  2464. " to move slave %d mpt %d to"
  2465. " SW ownership\n",
  2466. slave, mptn);
  2467. if (mpt->mtt)
  2468. atomic_dec(&mpt->mtt->ref_count);
  2469. state = RES_MPT_MAPPED;
  2470. break;
  2471. default:
  2472. state = 0;
  2473. }
  2474. }
  2475. }
  2476. spin_lock_irq(mlx4_tlock(dev));
  2477. }
  2478. spin_unlock_irq(mlx4_tlock(dev));
  2479. }
  2480. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  2481. {
  2482. struct mlx4_priv *priv = mlx4_priv(dev);
  2483. struct mlx4_resource_tracker *tracker =
  2484. &priv->mfunc.master.res_tracker;
  2485. struct list_head *mtt_list =
  2486. &tracker->slave_list[slave].res_list[RES_MTT];
  2487. struct res_mtt *mtt;
  2488. struct res_mtt *tmp;
  2489. int state;
  2490. LIST_HEAD(tlist);
  2491. int base;
  2492. int err;
  2493. err = move_all_busy(dev, slave, RES_MTT);
  2494. if (err)
  2495. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
  2496. "busy for slave %d\n", slave);
  2497. spin_lock_irq(mlx4_tlock(dev));
  2498. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  2499. spin_unlock_irq(mlx4_tlock(dev));
  2500. if (mtt->com.owner == slave) {
  2501. base = mtt->com.res_id;
  2502. state = mtt->com.from_state;
  2503. while (state != 0) {
  2504. switch (state) {
  2505. case RES_MTT_ALLOCATED:
  2506. __mlx4_free_mtt_range(dev, base,
  2507. mtt->order);
  2508. spin_lock_irq(mlx4_tlock(dev));
  2509. radix_tree_delete(&tracker->res_tree[RES_MTT],
  2510. base);
  2511. list_del(&mtt->com.list);
  2512. spin_unlock_irq(mlx4_tlock(dev));
  2513. kfree(mtt);
  2514. state = 0;
  2515. break;
  2516. default:
  2517. state = 0;
  2518. }
  2519. }
  2520. }
  2521. spin_lock_irq(mlx4_tlock(dev));
  2522. }
  2523. spin_unlock_irq(mlx4_tlock(dev));
  2524. }
  2525. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  2526. {
  2527. struct mlx4_priv *priv = mlx4_priv(dev);
  2528. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2529. struct list_head *eq_list =
  2530. &tracker->slave_list[slave].res_list[RES_EQ];
  2531. struct res_eq *eq;
  2532. struct res_eq *tmp;
  2533. int err;
  2534. int state;
  2535. LIST_HEAD(tlist);
  2536. int eqn;
  2537. struct mlx4_cmd_mailbox *mailbox;
  2538. err = move_all_busy(dev, slave, RES_EQ);
  2539. if (err)
  2540. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
  2541. "busy for slave %d\n", slave);
  2542. spin_lock_irq(mlx4_tlock(dev));
  2543. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  2544. spin_unlock_irq(mlx4_tlock(dev));
  2545. if (eq->com.owner == slave) {
  2546. eqn = eq->com.res_id;
  2547. state = eq->com.from_state;
  2548. while (state != 0) {
  2549. switch (state) {
  2550. case RES_EQ_RESERVED:
  2551. spin_lock_irq(mlx4_tlock(dev));
  2552. radix_tree_delete(&tracker->res_tree[RES_EQ],
  2553. eqn);
  2554. list_del(&eq->com.list);
  2555. spin_unlock_irq(mlx4_tlock(dev));
  2556. kfree(eq);
  2557. state = 0;
  2558. break;
  2559. case RES_EQ_HW:
  2560. mailbox = mlx4_alloc_cmd_mailbox(dev);
  2561. if (IS_ERR(mailbox)) {
  2562. cond_resched();
  2563. continue;
  2564. }
  2565. err = mlx4_cmd_box(dev, slave, 0,
  2566. eqn & 0xff, 0,
  2567. MLX4_CMD_HW2SW_EQ,
  2568. MLX4_CMD_TIME_CLASS_A,
  2569. MLX4_CMD_NATIVE);
  2570. mlx4_dbg(dev, "rem_slave_eqs: failed"
  2571. " to move slave %d eqs %d to"
  2572. " SW ownership\n", slave, eqn);
  2573. mlx4_free_cmd_mailbox(dev, mailbox);
  2574. if (!err) {
  2575. atomic_dec(&eq->mtt->ref_count);
  2576. state = RES_EQ_RESERVED;
  2577. }
  2578. break;
  2579. default:
  2580. state = 0;
  2581. }
  2582. }
  2583. }
  2584. spin_lock_irq(mlx4_tlock(dev));
  2585. }
  2586. spin_unlock_irq(mlx4_tlock(dev));
  2587. }
  2588. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  2589. {
  2590. struct mlx4_priv *priv = mlx4_priv(dev);
  2591. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2592. /*VLAN*/
  2593. rem_slave_macs(dev, slave);
  2594. rem_slave_qps(dev, slave);
  2595. rem_slave_srqs(dev, slave);
  2596. rem_slave_cqs(dev, slave);
  2597. rem_slave_mrs(dev, slave);
  2598. rem_slave_eqs(dev, slave);
  2599. rem_slave_mtts(dev, slave);
  2600. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2601. }