en_rx.c 26 KB

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  1. /*
  2. * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. */
  33. #include <linux/mlx4/cq.h>
  34. #include <linux/slab.h>
  35. #include <linux/mlx4/qp.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/if_ether.h>
  38. #include <linux/if_vlan.h>
  39. #include <linux/vmalloc.h>
  40. #include "mlx4_en.h"
  41. static int mlx4_en_alloc_frag(struct mlx4_en_priv *priv,
  42. struct mlx4_en_rx_desc *rx_desc,
  43. struct page_frag *skb_frags,
  44. struct mlx4_en_rx_alloc *ring_alloc,
  45. int i)
  46. {
  47. struct mlx4_en_dev *mdev = priv->mdev;
  48. struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
  49. struct mlx4_en_rx_alloc *page_alloc = &ring_alloc[i];
  50. struct page *page;
  51. dma_addr_t dma;
  52. if (page_alloc->offset == frag_info->last_offset) {
  53. /* Allocate new page */
  54. page = alloc_pages(GFP_ATOMIC | __GFP_COMP, MLX4_EN_ALLOC_ORDER);
  55. if (!page)
  56. return -ENOMEM;
  57. skb_frags[i].page = page_alloc->page;
  58. skb_frags[i].offset = page_alloc->offset;
  59. page_alloc->page = page;
  60. page_alloc->offset = frag_info->frag_align;
  61. } else {
  62. page = page_alloc->page;
  63. get_page(page);
  64. skb_frags[i].page = page;
  65. skb_frags[i].offset = page_alloc->offset;
  66. page_alloc->offset += frag_info->frag_stride;
  67. }
  68. dma = pci_map_single(mdev->pdev, page_address(skb_frags[i].page) +
  69. skb_frags[i].offset, frag_info->frag_size,
  70. PCI_DMA_FROMDEVICE);
  71. rx_desc->data[i].addr = cpu_to_be64(dma);
  72. return 0;
  73. }
  74. static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
  75. struct mlx4_en_rx_ring *ring)
  76. {
  77. struct mlx4_en_rx_alloc *page_alloc;
  78. int i;
  79. for (i = 0; i < priv->num_frags; i++) {
  80. page_alloc = &ring->page_alloc[i];
  81. page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
  82. MLX4_EN_ALLOC_ORDER);
  83. if (!page_alloc->page)
  84. goto out;
  85. page_alloc->offset = priv->frag_info[i].frag_align;
  86. en_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n",
  87. i, page_alloc->page);
  88. }
  89. return 0;
  90. out:
  91. while (i--) {
  92. page_alloc = &ring->page_alloc[i];
  93. put_page(page_alloc->page);
  94. page_alloc->page = NULL;
  95. }
  96. return -ENOMEM;
  97. }
  98. static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
  99. struct mlx4_en_rx_ring *ring)
  100. {
  101. struct mlx4_en_rx_alloc *page_alloc;
  102. int i;
  103. for (i = 0; i < priv->num_frags; i++) {
  104. page_alloc = &ring->page_alloc[i];
  105. en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
  106. i, page_count(page_alloc->page));
  107. put_page(page_alloc->page);
  108. page_alloc->page = NULL;
  109. }
  110. }
  111. static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
  112. struct mlx4_en_rx_ring *ring, int index)
  113. {
  114. struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
  115. struct skb_frag_struct *skb_frags = ring->rx_info +
  116. (index << priv->log_rx_info);
  117. int possible_frags;
  118. int i;
  119. /* Set size and memtype fields */
  120. for (i = 0; i < priv->num_frags; i++) {
  121. skb_frag_size_set(&skb_frags[i], priv->frag_info[i].frag_size);
  122. rx_desc->data[i].byte_count =
  123. cpu_to_be32(priv->frag_info[i].frag_size);
  124. rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
  125. }
  126. /* If the number of used fragments does not fill up the ring stride,
  127. * remaining (unused) fragments must be padded with null address/size
  128. * and a special memory key */
  129. possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
  130. for (i = priv->num_frags; i < possible_frags; i++) {
  131. rx_desc->data[i].byte_count = 0;
  132. rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
  133. rx_desc->data[i].addr = 0;
  134. }
  135. }
  136. static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
  137. struct mlx4_en_rx_ring *ring, int index)
  138. {
  139. struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
  140. struct page_frag *skb_frags = ring->rx_info +
  141. (index << priv->log_rx_info);
  142. int i;
  143. for (i = 0; i < priv->num_frags; i++)
  144. if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, ring->page_alloc, i))
  145. goto err;
  146. return 0;
  147. err:
  148. while (i--)
  149. put_page(skb_frags[i].page);
  150. return -ENOMEM;
  151. }
  152. static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
  153. {
  154. *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
  155. }
  156. static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
  157. struct mlx4_en_rx_ring *ring,
  158. int index)
  159. {
  160. struct mlx4_en_dev *mdev = priv->mdev;
  161. struct page_frag *skb_frags;
  162. struct mlx4_en_rx_desc *rx_desc = ring->buf + (index << ring->log_stride);
  163. dma_addr_t dma;
  164. int nr;
  165. skb_frags = ring->rx_info + (index << priv->log_rx_info);
  166. for (nr = 0; nr < priv->num_frags; nr++) {
  167. en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
  168. dma = be64_to_cpu(rx_desc->data[nr].addr);
  169. en_dbg(DRV, priv, "Unmapping buffer at dma:0x%llx\n", (u64) dma);
  170. pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size,
  171. PCI_DMA_FROMDEVICE);
  172. put_page(skb_frags[nr].page);
  173. }
  174. }
  175. static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
  176. {
  177. struct mlx4_en_rx_ring *ring;
  178. int ring_ind;
  179. int buf_ind;
  180. int new_size;
  181. for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
  182. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  183. ring = &priv->rx_ring[ring_ind];
  184. if (mlx4_en_prepare_rx_desc(priv, ring,
  185. ring->actual_size)) {
  186. if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
  187. en_err(priv, "Failed to allocate "
  188. "enough rx buffers\n");
  189. return -ENOMEM;
  190. } else {
  191. new_size = rounddown_pow_of_two(ring->actual_size);
  192. en_warn(priv, "Only %d buffers allocated "
  193. "reducing ring size to %d",
  194. ring->actual_size, new_size);
  195. goto reduce_rings;
  196. }
  197. }
  198. ring->actual_size++;
  199. ring->prod++;
  200. }
  201. }
  202. return 0;
  203. reduce_rings:
  204. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  205. ring = &priv->rx_ring[ring_ind];
  206. while (ring->actual_size > new_size) {
  207. ring->actual_size--;
  208. ring->prod--;
  209. mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
  210. }
  211. }
  212. return 0;
  213. }
  214. static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
  215. struct mlx4_en_rx_ring *ring)
  216. {
  217. int index;
  218. en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
  219. ring->cons, ring->prod);
  220. /* Unmap and free Rx buffers */
  221. BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
  222. while (ring->cons != ring->prod) {
  223. index = ring->cons & ring->size_mask;
  224. en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
  225. mlx4_en_free_rx_desc(priv, ring, index);
  226. ++ring->cons;
  227. }
  228. }
  229. int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
  230. struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
  231. {
  232. struct mlx4_en_dev *mdev = priv->mdev;
  233. int err;
  234. int tmp;
  235. ring->prod = 0;
  236. ring->cons = 0;
  237. ring->size = size;
  238. ring->size_mask = size - 1;
  239. ring->stride = stride;
  240. ring->log_stride = ffs(ring->stride) - 1;
  241. ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
  242. tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
  243. sizeof(struct skb_frag_struct));
  244. ring->rx_info = vmalloc(tmp);
  245. if (!ring->rx_info) {
  246. en_err(priv, "Failed allocating rx_info ring\n");
  247. return -ENOMEM;
  248. }
  249. en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
  250. ring->rx_info, tmp);
  251. err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
  252. ring->buf_size, 2 * PAGE_SIZE);
  253. if (err)
  254. goto err_ring;
  255. err = mlx4_en_map_buffer(&ring->wqres.buf);
  256. if (err) {
  257. en_err(priv, "Failed to map RX buffer\n");
  258. goto err_hwq;
  259. }
  260. ring->buf = ring->wqres.buf.direct.buf;
  261. return 0;
  262. err_hwq:
  263. mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
  264. err_ring:
  265. vfree(ring->rx_info);
  266. ring->rx_info = NULL;
  267. return err;
  268. }
  269. int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
  270. {
  271. struct mlx4_en_rx_ring *ring;
  272. int i;
  273. int ring_ind;
  274. int err;
  275. int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
  276. DS_SIZE * priv->num_frags);
  277. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  278. ring = &priv->rx_ring[ring_ind];
  279. ring->prod = 0;
  280. ring->cons = 0;
  281. ring->actual_size = 0;
  282. ring->cqn = priv->rx_cq[ring_ind].mcq.cqn;
  283. ring->stride = stride;
  284. if (ring->stride <= TXBB_SIZE)
  285. ring->buf += TXBB_SIZE;
  286. ring->log_stride = ffs(ring->stride) - 1;
  287. ring->buf_size = ring->size * ring->stride;
  288. memset(ring->buf, 0, ring->buf_size);
  289. mlx4_en_update_rx_prod_db(ring);
  290. /* Initailize all descriptors */
  291. for (i = 0; i < ring->size; i++)
  292. mlx4_en_init_rx_desc(priv, ring, i);
  293. /* Initialize page allocators */
  294. err = mlx4_en_init_allocator(priv, ring);
  295. if (err) {
  296. en_err(priv, "Failed initializing ring allocator\n");
  297. if (ring->stride <= TXBB_SIZE)
  298. ring->buf -= TXBB_SIZE;
  299. ring_ind--;
  300. goto err_allocator;
  301. }
  302. }
  303. err = mlx4_en_fill_rx_buffers(priv);
  304. if (err)
  305. goto err_buffers;
  306. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  307. ring = &priv->rx_ring[ring_ind];
  308. ring->size_mask = ring->actual_size - 1;
  309. mlx4_en_update_rx_prod_db(ring);
  310. }
  311. return 0;
  312. err_buffers:
  313. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
  314. mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]);
  315. ring_ind = priv->rx_ring_num - 1;
  316. err_allocator:
  317. while (ring_ind >= 0) {
  318. if (priv->rx_ring[ring_ind].stride <= TXBB_SIZE)
  319. priv->rx_ring[ring_ind].buf -= TXBB_SIZE;
  320. mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]);
  321. ring_ind--;
  322. }
  323. return err;
  324. }
  325. void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
  326. struct mlx4_en_rx_ring *ring)
  327. {
  328. struct mlx4_en_dev *mdev = priv->mdev;
  329. mlx4_en_unmap_buffer(&ring->wqres.buf);
  330. mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size + TXBB_SIZE);
  331. vfree(ring->rx_info);
  332. ring->rx_info = NULL;
  333. }
  334. void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
  335. struct mlx4_en_rx_ring *ring)
  336. {
  337. mlx4_en_free_rx_buf(priv, ring);
  338. if (ring->stride <= TXBB_SIZE)
  339. ring->buf -= TXBB_SIZE;
  340. mlx4_en_destroy_allocator(priv, ring);
  341. }
  342. /* Unmap a completed descriptor and free unused pages */
  343. static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
  344. struct mlx4_en_rx_desc *rx_desc,
  345. struct page_frag *skb_frags,
  346. struct sk_buff *skb,
  347. struct mlx4_en_rx_alloc *page_alloc,
  348. int length)
  349. {
  350. struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
  351. struct mlx4_en_dev *mdev = priv->mdev;
  352. struct mlx4_en_frag_info *frag_info;
  353. int nr;
  354. dma_addr_t dma;
  355. /* Collect used fragments while replacing them in the HW descirptors */
  356. for (nr = 0; nr < priv->num_frags; nr++) {
  357. frag_info = &priv->frag_info[nr];
  358. if (length <= frag_info->frag_prefix_size)
  359. break;
  360. /* Save page reference in skb */
  361. __skb_frag_set_page(&skb_frags_rx[nr], skb_frags[nr].page);
  362. skb_frag_size_set(&skb_frags_rx[nr], skb_frags[nr].size);
  363. skb_frags_rx[nr].page_offset = skb_frags[nr].offset;
  364. skb->truesize += frag_info->frag_stride;
  365. dma = be64_to_cpu(rx_desc->data[nr].addr);
  366. /* Allocate a replacement page */
  367. if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, page_alloc, nr))
  368. goto fail;
  369. /* Unmap buffer */
  370. pci_unmap_single(mdev->pdev, dma, skb_frag_size(&skb_frags_rx[nr]),
  371. PCI_DMA_FROMDEVICE);
  372. }
  373. /* Adjust size of last fragment to match actual length */
  374. if (nr > 0)
  375. skb_frag_size_set(&skb_frags_rx[nr - 1],
  376. length - priv->frag_info[nr - 1].frag_prefix_size);
  377. return nr;
  378. fail:
  379. /* Drop all accumulated fragments (which have already been replaced in
  380. * the descriptor) of this packet; remaining fragments are reused... */
  381. while (nr > 0) {
  382. nr--;
  383. __skb_frag_unref(&skb_frags_rx[nr]);
  384. }
  385. return 0;
  386. }
  387. static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
  388. struct mlx4_en_rx_desc *rx_desc,
  389. struct page_frag *skb_frags,
  390. struct mlx4_en_rx_alloc *page_alloc,
  391. unsigned int length)
  392. {
  393. struct mlx4_en_dev *mdev = priv->mdev;
  394. struct sk_buff *skb;
  395. void *va;
  396. int used_frags;
  397. dma_addr_t dma;
  398. skb = dev_alloc_skb(SMALL_PACKET_SIZE + NET_IP_ALIGN);
  399. if (!skb) {
  400. en_dbg(RX_ERR, priv, "Failed allocating skb\n");
  401. return NULL;
  402. }
  403. skb->dev = priv->dev;
  404. skb_reserve(skb, NET_IP_ALIGN);
  405. skb->len = length;
  406. /* Get pointer to first fragment so we could copy the headers into the
  407. * (linear part of the) skb */
  408. va = page_address(skb_frags[0].page) + skb_frags[0].offset;
  409. if (length <= SMALL_PACKET_SIZE) {
  410. /* We are copying all relevant data to the skb - temporarily
  411. * synch buffers for the copy */
  412. dma = be64_to_cpu(rx_desc->data[0].addr);
  413. dma_sync_single_for_cpu(&mdev->pdev->dev, dma, length,
  414. DMA_FROM_DEVICE);
  415. skb_copy_to_linear_data(skb, va, length);
  416. dma_sync_single_for_device(&mdev->pdev->dev, dma, length,
  417. DMA_FROM_DEVICE);
  418. skb->tail += length;
  419. } else {
  420. /* Move relevant fragments to skb */
  421. used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, skb_frags,
  422. skb, page_alloc, length);
  423. if (unlikely(!used_frags)) {
  424. kfree_skb(skb);
  425. return NULL;
  426. }
  427. skb_shinfo(skb)->nr_frags = used_frags;
  428. /* Copy headers into the skb linear buffer */
  429. memcpy(skb->data, va, HEADER_COPY_SIZE);
  430. skb->tail += HEADER_COPY_SIZE;
  431. /* Skip headers in first fragment */
  432. skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
  433. /* Adjust size of first fragment */
  434. skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE);
  435. skb->data_len = length - HEADER_COPY_SIZE;
  436. }
  437. return skb;
  438. }
  439. static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
  440. {
  441. int i;
  442. int offset = ETH_HLEN;
  443. for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
  444. if (*(skb->data + offset) != (unsigned char) (i & 0xff))
  445. goto out_loopback;
  446. }
  447. /* Loopback found */
  448. priv->loopback_ok = 1;
  449. out_loopback:
  450. dev_kfree_skb_any(skb);
  451. }
  452. int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
  453. {
  454. struct mlx4_en_priv *priv = netdev_priv(dev);
  455. struct mlx4_cqe *cqe;
  456. struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring];
  457. struct page_frag *skb_frags;
  458. struct mlx4_en_rx_desc *rx_desc;
  459. struct sk_buff *skb;
  460. int index;
  461. int nr;
  462. unsigned int length;
  463. int polled = 0;
  464. int ip_summed;
  465. struct ethhdr *ethh;
  466. u64 s_mac;
  467. if (!priv->port_up)
  468. return 0;
  469. /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
  470. * descriptor offset can be deduced from the CQE index instead of
  471. * reading 'cqe->index' */
  472. index = cq->mcq.cons_index & ring->size_mask;
  473. cqe = &cq->buf[index];
  474. /* Process all completed CQEs */
  475. while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
  476. cq->mcq.cons_index & cq->size)) {
  477. skb_frags = ring->rx_info + (index << priv->log_rx_info);
  478. rx_desc = ring->buf + (index << ring->log_stride);
  479. /*
  480. * make sure we read the CQE after we read the ownership bit
  481. */
  482. rmb();
  483. /* Drop packet on bad receive or bad checksum */
  484. if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
  485. MLX4_CQE_OPCODE_ERROR)) {
  486. en_err(priv, "CQE completed in error - vendor "
  487. "syndrom:%d syndrom:%d\n",
  488. ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome,
  489. ((struct mlx4_err_cqe *) cqe)->syndrome);
  490. goto next;
  491. }
  492. if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
  493. en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
  494. goto next;
  495. }
  496. /* Get pointer to first fragment since we haven't skb yet and
  497. * cast it to ethhdr struct */
  498. ethh = (struct ethhdr *)(page_address(skb_frags[0].page) +
  499. skb_frags[0].offset);
  500. s_mac = mlx4_en_mac_to_u64(ethh->h_source);
  501. /* If source MAC is equal to our own MAC and not performing
  502. * the selftest or flb disabled - drop the packet */
  503. if (s_mac == priv->mac &&
  504. (!(dev->features & NETIF_F_LOOPBACK) ||
  505. !priv->validate_loopback))
  506. goto next;
  507. /*
  508. * Packet is OK - process it.
  509. */
  510. length = be32_to_cpu(cqe->byte_cnt);
  511. length -= ring->fcs_del;
  512. ring->bytes += length;
  513. ring->packets++;
  514. if (likely(dev->features & NETIF_F_RXCSUM)) {
  515. if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
  516. (cqe->checksum == cpu_to_be16(0xffff))) {
  517. ring->csum_ok++;
  518. /* This packet is eligible for LRO if it is:
  519. * - DIX Ethernet (type interpretation)
  520. * - TCP/IP (v4)
  521. * - without IP options
  522. * - not an IP fragment */
  523. if (dev->features & NETIF_F_GRO) {
  524. struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
  525. if (!gro_skb)
  526. goto next;
  527. nr = mlx4_en_complete_rx_desc(
  528. priv, rx_desc,
  529. skb_frags, gro_skb,
  530. ring->page_alloc, length);
  531. if (!nr)
  532. goto next;
  533. skb_shinfo(gro_skb)->nr_frags = nr;
  534. gro_skb->len = length;
  535. gro_skb->data_len = length;
  536. gro_skb->ip_summed = CHECKSUM_UNNECESSARY;
  537. if (cqe->vlan_my_qpn &
  538. cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) {
  539. u16 vid = be16_to_cpu(cqe->sl_vid);
  540. __vlan_hwaccel_put_tag(gro_skb, vid);
  541. }
  542. if (dev->features & NETIF_F_RXHASH)
  543. gro_skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid);
  544. skb_record_rx_queue(gro_skb, cq->ring);
  545. napi_gro_frags(&cq->napi);
  546. goto next;
  547. }
  548. /* LRO not possible, complete processing here */
  549. ip_summed = CHECKSUM_UNNECESSARY;
  550. } else {
  551. ip_summed = CHECKSUM_NONE;
  552. ring->csum_none++;
  553. }
  554. } else {
  555. ip_summed = CHECKSUM_NONE;
  556. ring->csum_none++;
  557. }
  558. skb = mlx4_en_rx_skb(priv, rx_desc, skb_frags,
  559. ring->page_alloc, length);
  560. if (!skb) {
  561. priv->stats.rx_dropped++;
  562. goto next;
  563. }
  564. if (unlikely(priv->validate_loopback)) {
  565. validate_loopback(priv, skb);
  566. goto next;
  567. }
  568. skb->ip_summed = ip_summed;
  569. skb->protocol = eth_type_trans(skb, dev);
  570. skb_record_rx_queue(skb, cq->ring);
  571. if (dev->features & NETIF_F_RXHASH)
  572. skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid);
  573. if (be32_to_cpu(cqe->vlan_my_qpn) &
  574. MLX4_CQE_VLAN_PRESENT_MASK)
  575. __vlan_hwaccel_put_tag(skb, be16_to_cpu(cqe->sl_vid));
  576. /* Push it up the stack */
  577. netif_receive_skb(skb);
  578. next:
  579. ++cq->mcq.cons_index;
  580. index = (cq->mcq.cons_index) & ring->size_mask;
  581. cqe = &cq->buf[index];
  582. if (++polled == budget) {
  583. /* We are here because we reached the NAPI budget -
  584. * flush only pending LRO sessions */
  585. goto out;
  586. }
  587. }
  588. out:
  589. AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
  590. mlx4_cq_set_ci(&cq->mcq);
  591. wmb(); /* ensure HW sees CQ consumer before we post new buffers */
  592. ring->cons = cq->mcq.cons_index;
  593. ring->prod += polled; /* Polled descriptors were realocated in place */
  594. mlx4_en_update_rx_prod_db(ring);
  595. return polled;
  596. }
  597. void mlx4_en_rx_irq(struct mlx4_cq *mcq)
  598. {
  599. struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
  600. struct mlx4_en_priv *priv = netdev_priv(cq->dev);
  601. if (priv->port_up)
  602. napi_schedule(&cq->napi);
  603. else
  604. mlx4_en_arm_cq(priv, cq);
  605. }
  606. /* Rx CQ polling - called by NAPI */
  607. int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
  608. {
  609. struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
  610. struct net_device *dev = cq->dev;
  611. struct mlx4_en_priv *priv = netdev_priv(dev);
  612. int done;
  613. done = mlx4_en_process_rx_cq(dev, cq, budget);
  614. /* If we used up all the quota - we're probably not done yet... */
  615. if (done == budget)
  616. INC_PERF_COUNTER(priv->pstats.napi_quota);
  617. else {
  618. /* Done for now */
  619. napi_complete(napi);
  620. mlx4_en_arm_cq(priv, cq);
  621. }
  622. return done;
  623. }
  624. /* Calculate the last offset position that accommodates a full fragment
  625. * (assuming fagment size = stride-align) */
  626. static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align)
  627. {
  628. u16 res = MLX4_EN_ALLOC_SIZE % stride;
  629. u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align;
  630. en_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d "
  631. "res:%d offset:%d\n", stride, align, res, offset);
  632. return offset;
  633. }
  634. static int frag_sizes[] = {
  635. FRAG_SZ0,
  636. FRAG_SZ1,
  637. FRAG_SZ2,
  638. FRAG_SZ3
  639. };
  640. void mlx4_en_calc_rx_buf(struct net_device *dev)
  641. {
  642. struct mlx4_en_priv *priv = netdev_priv(dev);
  643. int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE;
  644. int buf_size = 0;
  645. int i = 0;
  646. while (buf_size < eff_mtu) {
  647. priv->frag_info[i].frag_size =
  648. (eff_mtu > buf_size + frag_sizes[i]) ?
  649. frag_sizes[i] : eff_mtu - buf_size;
  650. priv->frag_info[i].frag_prefix_size = buf_size;
  651. if (!i) {
  652. priv->frag_info[i].frag_align = NET_IP_ALIGN;
  653. priv->frag_info[i].frag_stride =
  654. ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
  655. } else {
  656. priv->frag_info[i].frag_align = 0;
  657. priv->frag_info[i].frag_stride =
  658. ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
  659. }
  660. priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset(
  661. priv, priv->frag_info[i].frag_stride,
  662. priv->frag_info[i].frag_align);
  663. buf_size += priv->frag_info[i].frag_size;
  664. i++;
  665. }
  666. priv->num_frags = i;
  667. priv->rx_skb_size = eff_mtu;
  668. priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct skb_frag_struct));
  669. en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
  670. "num_frags:%d):\n", eff_mtu, priv->num_frags);
  671. for (i = 0; i < priv->num_frags; i++) {
  672. en_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d "
  673. "stride:%d last_offset:%d\n", i,
  674. priv->frag_info[i].frag_size,
  675. priv->frag_info[i].frag_prefix_size,
  676. priv->frag_info[i].frag_align,
  677. priv->frag_info[i].frag_stride,
  678. priv->frag_info[i].last_offset);
  679. }
  680. }
  681. /* RSS related functions */
  682. static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
  683. struct mlx4_en_rx_ring *ring,
  684. enum mlx4_qp_state *state,
  685. struct mlx4_qp *qp)
  686. {
  687. struct mlx4_en_dev *mdev = priv->mdev;
  688. struct mlx4_qp_context *context;
  689. int err = 0;
  690. context = kmalloc(sizeof *context , GFP_KERNEL);
  691. if (!context) {
  692. en_err(priv, "Failed to allocate qp context\n");
  693. return -ENOMEM;
  694. }
  695. err = mlx4_qp_alloc(mdev->dev, qpn, qp);
  696. if (err) {
  697. en_err(priv, "Failed to allocate qp #%x\n", qpn);
  698. goto out;
  699. }
  700. qp->event = mlx4_en_sqp_event;
  701. memset(context, 0, sizeof *context);
  702. mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
  703. qpn, ring->cqn, context);
  704. context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
  705. /* Cancel FCS removal if FW allows */
  706. if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
  707. context->param3 |= cpu_to_be32(1 << 29);
  708. ring->fcs_del = ETH_FCS_LEN;
  709. } else
  710. ring->fcs_del = 0;
  711. err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
  712. if (err) {
  713. mlx4_qp_remove(mdev->dev, qp);
  714. mlx4_qp_free(mdev->dev, qp);
  715. }
  716. mlx4_en_update_rx_prod_db(ring);
  717. out:
  718. kfree(context);
  719. return err;
  720. }
  721. /* Allocate rx qp's and configure them according to rss map */
  722. int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
  723. {
  724. struct mlx4_en_dev *mdev = priv->mdev;
  725. struct mlx4_en_rss_map *rss_map = &priv->rss_map;
  726. struct mlx4_qp_context context;
  727. struct mlx4_rss_context *rss_context;
  728. int rss_rings;
  729. void *ptr;
  730. u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
  731. MLX4_RSS_TCP_IPV6);
  732. int i, qpn;
  733. int err = 0;
  734. int good_qps = 0;
  735. static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC,
  736. 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD,
  737. 0x593D56D9, 0xF3253C06, 0x2ADC1FFC};
  738. en_dbg(DRV, priv, "Configuring rss steering\n");
  739. err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
  740. priv->rx_ring_num,
  741. &rss_map->base_qpn);
  742. if (err) {
  743. en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
  744. return err;
  745. }
  746. for (i = 0; i < priv->rx_ring_num; i++) {
  747. qpn = rss_map->base_qpn + i;
  748. err = mlx4_en_config_rss_qp(priv, qpn, &priv->rx_ring[i],
  749. &rss_map->state[i],
  750. &rss_map->qps[i]);
  751. if (err)
  752. goto rss_err;
  753. ++good_qps;
  754. }
  755. /* Configure RSS indirection qp */
  756. err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
  757. if (err) {
  758. en_err(priv, "Failed to allocate RSS indirection QP\n");
  759. goto rss_err;
  760. }
  761. rss_map->indir_qp.event = mlx4_en_sqp_event;
  762. mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
  763. priv->rx_ring[0].cqn, &context);
  764. if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
  765. rss_rings = priv->rx_ring_num;
  766. else
  767. rss_rings = priv->prof->rss_rings;
  768. ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
  769. + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
  770. rss_context = ptr;
  771. rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
  772. (rss_map->base_qpn));
  773. rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
  774. if (priv->mdev->profile.udp_rss) {
  775. rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
  776. rss_context->base_qpn_udp = rss_context->default_qpn;
  777. }
  778. rss_context->flags = rss_mask;
  779. rss_context->hash_fn = MLX4_RSS_HASH_TOP;
  780. for (i = 0; i < 10; i++)
  781. rss_context->rss_key[i] = rsskey[i];
  782. err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
  783. &rss_map->indir_qp, &rss_map->indir_state);
  784. if (err)
  785. goto indir_err;
  786. return 0;
  787. indir_err:
  788. mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
  789. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
  790. mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
  791. mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
  792. rss_err:
  793. for (i = 0; i < good_qps; i++) {
  794. mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
  795. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
  796. mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
  797. mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
  798. }
  799. mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
  800. return err;
  801. }
  802. void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
  803. {
  804. struct mlx4_en_dev *mdev = priv->mdev;
  805. struct mlx4_en_rss_map *rss_map = &priv->rss_map;
  806. int i;
  807. mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
  808. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
  809. mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
  810. mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
  811. for (i = 0; i < priv->rx_ring_num; i++) {
  812. mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
  813. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
  814. mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
  815. mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
  816. }
  817. mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
  818. }