bnx2x_stats.c 53 KB

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  1. /* bnx2x_stats.c: Broadcom Everest network driver.
  2. *
  3. * Copyright (c) 2007-2011 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10. * Written by: Eliezer Tamir
  11. * Based on code from Michael Chan's bnx2 driver
  12. * UDP CSUM errata workaround by Arik Gendelman
  13. * Slowpath and fastpath rework by Vladislav Zolotarov
  14. * Statistics and Link management by Yitchak Gertner
  15. *
  16. */
  17. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18. #include "bnx2x_stats.h"
  19. #include "bnx2x_cmn.h"
  20. /* Statistics */
  21. /*
  22. * General service functions
  23. */
  24. static inline long bnx2x_hilo(u32 *hiref)
  25. {
  26. u32 lo = *(hiref + 1);
  27. #if (BITS_PER_LONG == 64)
  28. u32 hi = *hiref;
  29. return HILO_U64(hi, lo);
  30. #else
  31. return lo;
  32. #endif
  33. }
  34. static u16 bnx2x_get_port_stats_dma_len(struct bnx2x *bp)
  35. {
  36. u16 res = sizeof(struct host_port_stats) >> 2;
  37. /* if PFC stats are not supported by the MFW, don't DMA them */
  38. if (!(bp->flags & BC_SUPPORTS_PFC_STATS))
  39. res -= (sizeof(u32)*4) >> 2;
  40. return res;
  41. }
  42. /*
  43. * Init service functions
  44. */
  45. /* Post the next statistics ramrod. Protect it with the spin in
  46. * order to ensure the strict order between statistics ramrods
  47. * (each ramrod has a sequence number passed in a
  48. * bp->fw_stats_req->hdr.drv_stats_counter and ramrods must be
  49. * sent in order).
  50. */
  51. static void bnx2x_storm_stats_post(struct bnx2x *bp)
  52. {
  53. if (!bp->stats_pending) {
  54. int rc;
  55. spin_lock_bh(&bp->stats_lock);
  56. if (bp->stats_pending) {
  57. spin_unlock_bh(&bp->stats_lock);
  58. return;
  59. }
  60. bp->fw_stats_req->hdr.drv_stats_counter =
  61. cpu_to_le16(bp->stats_counter++);
  62. DP(NETIF_MSG_TIMER, "Sending statistics ramrod %d\n",
  63. bp->fw_stats_req->hdr.drv_stats_counter);
  64. /* send FW stats ramrod */
  65. rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STAT_QUERY, 0,
  66. U64_HI(bp->fw_stats_req_mapping),
  67. U64_LO(bp->fw_stats_req_mapping),
  68. NONE_CONNECTION_TYPE);
  69. if (rc == 0)
  70. bp->stats_pending = 1;
  71. spin_unlock_bh(&bp->stats_lock);
  72. }
  73. }
  74. static void bnx2x_hw_stats_post(struct bnx2x *bp)
  75. {
  76. struct dmae_command *dmae = &bp->stats_dmae;
  77. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  78. *stats_comp = DMAE_COMP_VAL;
  79. if (CHIP_REV_IS_SLOW(bp))
  80. return;
  81. /* loader */
  82. if (bp->executer_idx) {
  83. int loader_idx = PMF_DMAE_C(bp);
  84. u32 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  85. true, DMAE_COMP_GRC);
  86. opcode = bnx2x_dmae_opcode_clr_src_reset(opcode);
  87. memset(dmae, 0, sizeof(struct dmae_command));
  88. dmae->opcode = opcode;
  89. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
  90. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
  91. dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
  92. sizeof(struct dmae_command) *
  93. (loader_idx + 1)) >> 2;
  94. dmae->dst_addr_hi = 0;
  95. dmae->len = sizeof(struct dmae_command) >> 2;
  96. if (CHIP_IS_E1(bp))
  97. dmae->len--;
  98. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
  99. dmae->comp_addr_hi = 0;
  100. dmae->comp_val = 1;
  101. *stats_comp = 0;
  102. bnx2x_post_dmae(bp, dmae, loader_idx);
  103. } else if (bp->func_stx) {
  104. *stats_comp = 0;
  105. bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
  106. }
  107. }
  108. static int bnx2x_stats_comp(struct bnx2x *bp)
  109. {
  110. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  111. int cnt = 10;
  112. might_sleep();
  113. while (*stats_comp != DMAE_COMP_VAL) {
  114. if (!cnt) {
  115. BNX2X_ERR("timeout waiting for stats finished\n");
  116. break;
  117. }
  118. cnt--;
  119. usleep_range(1000, 1000);
  120. }
  121. return 1;
  122. }
  123. /*
  124. * Statistics service functions
  125. */
  126. static void bnx2x_stats_pmf_update(struct bnx2x *bp)
  127. {
  128. struct dmae_command *dmae;
  129. u32 opcode;
  130. int loader_idx = PMF_DMAE_C(bp);
  131. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  132. /* sanity */
  133. if (!IS_MF(bp) || !bp->port.pmf || !bp->port.port_stx) {
  134. BNX2X_ERR("BUG!\n");
  135. return;
  136. }
  137. bp->executer_idx = 0;
  138. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI, false, 0);
  139. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  140. dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC);
  141. dmae->src_addr_lo = bp->port.port_stx >> 2;
  142. dmae->src_addr_hi = 0;
  143. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  144. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  145. dmae->len = DMAE_LEN32_RD_MAX;
  146. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  147. dmae->comp_addr_hi = 0;
  148. dmae->comp_val = 1;
  149. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  150. dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
  151. dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
  152. dmae->src_addr_hi = 0;
  153. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
  154. DMAE_LEN32_RD_MAX * 4);
  155. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
  156. DMAE_LEN32_RD_MAX * 4);
  157. dmae->len = bnx2x_get_port_stats_dma_len(bp) - DMAE_LEN32_RD_MAX;
  158. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  159. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  160. dmae->comp_val = DMAE_COMP_VAL;
  161. *stats_comp = 0;
  162. bnx2x_hw_stats_post(bp);
  163. bnx2x_stats_comp(bp);
  164. }
  165. static void bnx2x_port_stats_init(struct bnx2x *bp)
  166. {
  167. struct dmae_command *dmae;
  168. int port = BP_PORT(bp);
  169. u32 opcode;
  170. int loader_idx = PMF_DMAE_C(bp);
  171. u32 mac_addr;
  172. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  173. /* sanity */
  174. if (!bp->link_vars.link_up || !bp->port.pmf) {
  175. BNX2X_ERR("BUG!\n");
  176. return;
  177. }
  178. bp->executer_idx = 0;
  179. /* MCP */
  180. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  181. true, DMAE_COMP_GRC);
  182. if (bp->port.port_stx) {
  183. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  184. dmae->opcode = opcode;
  185. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  186. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  187. dmae->dst_addr_lo = bp->port.port_stx >> 2;
  188. dmae->dst_addr_hi = 0;
  189. dmae->len = bnx2x_get_port_stats_dma_len(bp);
  190. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  191. dmae->comp_addr_hi = 0;
  192. dmae->comp_val = 1;
  193. }
  194. if (bp->func_stx) {
  195. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  196. dmae->opcode = opcode;
  197. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
  198. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
  199. dmae->dst_addr_lo = bp->func_stx >> 2;
  200. dmae->dst_addr_hi = 0;
  201. dmae->len = sizeof(struct host_func_stats) >> 2;
  202. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  203. dmae->comp_addr_hi = 0;
  204. dmae->comp_val = 1;
  205. }
  206. /* MAC */
  207. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
  208. true, DMAE_COMP_GRC);
  209. /* EMAC is special */
  210. if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
  211. mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
  212. /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
  213. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  214. dmae->opcode = opcode;
  215. dmae->src_addr_lo = (mac_addr +
  216. EMAC_REG_EMAC_RX_STAT_AC) >> 2;
  217. dmae->src_addr_hi = 0;
  218. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
  219. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
  220. dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
  221. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  222. dmae->comp_addr_hi = 0;
  223. dmae->comp_val = 1;
  224. /* EMAC_REG_EMAC_RX_STAT_AC_28 */
  225. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  226. dmae->opcode = opcode;
  227. dmae->src_addr_lo = (mac_addr +
  228. EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
  229. dmae->src_addr_hi = 0;
  230. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
  231. offsetof(struct emac_stats, rx_stat_falsecarriererrors));
  232. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
  233. offsetof(struct emac_stats, rx_stat_falsecarriererrors));
  234. dmae->len = 1;
  235. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  236. dmae->comp_addr_hi = 0;
  237. dmae->comp_val = 1;
  238. /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
  239. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  240. dmae->opcode = opcode;
  241. dmae->src_addr_lo = (mac_addr +
  242. EMAC_REG_EMAC_TX_STAT_AC) >> 2;
  243. dmae->src_addr_hi = 0;
  244. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
  245. offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
  246. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
  247. offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
  248. dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
  249. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  250. dmae->comp_addr_hi = 0;
  251. dmae->comp_val = 1;
  252. } else {
  253. u32 tx_src_addr_lo, rx_src_addr_lo;
  254. u16 rx_len, tx_len;
  255. /* configure the params according to MAC type */
  256. switch (bp->link_vars.mac_type) {
  257. case MAC_TYPE_BMAC:
  258. mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
  259. NIG_REG_INGRESS_BMAC0_MEM);
  260. /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
  261. BIGMAC_REGISTER_TX_STAT_GTBYT */
  262. if (CHIP_IS_E1x(bp)) {
  263. tx_src_addr_lo = (mac_addr +
  264. BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
  265. tx_len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
  266. BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
  267. rx_src_addr_lo = (mac_addr +
  268. BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
  269. rx_len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
  270. BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
  271. } else {
  272. tx_src_addr_lo = (mac_addr +
  273. BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
  274. tx_len = (8 + BIGMAC2_REGISTER_TX_STAT_GTBYT -
  275. BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
  276. rx_src_addr_lo = (mac_addr +
  277. BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
  278. rx_len = (8 + BIGMAC2_REGISTER_RX_STAT_GRIPJ -
  279. BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
  280. }
  281. break;
  282. case MAC_TYPE_UMAC: /* handled by MSTAT */
  283. case MAC_TYPE_XMAC: /* handled by MSTAT */
  284. default:
  285. mac_addr = port ? GRCBASE_MSTAT1 : GRCBASE_MSTAT0;
  286. tx_src_addr_lo = (mac_addr +
  287. MSTAT_REG_TX_STAT_GTXPOK_LO) >> 2;
  288. rx_src_addr_lo = (mac_addr +
  289. MSTAT_REG_RX_STAT_GR64_LO) >> 2;
  290. tx_len = sizeof(bp->slowpath->
  291. mac_stats.mstat_stats.stats_tx) >> 2;
  292. rx_len = sizeof(bp->slowpath->
  293. mac_stats.mstat_stats.stats_rx) >> 2;
  294. break;
  295. }
  296. /* TX stats */
  297. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  298. dmae->opcode = opcode;
  299. dmae->src_addr_lo = tx_src_addr_lo;
  300. dmae->src_addr_hi = 0;
  301. dmae->len = tx_len;
  302. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
  303. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
  304. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  305. dmae->comp_addr_hi = 0;
  306. dmae->comp_val = 1;
  307. /* RX stats */
  308. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  309. dmae->opcode = opcode;
  310. dmae->src_addr_hi = 0;
  311. dmae->src_addr_lo = rx_src_addr_lo;
  312. dmae->dst_addr_lo =
  313. U64_LO(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
  314. dmae->dst_addr_hi =
  315. U64_HI(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
  316. dmae->len = rx_len;
  317. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  318. dmae->comp_addr_hi = 0;
  319. dmae->comp_val = 1;
  320. }
  321. /* NIG */
  322. if (!CHIP_IS_E3(bp)) {
  323. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  324. dmae->opcode = opcode;
  325. dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
  326. NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
  327. dmae->src_addr_hi = 0;
  328. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
  329. offsetof(struct nig_stats, egress_mac_pkt0_lo));
  330. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
  331. offsetof(struct nig_stats, egress_mac_pkt0_lo));
  332. dmae->len = (2*sizeof(u32)) >> 2;
  333. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  334. dmae->comp_addr_hi = 0;
  335. dmae->comp_val = 1;
  336. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  337. dmae->opcode = opcode;
  338. dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
  339. NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
  340. dmae->src_addr_hi = 0;
  341. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
  342. offsetof(struct nig_stats, egress_mac_pkt1_lo));
  343. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
  344. offsetof(struct nig_stats, egress_mac_pkt1_lo));
  345. dmae->len = (2*sizeof(u32)) >> 2;
  346. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  347. dmae->comp_addr_hi = 0;
  348. dmae->comp_val = 1;
  349. }
  350. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  351. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
  352. true, DMAE_COMP_PCI);
  353. dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
  354. NIG_REG_STAT0_BRB_DISCARD) >> 2;
  355. dmae->src_addr_hi = 0;
  356. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
  357. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
  358. dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
  359. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  360. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  361. dmae->comp_val = DMAE_COMP_VAL;
  362. *stats_comp = 0;
  363. }
  364. static void bnx2x_func_stats_init(struct bnx2x *bp)
  365. {
  366. struct dmae_command *dmae = &bp->stats_dmae;
  367. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  368. /* sanity */
  369. if (!bp->func_stx) {
  370. BNX2X_ERR("BUG!\n");
  371. return;
  372. }
  373. bp->executer_idx = 0;
  374. memset(dmae, 0, sizeof(struct dmae_command));
  375. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  376. true, DMAE_COMP_PCI);
  377. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
  378. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
  379. dmae->dst_addr_lo = bp->func_stx >> 2;
  380. dmae->dst_addr_hi = 0;
  381. dmae->len = sizeof(struct host_func_stats) >> 2;
  382. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  383. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  384. dmae->comp_val = DMAE_COMP_VAL;
  385. *stats_comp = 0;
  386. }
  387. static void bnx2x_stats_start(struct bnx2x *bp)
  388. {
  389. if (bp->port.pmf)
  390. bnx2x_port_stats_init(bp);
  391. else if (bp->func_stx)
  392. bnx2x_func_stats_init(bp);
  393. bnx2x_hw_stats_post(bp);
  394. bnx2x_storm_stats_post(bp);
  395. }
  396. static void bnx2x_stats_pmf_start(struct bnx2x *bp)
  397. {
  398. bnx2x_stats_comp(bp);
  399. bnx2x_stats_pmf_update(bp);
  400. bnx2x_stats_start(bp);
  401. }
  402. static void bnx2x_stats_restart(struct bnx2x *bp)
  403. {
  404. bnx2x_stats_comp(bp);
  405. bnx2x_stats_start(bp);
  406. }
  407. static void bnx2x_bmac_stats_update(struct bnx2x *bp)
  408. {
  409. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  410. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  411. struct {
  412. u32 lo;
  413. u32 hi;
  414. } diff;
  415. if (CHIP_IS_E1x(bp)) {
  416. struct bmac1_stats *new = bnx2x_sp(bp, mac_stats.bmac1_stats);
  417. /* the macros below will use "bmac1_stats" type */
  418. UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
  419. UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
  420. UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
  421. UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
  422. UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
  423. UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
  424. UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
  425. UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
  426. UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
  427. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
  428. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
  429. UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
  430. UPDATE_STAT64(tx_stat_gt127,
  431. tx_stat_etherstatspkts65octetsto127octets);
  432. UPDATE_STAT64(tx_stat_gt255,
  433. tx_stat_etherstatspkts128octetsto255octets);
  434. UPDATE_STAT64(tx_stat_gt511,
  435. tx_stat_etherstatspkts256octetsto511octets);
  436. UPDATE_STAT64(tx_stat_gt1023,
  437. tx_stat_etherstatspkts512octetsto1023octets);
  438. UPDATE_STAT64(tx_stat_gt1518,
  439. tx_stat_etherstatspkts1024octetsto1522octets);
  440. UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
  441. UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
  442. UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
  443. UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
  444. UPDATE_STAT64(tx_stat_gterr,
  445. tx_stat_dot3statsinternalmactransmiterrors);
  446. UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
  447. } else {
  448. struct bmac2_stats *new = bnx2x_sp(bp, mac_stats.bmac2_stats);
  449. /* the macros below will use "bmac2_stats" type */
  450. UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
  451. UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
  452. UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
  453. UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
  454. UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
  455. UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
  456. UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
  457. UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
  458. UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
  459. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
  460. UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
  461. UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
  462. UPDATE_STAT64(tx_stat_gt127,
  463. tx_stat_etherstatspkts65octetsto127octets);
  464. UPDATE_STAT64(tx_stat_gt255,
  465. tx_stat_etherstatspkts128octetsto255octets);
  466. UPDATE_STAT64(tx_stat_gt511,
  467. tx_stat_etherstatspkts256octetsto511octets);
  468. UPDATE_STAT64(tx_stat_gt1023,
  469. tx_stat_etherstatspkts512octetsto1023octets);
  470. UPDATE_STAT64(tx_stat_gt1518,
  471. tx_stat_etherstatspkts1024octetsto1522octets);
  472. UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
  473. UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
  474. UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
  475. UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
  476. UPDATE_STAT64(tx_stat_gterr,
  477. tx_stat_dot3statsinternalmactransmiterrors);
  478. UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
  479. /* collect PFC stats */
  480. DIFF_64(diff.hi, new->tx_stat_gtpp_hi,
  481. pstats->pfc_frames_tx_hi,
  482. diff.lo, new->tx_stat_gtpp_lo,
  483. pstats->pfc_frames_tx_lo);
  484. pstats->pfc_frames_tx_hi = new->tx_stat_gtpp_hi;
  485. pstats->pfc_frames_tx_lo = new->tx_stat_gtpp_lo;
  486. ADD_64(pstats->pfc_frames_tx_hi, diff.hi,
  487. pstats->pfc_frames_tx_lo, diff.lo);
  488. DIFF_64(diff.hi, new->rx_stat_grpp_hi,
  489. pstats->pfc_frames_rx_hi,
  490. diff.lo, new->rx_stat_grpp_lo,
  491. pstats->pfc_frames_rx_lo);
  492. pstats->pfc_frames_rx_hi = new->rx_stat_grpp_hi;
  493. pstats->pfc_frames_rx_lo = new->rx_stat_grpp_lo;
  494. ADD_64(pstats->pfc_frames_rx_hi, diff.hi,
  495. pstats->pfc_frames_rx_lo, diff.lo);
  496. }
  497. estats->pause_frames_received_hi =
  498. pstats->mac_stx[1].rx_stat_mac_xpf_hi;
  499. estats->pause_frames_received_lo =
  500. pstats->mac_stx[1].rx_stat_mac_xpf_lo;
  501. estats->pause_frames_sent_hi =
  502. pstats->mac_stx[1].tx_stat_outxoffsent_hi;
  503. estats->pause_frames_sent_lo =
  504. pstats->mac_stx[1].tx_stat_outxoffsent_lo;
  505. estats->pfc_frames_received_hi =
  506. pstats->pfc_frames_rx_hi;
  507. estats->pfc_frames_received_lo =
  508. pstats->pfc_frames_rx_lo;
  509. estats->pfc_frames_sent_hi =
  510. pstats->pfc_frames_tx_hi;
  511. estats->pfc_frames_sent_lo =
  512. pstats->pfc_frames_tx_lo;
  513. }
  514. static void bnx2x_mstat_stats_update(struct bnx2x *bp)
  515. {
  516. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  517. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  518. struct mstat_stats *new = bnx2x_sp(bp, mac_stats.mstat_stats);
  519. ADD_STAT64(stats_rx.rx_grerb, rx_stat_ifhcinbadoctets);
  520. ADD_STAT64(stats_rx.rx_grfcs, rx_stat_dot3statsfcserrors);
  521. ADD_STAT64(stats_rx.rx_grund, rx_stat_etherstatsundersizepkts);
  522. ADD_STAT64(stats_rx.rx_grovr, rx_stat_dot3statsframestoolong);
  523. ADD_STAT64(stats_rx.rx_grfrg, rx_stat_etherstatsfragments);
  524. ADD_STAT64(stats_rx.rx_grxcf, rx_stat_maccontrolframesreceived);
  525. ADD_STAT64(stats_rx.rx_grxpf, rx_stat_xoffstateentered);
  526. ADD_STAT64(stats_rx.rx_grxpf, rx_stat_mac_xpf);
  527. ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_outxoffsent);
  528. ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_flowcontroldone);
  529. /* collect pfc stats */
  530. ADD_64(pstats->pfc_frames_tx_hi, new->stats_tx.tx_gtxpp_hi,
  531. pstats->pfc_frames_tx_lo, new->stats_tx.tx_gtxpp_lo);
  532. ADD_64(pstats->pfc_frames_rx_hi, new->stats_rx.rx_grxpp_hi,
  533. pstats->pfc_frames_rx_lo, new->stats_rx.rx_grxpp_lo);
  534. ADD_STAT64(stats_tx.tx_gt64, tx_stat_etherstatspkts64octets);
  535. ADD_STAT64(stats_tx.tx_gt127,
  536. tx_stat_etherstatspkts65octetsto127octets);
  537. ADD_STAT64(stats_tx.tx_gt255,
  538. tx_stat_etherstatspkts128octetsto255octets);
  539. ADD_STAT64(stats_tx.tx_gt511,
  540. tx_stat_etherstatspkts256octetsto511octets);
  541. ADD_STAT64(stats_tx.tx_gt1023,
  542. tx_stat_etherstatspkts512octetsto1023octets);
  543. ADD_STAT64(stats_tx.tx_gt1518,
  544. tx_stat_etherstatspkts1024octetsto1522octets);
  545. ADD_STAT64(stats_tx.tx_gt2047, tx_stat_mac_2047);
  546. ADD_STAT64(stats_tx.tx_gt4095, tx_stat_mac_4095);
  547. ADD_STAT64(stats_tx.tx_gt9216, tx_stat_mac_9216);
  548. ADD_STAT64(stats_tx.tx_gt16383, tx_stat_mac_16383);
  549. ADD_STAT64(stats_tx.tx_gterr,
  550. tx_stat_dot3statsinternalmactransmiterrors);
  551. ADD_STAT64(stats_tx.tx_gtufl, tx_stat_mac_ufl);
  552. ADD_64(estats->etherstatspkts1024octetsto1522octets_hi,
  553. new->stats_tx.tx_gt1518_hi,
  554. estats->etherstatspkts1024octetsto1522octets_lo,
  555. new->stats_tx.tx_gt1518_lo);
  556. ADD_64(estats->etherstatspktsover1522octets_hi,
  557. new->stats_tx.tx_gt2047_hi,
  558. estats->etherstatspktsover1522octets_lo,
  559. new->stats_tx.tx_gt2047_lo);
  560. ADD_64(estats->etherstatspktsover1522octets_hi,
  561. new->stats_tx.tx_gt4095_hi,
  562. estats->etherstatspktsover1522octets_lo,
  563. new->stats_tx.tx_gt4095_lo);
  564. ADD_64(estats->etherstatspktsover1522octets_hi,
  565. new->stats_tx.tx_gt9216_hi,
  566. estats->etherstatspktsover1522octets_lo,
  567. new->stats_tx.tx_gt9216_lo);
  568. ADD_64(estats->etherstatspktsover1522octets_hi,
  569. new->stats_tx.tx_gt16383_hi,
  570. estats->etherstatspktsover1522octets_lo,
  571. new->stats_tx.tx_gt16383_lo);
  572. estats->pause_frames_received_hi =
  573. pstats->mac_stx[1].rx_stat_mac_xpf_hi;
  574. estats->pause_frames_received_lo =
  575. pstats->mac_stx[1].rx_stat_mac_xpf_lo;
  576. estats->pause_frames_sent_hi =
  577. pstats->mac_stx[1].tx_stat_outxoffsent_hi;
  578. estats->pause_frames_sent_lo =
  579. pstats->mac_stx[1].tx_stat_outxoffsent_lo;
  580. estats->pfc_frames_received_hi =
  581. pstats->pfc_frames_rx_hi;
  582. estats->pfc_frames_received_lo =
  583. pstats->pfc_frames_rx_lo;
  584. estats->pfc_frames_sent_hi =
  585. pstats->pfc_frames_tx_hi;
  586. estats->pfc_frames_sent_lo =
  587. pstats->pfc_frames_tx_lo;
  588. }
  589. static void bnx2x_emac_stats_update(struct bnx2x *bp)
  590. {
  591. struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
  592. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  593. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  594. UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
  595. UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
  596. UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
  597. UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
  598. UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
  599. UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
  600. UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
  601. UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
  602. UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
  603. UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
  604. UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
  605. UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
  606. UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
  607. UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
  608. UPDATE_EXTEND_STAT(tx_stat_outxonsent);
  609. UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
  610. UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
  611. UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
  612. UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
  613. UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
  614. UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
  615. UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
  616. UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
  617. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
  618. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
  619. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
  620. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
  621. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
  622. UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
  623. UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
  624. UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
  625. estats->pause_frames_received_hi =
  626. pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
  627. estats->pause_frames_received_lo =
  628. pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
  629. ADD_64(estats->pause_frames_received_hi,
  630. pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
  631. estats->pause_frames_received_lo,
  632. pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
  633. estats->pause_frames_sent_hi =
  634. pstats->mac_stx[1].tx_stat_outxonsent_hi;
  635. estats->pause_frames_sent_lo =
  636. pstats->mac_stx[1].tx_stat_outxonsent_lo;
  637. ADD_64(estats->pause_frames_sent_hi,
  638. pstats->mac_stx[1].tx_stat_outxoffsent_hi,
  639. estats->pause_frames_sent_lo,
  640. pstats->mac_stx[1].tx_stat_outxoffsent_lo);
  641. }
  642. static int bnx2x_hw_stats_update(struct bnx2x *bp)
  643. {
  644. struct nig_stats *new = bnx2x_sp(bp, nig_stats);
  645. struct nig_stats *old = &(bp->port.old_nig_stats);
  646. struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
  647. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  648. struct {
  649. u32 lo;
  650. u32 hi;
  651. } diff;
  652. switch (bp->link_vars.mac_type) {
  653. case MAC_TYPE_BMAC:
  654. bnx2x_bmac_stats_update(bp);
  655. break;
  656. case MAC_TYPE_EMAC:
  657. bnx2x_emac_stats_update(bp);
  658. break;
  659. case MAC_TYPE_UMAC:
  660. case MAC_TYPE_XMAC:
  661. bnx2x_mstat_stats_update(bp);
  662. break;
  663. case MAC_TYPE_NONE: /* unreached */
  664. DP(BNX2X_MSG_STATS,
  665. "stats updated by DMAE but no MAC active\n");
  666. return -1;
  667. default: /* unreached */
  668. BNX2X_ERR("Unknown MAC type\n");
  669. }
  670. ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
  671. new->brb_discard - old->brb_discard);
  672. ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
  673. new->brb_truncate - old->brb_truncate);
  674. if (!CHIP_IS_E3(bp)) {
  675. UPDATE_STAT64_NIG(egress_mac_pkt0,
  676. etherstatspkts1024octetsto1522octets);
  677. UPDATE_STAT64_NIG(egress_mac_pkt1,
  678. etherstatspktsover1522octets);
  679. }
  680. memcpy(old, new, sizeof(struct nig_stats));
  681. memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
  682. sizeof(struct mac_stx));
  683. estats->brb_drop_hi = pstats->brb_drop_hi;
  684. estats->brb_drop_lo = pstats->brb_drop_lo;
  685. pstats->host_port_stats_counter++;
  686. if (!BP_NOMCP(bp)) {
  687. u32 nig_timer_max =
  688. SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
  689. if (nig_timer_max != estats->nig_timer_max) {
  690. estats->nig_timer_max = nig_timer_max;
  691. BNX2X_ERR("NIG timer max (%u)\n",
  692. estats->nig_timer_max);
  693. }
  694. }
  695. return 0;
  696. }
  697. static int bnx2x_storm_stats_update(struct bnx2x *bp)
  698. {
  699. struct tstorm_per_port_stats *tport =
  700. &bp->fw_stats_data->port.tstorm_port_statistics;
  701. struct tstorm_per_pf_stats *tfunc =
  702. &bp->fw_stats_data->pf.tstorm_pf_statistics;
  703. struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
  704. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  705. struct stats_counter *counters = &bp->fw_stats_data->storm_counters;
  706. int i;
  707. u16 cur_stats_counter;
  708. /* Make sure we use the value of the counter
  709. * used for sending the last stats ramrod.
  710. */
  711. spin_lock_bh(&bp->stats_lock);
  712. cur_stats_counter = bp->stats_counter - 1;
  713. spin_unlock_bh(&bp->stats_lock);
  714. /* are storm stats valid? */
  715. if (le16_to_cpu(counters->xstats_counter) != cur_stats_counter) {
  716. DP(BNX2X_MSG_STATS, "stats not updated by xstorm"
  717. " xstorm counter (0x%x) != stats_counter (0x%x)\n",
  718. le16_to_cpu(counters->xstats_counter), bp->stats_counter);
  719. return -EAGAIN;
  720. }
  721. if (le16_to_cpu(counters->ustats_counter) != cur_stats_counter) {
  722. DP(BNX2X_MSG_STATS, "stats not updated by ustorm"
  723. " ustorm counter (0x%x) != stats_counter (0x%x)\n",
  724. le16_to_cpu(counters->ustats_counter), bp->stats_counter);
  725. return -EAGAIN;
  726. }
  727. if (le16_to_cpu(counters->cstats_counter) != cur_stats_counter) {
  728. DP(BNX2X_MSG_STATS, "stats not updated by cstorm"
  729. " cstorm counter (0x%x) != stats_counter (0x%x)\n",
  730. le16_to_cpu(counters->cstats_counter), bp->stats_counter);
  731. return -EAGAIN;
  732. }
  733. if (le16_to_cpu(counters->tstats_counter) != cur_stats_counter) {
  734. DP(BNX2X_MSG_STATS, "stats not updated by tstorm"
  735. " tstorm counter (0x%x) != stats_counter (0x%x)\n",
  736. le16_to_cpu(counters->tstats_counter), bp->stats_counter);
  737. return -EAGAIN;
  738. }
  739. memcpy(&(fstats->total_bytes_received_hi),
  740. &(bnx2x_sp(bp, func_stats_base)->total_bytes_received_hi),
  741. sizeof(struct host_func_stats) - 2*sizeof(u32));
  742. estats->error_bytes_received_hi = 0;
  743. estats->error_bytes_received_lo = 0;
  744. estats->etherstatsoverrsizepkts_hi = 0;
  745. estats->etherstatsoverrsizepkts_lo = 0;
  746. estats->no_buff_discard_hi = 0;
  747. estats->no_buff_discard_lo = 0;
  748. estats->total_tpa_aggregations_hi = 0;
  749. estats->total_tpa_aggregations_lo = 0;
  750. estats->total_tpa_aggregated_frames_hi = 0;
  751. estats->total_tpa_aggregated_frames_lo = 0;
  752. estats->total_tpa_bytes_hi = 0;
  753. estats->total_tpa_bytes_lo = 0;
  754. for_each_eth_queue(bp, i) {
  755. struct bnx2x_fastpath *fp = &bp->fp[i];
  756. struct tstorm_per_queue_stats *tclient =
  757. &bp->fw_stats_data->queue_stats[i].
  758. tstorm_queue_statistics;
  759. struct tstorm_per_queue_stats *old_tclient = &fp->old_tclient;
  760. struct ustorm_per_queue_stats *uclient =
  761. &bp->fw_stats_data->queue_stats[i].
  762. ustorm_queue_statistics;
  763. struct ustorm_per_queue_stats *old_uclient = &fp->old_uclient;
  764. struct xstorm_per_queue_stats *xclient =
  765. &bp->fw_stats_data->queue_stats[i].
  766. xstorm_queue_statistics;
  767. struct xstorm_per_queue_stats *old_xclient = &fp->old_xclient;
  768. struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
  769. u32 diff;
  770. DP(BNX2X_MSG_STATS, "queue[%d]: ucast_sent 0x%x, "
  771. "bcast_sent 0x%x mcast_sent 0x%x\n",
  772. i, xclient->ucast_pkts_sent,
  773. xclient->bcast_pkts_sent, xclient->mcast_pkts_sent);
  774. DP(BNX2X_MSG_STATS, "---------------\n");
  775. qstats->total_broadcast_bytes_received_hi =
  776. le32_to_cpu(tclient->rcv_bcast_bytes.hi);
  777. qstats->total_broadcast_bytes_received_lo =
  778. le32_to_cpu(tclient->rcv_bcast_bytes.lo);
  779. qstats->total_multicast_bytes_received_hi =
  780. le32_to_cpu(tclient->rcv_mcast_bytes.hi);
  781. qstats->total_multicast_bytes_received_lo =
  782. le32_to_cpu(tclient->rcv_mcast_bytes.lo);
  783. qstats->total_unicast_bytes_received_hi =
  784. le32_to_cpu(tclient->rcv_ucast_bytes.hi);
  785. qstats->total_unicast_bytes_received_lo =
  786. le32_to_cpu(tclient->rcv_ucast_bytes.lo);
  787. /*
  788. * sum to total_bytes_received all
  789. * unicast/multicast/broadcast
  790. */
  791. qstats->total_bytes_received_hi =
  792. qstats->total_broadcast_bytes_received_hi;
  793. qstats->total_bytes_received_lo =
  794. qstats->total_broadcast_bytes_received_lo;
  795. ADD_64(qstats->total_bytes_received_hi,
  796. qstats->total_multicast_bytes_received_hi,
  797. qstats->total_bytes_received_lo,
  798. qstats->total_multicast_bytes_received_lo);
  799. ADD_64(qstats->total_bytes_received_hi,
  800. qstats->total_unicast_bytes_received_hi,
  801. qstats->total_bytes_received_lo,
  802. qstats->total_unicast_bytes_received_lo);
  803. qstats->valid_bytes_received_hi =
  804. qstats->total_bytes_received_hi;
  805. qstats->valid_bytes_received_lo =
  806. qstats->total_bytes_received_lo;
  807. UPDATE_EXTEND_TSTAT(rcv_ucast_pkts,
  808. total_unicast_packets_received);
  809. UPDATE_EXTEND_TSTAT(rcv_mcast_pkts,
  810. total_multicast_packets_received);
  811. UPDATE_EXTEND_TSTAT(rcv_bcast_pkts,
  812. total_broadcast_packets_received);
  813. UPDATE_EXTEND_TSTAT(pkts_too_big_discard,
  814. etherstatsoverrsizepkts);
  815. UPDATE_EXTEND_TSTAT(no_buff_discard, no_buff_discard);
  816. SUB_EXTEND_USTAT(ucast_no_buff_pkts,
  817. total_unicast_packets_received);
  818. SUB_EXTEND_USTAT(mcast_no_buff_pkts,
  819. total_multicast_packets_received);
  820. SUB_EXTEND_USTAT(bcast_no_buff_pkts,
  821. total_broadcast_packets_received);
  822. UPDATE_EXTEND_USTAT(ucast_no_buff_pkts, no_buff_discard);
  823. UPDATE_EXTEND_USTAT(mcast_no_buff_pkts, no_buff_discard);
  824. UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard);
  825. qstats->total_broadcast_bytes_transmitted_hi =
  826. le32_to_cpu(xclient->bcast_bytes_sent.hi);
  827. qstats->total_broadcast_bytes_transmitted_lo =
  828. le32_to_cpu(xclient->bcast_bytes_sent.lo);
  829. qstats->total_multicast_bytes_transmitted_hi =
  830. le32_to_cpu(xclient->mcast_bytes_sent.hi);
  831. qstats->total_multicast_bytes_transmitted_lo =
  832. le32_to_cpu(xclient->mcast_bytes_sent.lo);
  833. qstats->total_unicast_bytes_transmitted_hi =
  834. le32_to_cpu(xclient->ucast_bytes_sent.hi);
  835. qstats->total_unicast_bytes_transmitted_lo =
  836. le32_to_cpu(xclient->ucast_bytes_sent.lo);
  837. /*
  838. * sum to total_bytes_transmitted all
  839. * unicast/multicast/broadcast
  840. */
  841. qstats->total_bytes_transmitted_hi =
  842. qstats->total_unicast_bytes_transmitted_hi;
  843. qstats->total_bytes_transmitted_lo =
  844. qstats->total_unicast_bytes_transmitted_lo;
  845. ADD_64(qstats->total_bytes_transmitted_hi,
  846. qstats->total_broadcast_bytes_transmitted_hi,
  847. qstats->total_bytes_transmitted_lo,
  848. qstats->total_broadcast_bytes_transmitted_lo);
  849. ADD_64(qstats->total_bytes_transmitted_hi,
  850. qstats->total_multicast_bytes_transmitted_hi,
  851. qstats->total_bytes_transmitted_lo,
  852. qstats->total_multicast_bytes_transmitted_lo);
  853. UPDATE_EXTEND_XSTAT(ucast_pkts_sent,
  854. total_unicast_packets_transmitted);
  855. UPDATE_EXTEND_XSTAT(mcast_pkts_sent,
  856. total_multicast_packets_transmitted);
  857. UPDATE_EXTEND_XSTAT(bcast_pkts_sent,
  858. total_broadcast_packets_transmitted);
  859. UPDATE_EXTEND_TSTAT(checksum_discard,
  860. total_packets_received_checksum_discarded);
  861. UPDATE_EXTEND_TSTAT(ttl0_discard,
  862. total_packets_received_ttl0_discarded);
  863. UPDATE_EXTEND_XSTAT(error_drop_pkts,
  864. total_transmitted_dropped_packets_error);
  865. /* TPA aggregations completed */
  866. UPDATE_EXTEND_USTAT(coalesced_events, total_tpa_aggregations);
  867. /* Number of network frames aggregated by TPA */
  868. UPDATE_EXTEND_USTAT(coalesced_pkts,
  869. total_tpa_aggregated_frames);
  870. /* Total number of bytes in completed TPA aggregations */
  871. qstats->total_tpa_bytes_lo =
  872. le32_to_cpu(uclient->coalesced_bytes.lo);
  873. qstats->total_tpa_bytes_hi =
  874. le32_to_cpu(uclient->coalesced_bytes.hi);
  875. /* TPA stats per-function */
  876. ADD_64(estats->total_tpa_aggregations_hi,
  877. qstats->total_tpa_aggregations_hi,
  878. estats->total_tpa_aggregations_lo,
  879. qstats->total_tpa_aggregations_lo);
  880. ADD_64(estats->total_tpa_aggregated_frames_hi,
  881. qstats->total_tpa_aggregated_frames_hi,
  882. estats->total_tpa_aggregated_frames_lo,
  883. qstats->total_tpa_aggregated_frames_lo);
  884. ADD_64(estats->total_tpa_bytes_hi,
  885. qstats->total_tpa_bytes_hi,
  886. estats->total_tpa_bytes_lo,
  887. qstats->total_tpa_bytes_lo);
  888. ADD_64(fstats->total_bytes_received_hi,
  889. qstats->total_bytes_received_hi,
  890. fstats->total_bytes_received_lo,
  891. qstats->total_bytes_received_lo);
  892. ADD_64(fstats->total_bytes_transmitted_hi,
  893. qstats->total_bytes_transmitted_hi,
  894. fstats->total_bytes_transmitted_lo,
  895. qstats->total_bytes_transmitted_lo);
  896. ADD_64(fstats->total_unicast_packets_received_hi,
  897. qstats->total_unicast_packets_received_hi,
  898. fstats->total_unicast_packets_received_lo,
  899. qstats->total_unicast_packets_received_lo);
  900. ADD_64(fstats->total_multicast_packets_received_hi,
  901. qstats->total_multicast_packets_received_hi,
  902. fstats->total_multicast_packets_received_lo,
  903. qstats->total_multicast_packets_received_lo);
  904. ADD_64(fstats->total_broadcast_packets_received_hi,
  905. qstats->total_broadcast_packets_received_hi,
  906. fstats->total_broadcast_packets_received_lo,
  907. qstats->total_broadcast_packets_received_lo);
  908. ADD_64(fstats->total_unicast_packets_transmitted_hi,
  909. qstats->total_unicast_packets_transmitted_hi,
  910. fstats->total_unicast_packets_transmitted_lo,
  911. qstats->total_unicast_packets_transmitted_lo);
  912. ADD_64(fstats->total_multicast_packets_transmitted_hi,
  913. qstats->total_multicast_packets_transmitted_hi,
  914. fstats->total_multicast_packets_transmitted_lo,
  915. qstats->total_multicast_packets_transmitted_lo);
  916. ADD_64(fstats->total_broadcast_packets_transmitted_hi,
  917. qstats->total_broadcast_packets_transmitted_hi,
  918. fstats->total_broadcast_packets_transmitted_lo,
  919. qstats->total_broadcast_packets_transmitted_lo);
  920. ADD_64(fstats->valid_bytes_received_hi,
  921. qstats->valid_bytes_received_hi,
  922. fstats->valid_bytes_received_lo,
  923. qstats->valid_bytes_received_lo);
  924. ADD_64(estats->etherstatsoverrsizepkts_hi,
  925. qstats->etherstatsoverrsizepkts_hi,
  926. estats->etherstatsoverrsizepkts_lo,
  927. qstats->etherstatsoverrsizepkts_lo);
  928. ADD_64(estats->no_buff_discard_hi, qstats->no_buff_discard_hi,
  929. estats->no_buff_discard_lo, qstats->no_buff_discard_lo);
  930. }
  931. ADD_64(fstats->total_bytes_received_hi,
  932. estats->rx_stat_ifhcinbadoctets_hi,
  933. fstats->total_bytes_received_lo,
  934. estats->rx_stat_ifhcinbadoctets_lo);
  935. ADD_64(fstats->total_bytes_received_hi,
  936. tfunc->rcv_error_bytes.hi,
  937. fstats->total_bytes_received_lo,
  938. tfunc->rcv_error_bytes.lo);
  939. memcpy(estats, &(fstats->total_bytes_received_hi),
  940. sizeof(struct host_func_stats) - 2*sizeof(u32));
  941. ADD_64(estats->error_bytes_received_hi,
  942. tfunc->rcv_error_bytes.hi,
  943. estats->error_bytes_received_lo,
  944. tfunc->rcv_error_bytes.lo);
  945. ADD_64(estats->etherstatsoverrsizepkts_hi,
  946. estats->rx_stat_dot3statsframestoolong_hi,
  947. estats->etherstatsoverrsizepkts_lo,
  948. estats->rx_stat_dot3statsframestoolong_lo);
  949. ADD_64(estats->error_bytes_received_hi,
  950. estats->rx_stat_ifhcinbadoctets_hi,
  951. estats->error_bytes_received_lo,
  952. estats->rx_stat_ifhcinbadoctets_lo);
  953. if (bp->port.pmf) {
  954. estats->mac_filter_discard =
  955. le32_to_cpu(tport->mac_filter_discard);
  956. estats->mf_tag_discard =
  957. le32_to_cpu(tport->mf_tag_discard);
  958. estats->brb_truncate_discard =
  959. le32_to_cpu(tport->brb_truncate_discard);
  960. estats->mac_discard = le32_to_cpu(tport->mac_discard);
  961. }
  962. fstats->host_func_stats_start = ++fstats->host_func_stats_end;
  963. bp->stats_pending = 0;
  964. return 0;
  965. }
  966. static void bnx2x_net_stats_update(struct bnx2x *bp)
  967. {
  968. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  969. struct net_device_stats *nstats = &bp->dev->stats;
  970. unsigned long tmp;
  971. int i;
  972. nstats->rx_packets =
  973. bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
  974. bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
  975. bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
  976. nstats->tx_packets =
  977. bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
  978. bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
  979. bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
  980. nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
  981. nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
  982. tmp = estats->mac_discard;
  983. for_each_rx_queue(bp, i)
  984. tmp += le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);
  985. nstats->rx_dropped = tmp;
  986. nstats->tx_dropped = 0;
  987. nstats->multicast =
  988. bnx2x_hilo(&estats->total_multicast_packets_received_hi);
  989. nstats->collisions =
  990. bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi);
  991. nstats->rx_length_errors =
  992. bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) +
  993. bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi);
  994. nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) +
  995. bnx2x_hilo(&estats->brb_truncate_hi);
  996. nstats->rx_crc_errors =
  997. bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi);
  998. nstats->rx_frame_errors =
  999. bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi);
  1000. nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi);
  1001. nstats->rx_missed_errors = 0;
  1002. nstats->rx_errors = nstats->rx_length_errors +
  1003. nstats->rx_over_errors +
  1004. nstats->rx_crc_errors +
  1005. nstats->rx_frame_errors +
  1006. nstats->rx_fifo_errors +
  1007. nstats->rx_missed_errors;
  1008. nstats->tx_aborted_errors =
  1009. bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) +
  1010. bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi);
  1011. nstats->tx_carrier_errors =
  1012. bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi);
  1013. nstats->tx_fifo_errors = 0;
  1014. nstats->tx_heartbeat_errors = 0;
  1015. nstats->tx_window_errors = 0;
  1016. nstats->tx_errors = nstats->tx_aborted_errors +
  1017. nstats->tx_carrier_errors +
  1018. bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi);
  1019. }
  1020. static void bnx2x_drv_stats_update(struct bnx2x *bp)
  1021. {
  1022. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  1023. int i;
  1024. estats->driver_xoff = 0;
  1025. estats->rx_err_discard_pkt = 0;
  1026. estats->rx_skb_alloc_failed = 0;
  1027. estats->hw_csum_err = 0;
  1028. for_each_queue(bp, i) {
  1029. struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats;
  1030. estats->driver_xoff += qstats->driver_xoff;
  1031. estats->rx_err_discard_pkt += qstats->rx_err_discard_pkt;
  1032. estats->rx_skb_alloc_failed += qstats->rx_skb_alloc_failed;
  1033. estats->hw_csum_err += qstats->hw_csum_err;
  1034. }
  1035. }
  1036. static bool bnx2x_edebug_stats_stopped(struct bnx2x *bp)
  1037. {
  1038. u32 val;
  1039. if (SHMEM2_HAS(bp, edebug_driver_if[1])) {
  1040. val = SHMEM2_RD(bp, edebug_driver_if[1]);
  1041. if (val == EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT)
  1042. return true;
  1043. }
  1044. return false;
  1045. }
  1046. static void bnx2x_stats_update(struct bnx2x *bp)
  1047. {
  1048. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  1049. if (bnx2x_edebug_stats_stopped(bp))
  1050. return;
  1051. if (*stats_comp != DMAE_COMP_VAL)
  1052. return;
  1053. if (bp->port.pmf)
  1054. bnx2x_hw_stats_update(bp);
  1055. if (bnx2x_storm_stats_update(bp) && (bp->stats_pending++ == 3)) {
  1056. BNX2X_ERR("storm stats were not updated for 3 times\n");
  1057. bnx2x_panic();
  1058. return;
  1059. }
  1060. bnx2x_net_stats_update(bp);
  1061. bnx2x_drv_stats_update(bp);
  1062. if (netif_msg_timer(bp)) {
  1063. struct bnx2x_eth_stats *estats = &bp->eth_stats;
  1064. int i, cos;
  1065. netdev_dbg(bp->dev, "brb drops %u brb truncate %u\n",
  1066. estats->brb_drop_lo, estats->brb_truncate_lo);
  1067. for_each_eth_queue(bp, i) {
  1068. struct bnx2x_fastpath *fp = &bp->fp[i];
  1069. struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
  1070. pr_debug("%s: rx usage(%4u) *rx_cons_sb(%u) rx pkt(%lu) rx calls(%lu %lu)\n",
  1071. fp->name, (le16_to_cpu(*fp->rx_cons_sb) -
  1072. fp->rx_comp_cons),
  1073. le16_to_cpu(*fp->rx_cons_sb),
  1074. bnx2x_hilo(&qstats->
  1075. total_unicast_packets_received_hi),
  1076. fp->rx_calls, fp->rx_pkt);
  1077. }
  1078. for_each_eth_queue(bp, i) {
  1079. struct bnx2x_fastpath *fp = &bp->fp[i];
  1080. struct bnx2x_fp_txdata *txdata;
  1081. struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
  1082. struct netdev_queue *txq;
  1083. pr_debug("%s: tx pkt(%lu) (Xoff events %u)",
  1084. fp->name,
  1085. bnx2x_hilo(
  1086. &qstats->total_unicast_packets_transmitted_hi),
  1087. qstats->driver_xoff);
  1088. for_each_cos_in_tx_queue(fp, cos) {
  1089. txdata = &fp->txdata[cos];
  1090. txq = netdev_get_tx_queue(bp->dev,
  1091. FP_COS_TO_TXQ(fp, cos));
  1092. pr_debug("%d: tx avail(%4u) *tx_cons_sb(%u) tx calls (%lu) %s\n",
  1093. cos,
  1094. bnx2x_tx_avail(bp, txdata),
  1095. le16_to_cpu(*txdata->tx_cons_sb),
  1096. txdata->tx_pkt,
  1097. (netif_tx_queue_stopped(txq) ?
  1098. "Xoff" : "Xon")
  1099. );
  1100. }
  1101. }
  1102. }
  1103. bnx2x_hw_stats_post(bp);
  1104. bnx2x_storm_stats_post(bp);
  1105. }
  1106. static void bnx2x_port_stats_stop(struct bnx2x *bp)
  1107. {
  1108. struct dmae_command *dmae;
  1109. u32 opcode;
  1110. int loader_idx = PMF_DMAE_C(bp);
  1111. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  1112. bp->executer_idx = 0;
  1113. opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, false, 0);
  1114. if (bp->port.port_stx) {
  1115. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  1116. if (bp->func_stx)
  1117. dmae->opcode = bnx2x_dmae_opcode_add_comp(
  1118. opcode, DMAE_COMP_GRC);
  1119. else
  1120. dmae->opcode = bnx2x_dmae_opcode_add_comp(
  1121. opcode, DMAE_COMP_PCI);
  1122. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  1123. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  1124. dmae->dst_addr_lo = bp->port.port_stx >> 2;
  1125. dmae->dst_addr_hi = 0;
  1126. dmae->len = bnx2x_get_port_stats_dma_len(bp);
  1127. if (bp->func_stx) {
  1128. dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
  1129. dmae->comp_addr_hi = 0;
  1130. dmae->comp_val = 1;
  1131. } else {
  1132. dmae->comp_addr_lo =
  1133. U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1134. dmae->comp_addr_hi =
  1135. U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1136. dmae->comp_val = DMAE_COMP_VAL;
  1137. *stats_comp = 0;
  1138. }
  1139. }
  1140. if (bp->func_stx) {
  1141. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  1142. dmae->opcode =
  1143. bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
  1144. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
  1145. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
  1146. dmae->dst_addr_lo = bp->func_stx >> 2;
  1147. dmae->dst_addr_hi = 0;
  1148. dmae->len = sizeof(struct host_func_stats) >> 2;
  1149. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1150. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1151. dmae->comp_val = DMAE_COMP_VAL;
  1152. *stats_comp = 0;
  1153. }
  1154. }
  1155. static void bnx2x_stats_stop(struct bnx2x *bp)
  1156. {
  1157. int update = 0;
  1158. bnx2x_stats_comp(bp);
  1159. if (bp->port.pmf)
  1160. update = (bnx2x_hw_stats_update(bp) == 0);
  1161. update |= (bnx2x_storm_stats_update(bp) == 0);
  1162. if (update) {
  1163. bnx2x_net_stats_update(bp);
  1164. if (bp->port.pmf)
  1165. bnx2x_port_stats_stop(bp);
  1166. bnx2x_hw_stats_post(bp);
  1167. bnx2x_stats_comp(bp);
  1168. }
  1169. }
  1170. static void bnx2x_stats_do_nothing(struct bnx2x *bp)
  1171. {
  1172. }
  1173. static const struct {
  1174. void (*action)(struct bnx2x *bp);
  1175. enum bnx2x_stats_state next_state;
  1176. } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
  1177. /* state event */
  1178. {
  1179. /* DISABLED PMF */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
  1180. /* LINK_UP */ {bnx2x_stats_start, STATS_STATE_ENABLED},
  1181. /* UPDATE */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
  1182. /* STOP */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
  1183. },
  1184. {
  1185. /* ENABLED PMF */ {bnx2x_stats_pmf_start, STATS_STATE_ENABLED},
  1186. /* LINK_UP */ {bnx2x_stats_restart, STATS_STATE_ENABLED},
  1187. /* UPDATE */ {bnx2x_stats_update, STATS_STATE_ENABLED},
  1188. /* STOP */ {bnx2x_stats_stop, STATS_STATE_DISABLED}
  1189. }
  1190. };
  1191. void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
  1192. {
  1193. enum bnx2x_stats_state state;
  1194. if (unlikely(bp->panic))
  1195. return;
  1196. spin_lock_bh(&bp->stats_lock);
  1197. state = bp->stats_state;
  1198. bp->stats_state = bnx2x_stats_stm[state][event].next_state;
  1199. spin_unlock_bh(&bp->stats_lock);
  1200. bnx2x_stats_stm[state][event].action(bp);
  1201. if ((event != STATS_EVENT_UPDATE) || netif_msg_timer(bp))
  1202. DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
  1203. state, event, bp->stats_state);
  1204. }
  1205. static void bnx2x_port_stats_base_init(struct bnx2x *bp)
  1206. {
  1207. struct dmae_command *dmae;
  1208. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  1209. /* sanity */
  1210. if (!bp->port.pmf || !bp->port.port_stx) {
  1211. BNX2X_ERR("BUG!\n");
  1212. return;
  1213. }
  1214. bp->executer_idx = 0;
  1215. dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
  1216. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
  1217. true, DMAE_COMP_PCI);
  1218. dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
  1219. dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
  1220. dmae->dst_addr_lo = bp->port.port_stx >> 2;
  1221. dmae->dst_addr_hi = 0;
  1222. dmae->len = bnx2x_get_port_stats_dma_len(bp);
  1223. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1224. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1225. dmae->comp_val = DMAE_COMP_VAL;
  1226. *stats_comp = 0;
  1227. bnx2x_hw_stats_post(bp);
  1228. bnx2x_stats_comp(bp);
  1229. }
  1230. static void bnx2x_func_stats_base_init(struct bnx2x *bp)
  1231. {
  1232. int vn, vn_max = IS_MF(bp) ? BP_MAX_VN_NUM(bp) : E1VN_MAX;
  1233. u32 func_stx;
  1234. /* sanity */
  1235. if (!bp->port.pmf || !bp->func_stx) {
  1236. BNX2X_ERR("BUG!\n");
  1237. return;
  1238. }
  1239. /* save our func_stx */
  1240. func_stx = bp->func_stx;
  1241. for (vn = VN_0; vn < vn_max; vn++) {
  1242. int mb_idx = BP_FW_MB_IDX_VN(bp, vn);
  1243. bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param);
  1244. bnx2x_func_stats_init(bp);
  1245. bnx2x_hw_stats_post(bp);
  1246. bnx2x_stats_comp(bp);
  1247. }
  1248. /* restore our func_stx */
  1249. bp->func_stx = func_stx;
  1250. }
  1251. static void bnx2x_func_stats_base_update(struct bnx2x *bp)
  1252. {
  1253. struct dmae_command *dmae = &bp->stats_dmae;
  1254. u32 *stats_comp = bnx2x_sp(bp, stats_comp);
  1255. /* sanity */
  1256. if (!bp->func_stx) {
  1257. BNX2X_ERR("BUG!\n");
  1258. return;
  1259. }
  1260. bp->executer_idx = 0;
  1261. memset(dmae, 0, sizeof(struct dmae_command));
  1262. dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
  1263. true, DMAE_COMP_PCI);
  1264. dmae->src_addr_lo = bp->func_stx >> 2;
  1265. dmae->src_addr_hi = 0;
  1266. dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats_base));
  1267. dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats_base));
  1268. dmae->len = sizeof(struct host_func_stats) >> 2;
  1269. dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
  1270. dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
  1271. dmae->comp_val = DMAE_COMP_VAL;
  1272. *stats_comp = 0;
  1273. bnx2x_hw_stats_post(bp);
  1274. bnx2x_stats_comp(bp);
  1275. }
  1276. /**
  1277. * This function will prepare the statistics ramrod data the way
  1278. * we will only have to increment the statistics counter and
  1279. * send the ramrod each time we have to.
  1280. *
  1281. * @param bp
  1282. */
  1283. static inline void bnx2x_prep_fw_stats_req(struct bnx2x *bp)
  1284. {
  1285. int i;
  1286. int first_queue_query_index;
  1287. struct stats_query_header *stats_hdr = &bp->fw_stats_req->hdr;
  1288. dma_addr_t cur_data_offset;
  1289. struct stats_query_entry *cur_query_entry;
  1290. stats_hdr->cmd_num = bp->fw_stats_num;
  1291. stats_hdr->drv_stats_counter = 0;
  1292. /* storm_counters struct contains the counters of completed
  1293. * statistics requests per storm which are incremented by FW
  1294. * each time it completes hadning a statistics ramrod. We will
  1295. * check these counters in the timer handler and discard a
  1296. * (statistics) ramrod completion.
  1297. */
  1298. cur_data_offset = bp->fw_stats_data_mapping +
  1299. offsetof(struct bnx2x_fw_stats_data, storm_counters);
  1300. stats_hdr->stats_counters_addrs.hi =
  1301. cpu_to_le32(U64_HI(cur_data_offset));
  1302. stats_hdr->stats_counters_addrs.lo =
  1303. cpu_to_le32(U64_LO(cur_data_offset));
  1304. /* prepare to the first stats ramrod (will be completed with
  1305. * the counters equal to zero) - init counters to somethig different.
  1306. */
  1307. memset(&bp->fw_stats_data->storm_counters, 0xff,
  1308. sizeof(struct stats_counter));
  1309. /**** Port FW statistics data ****/
  1310. cur_data_offset = bp->fw_stats_data_mapping +
  1311. offsetof(struct bnx2x_fw_stats_data, port);
  1312. cur_query_entry = &bp->fw_stats_req->query[BNX2X_PORT_QUERY_IDX];
  1313. cur_query_entry->kind = STATS_TYPE_PORT;
  1314. /* For port query index is a DONT CARE */
  1315. cur_query_entry->index = BP_PORT(bp);
  1316. /* For port query funcID is a DONT CARE */
  1317. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1318. cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
  1319. cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
  1320. /**** PF FW statistics data ****/
  1321. cur_data_offset = bp->fw_stats_data_mapping +
  1322. offsetof(struct bnx2x_fw_stats_data, pf);
  1323. cur_query_entry = &bp->fw_stats_req->query[BNX2X_PF_QUERY_IDX];
  1324. cur_query_entry->kind = STATS_TYPE_PF;
  1325. /* For PF query index is a DONT CARE */
  1326. cur_query_entry->index = BP_PORT(bp);
  1327. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1328. cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
  1329. cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
  1330. /**** FCoE FW statistics data ****/
  1331. if (!NO_FCOE(bp)) {
  1332. cur_data_offset = bp->fw_stats_data_mapping +
  1333. offsetof(struct bnx2x_fw_stats_data, fcoe);
  1334. cur_query_entry =
  1335. &bp->fw_stats_req->query[BNX2X_FCOE_QUERY_IDX];
  1336. cur_query_entry->kind = STATS_TYPE_FCOE;
  1337. /* For FCoE query index is a DONT CARE */
  1338. cur_query_entry->index = BP_PORT(bp);
  1339. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1340. cur_query_entry->address.hi =
  1341. cpu_to_le32(U64_HI(cur_data_offset));
  1342. cur_query_entry->address.lo =
  1343. cpu_to_le32(U64_LO(cur_data_offset));
  1344. }
  1345. /**** Clients' queries ****/
  1346. cur_data_offset = bp->fw_stats_data_mapping +
  1347. offsetof(struct bnx2x_fw_stats_data, queue_stats);
  1348. /* first queue query index depends whether FCoE offloaded request will
  1349. * be included in the ramrod
  1350. */
  1351. if (!NO_FCOE(bp))
  1352. first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX;
  1353. else
  1354. first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX - 1;
  1355. for_each_eth_queue(bp, i) {
  1356. cur_query_entry =
  1357. &bp->fw_stats_req->
  1358. query[first_queue_query_index + i];
  1359. cur_query_entry->kind = STATS_TYPE_QUEUE;
  1360. cur_query_entry->index = bnx2x_stats_id(&bp->fp[i]);
  1361. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1362. cur_query_entry->address.hi =
  1363. cpu_to_le32(U64_HI(cur_data_offset));
  1364. cur_query_entry->address.lo =
  1365. cpu_to_le32(U64_LO(cur_data_offset));
  1366. cur_data_offset += sizeof(struct per_queue_stats);
  1367. }
  1368. /* add FCoE queue query if needed */
  1369. if (!NO_FCOE(bp)) {
  1370. cur_query_entry =
  1371. &bp->fw_stats_req->
  1372. query[first_queue_query_index + i];
  1373. cur_query_entry->kind = STATS_TYPE_QUEUE;
  1374. cur_query_entry->index = bnx2x_stats_id(&bp->fp[FCOE_IDX]);
  1375. cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
  1376. cur_query_entry->address.hi =
  1377. cpu_to_le32(U64_HI(cur_data_offset));
  1378. cur_query_entry->address.lo =
  1379. cpu_to_le32(U64_LO(cur_data_offset));
  1380. }
  1381. }
  1382. void bnx2x_stats_init(struct bnx2x *bp)
  1383. {
  1384. int /*abs*/port = BP_PORT(bp);
  1385. int mb_idx = BP_FW_MB_IDX(bp);
  1386. int i;
  1387. bp->stats_pending = 0;
  1388. bp->executer_idx = 0;
  1389. bp->stats_counter = 0;
  1390. /* port and func stats for management */
  1391. if (!BP_NOMCP(bp)) {
  1392. bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
  1393. bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param);
  1394. } else {
  1395. bp->port.port_stx = 0;
  1396. bp->func_stx = 0;
  1397. }
  1398. DP(BNX2X_MSG_STATS, "port_stx 0x%x func_stx 0x%x\n",
  1399. bp->port.port_stx, bp->func_stx);
  1400. port = BP_PORT(bp);
  1401. /* port stats */
  1402. memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
  1403. bp->port.old_nig_stats.brb_discard =
  1404. REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
  1405. bp->port.old_nig_stats.brb_truncate =
  1406. REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
  1407. if (!CHIP_IS_E3(bp)) {
  1408. REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
  1409. &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
  1410. REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
  1411. &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
  1412. }
  1413. /* function stats */
  1414. for_each_queue(bp, i) {
  1415. struct bnx2x_fastpath *fp = &bp->fp[i];
  1416. memset(&fp->old_tclient, 0, sizeof(fp->old_tclient));
  1417. memset(&fp->old_uclient, 0, sizeof(fp->old_uclient));
  1418. memset(&fp->old_xclient, 0, sizeof(fp->old_xclient));
  1419. memset(&fp->eth_q_stats, 0, sizeof(fp->eth_q_stats));
  1420. }
  1421. /* Prepare statistics ramrod data */
  1422. bnx2x_prep_fw_stats_req(bp);
  1423. memset(&bp->dev->stats, 0, sizeof(bp->dev->stats));
  1424. memset(&bp->eth_stats, 0, sizeof(bp->eth_stats));
  1425. bp->stats_state = STATS_STATE_DISABLED;
  1426. if (bp->port.pmf) {
  1427. if (bp->port.port_stx)
  1428. bnx2x_port_stats_base_init(bp);
  1429. if (bp->func_stx)
  1430. bnx2x_func_stats_base_init(bp);
  1431. } else if (bp->func_stx)
  1432. bnx2x_func_stats_base_update(bp);
  1433. }