ucb1x00-core.c 19 KB

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  1. /*
  2. * linux/drivers/mfd/ucb1x00-core.c
  3. *
  4. * Copyright (C) 2001 Russell King, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License.
  9. *
  10. * The UCB1x00 core driver provides basic services for handling IO,
  11. * the ADC, interrupts, and accessing registers. It is designed
  12. * such that everything goes through this layer, thereby providing
  13. * a consistent locking methodology, as well as allowing the drivers
  14. * to be used on other non-MCP-enabled hardware platforms.
  15. *
  16. * Note that all locks are private to this file. Nothing else may
  17. * touch them.
  18. */
  19. #include <linux/module.h>
  20. #include <linux/kernel.h>
  21. #include <linux/sched.h>
  22. #include <linux/slab.h>
  23. #include <linux/init.h>
  24. #include <linux/errno.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/device.h>
  27. #include <linux/mutex.h>
  28. #include <linux/mfd/ucb1x00.h>
  29. #include <linux/gpio.h>
  30. #include <linux/semaphore.h>
  31. #include <mach/dma.h>
  32. #include <mach/hardware.h>
  33. static DEFINE_MUTEX(ucb1x00_mutex);
  34. static LIST_HEAD(ucb1x00_drivers);
  35. static LIST_HEAD(ucb1x00_devices);
  36. static struct mcp_device_id ucb1x00_id[] = {
  37. { "ucb1x00", 0 }, /* auto-detection */
  38. { "ucb1200", UCB_ID_1200 },
  39. { "ucb1300", UCB_ID_1300 },
  40. { "tc35143", UCB_ID_TC35143 },
  41. { }
  42. };
  43. MODULE_DEVICE_TABLE(mcp, ucb1x00_id);
  44. /**
  45. * ucb1x00_io_set_dir - set IO direction
  46. * @ucb: UCB1x00 structure describing chip
  47. * @in: bitfield of IO pins to be set as inputs
  48. * @out: bitfield of IO pins to be set as outputs
  49. *
  50. * Set the IO direction of the ten general purpose IO pins on
  51. * the UCB1x00 chip. The @in bitfield has priority over the
  52. * @out bitfield, in that if you specify a pin as both input
  53. * and output, it will end up as an input.
  54. *
  55. * ucb1x00_enable must have been called to enable the comms
  56. * before using this function.
  57. *
  58. * This function takes a spinlock, disabling interrupts.
  59. */
  60. void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out)
  61. {
  62. unsigned long flags;
  63. spin_lock_irqsave(&ucb->io_lock, flags);
  64. ucb->io_dir |= out;
  65. ucb->io_dir &= ~in;
  66. ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
  67. spin_unlock_irqrestore(&ucb->io_lock, flags);
  68. }
  69. /**
  70. * ucb1x00_io_write - set or clear IO outputs
  71. * @ucb: UCB1x00 structure describing chip
  72. * @set: bitfield of IO pins to set to logic '1'
  73. * @clear: bitfield of IO pins to set to logic '0'
  74. *
  75. * Set the IO output state of the specified IO pins. The value
  76. * is retained if the pins are subsequently configured as inputs.
  77. * The @clear bitfield has priority over the @set bitfield -
  78. * outputs will be cleared.
  79. *
  80. * ucb1x00_enable must have been called to enable the comms
  81. * before using this function.
  82. *
  83. * This function takes a spinlock, disabling interrupts.
  84. */
  85. void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear)
  86. {
  87. unsigned long flags;
  88. spin_lock_irqsave(&ucb->io_lock, flags);
  89. ucb->io_out |= set;
  90. ucb->io_out &= ~clear;
  91. ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
  92. spin_unlock_irqrestore(&ucb->io_lock, flags);
  93. }
  94. /**
  95. * ucb1x00_io_read - read the current state of the IO pins
  96. * @ucb: UCB1x00 structure describing chip
  97. *
  98. * Return a bitfield describing the logic state of the ten
  99. * general purpose IO pins.
  100. *
  101. * ucb1x00_enable must have been called to enable the comms
  102. * before using this function.
  103. *
  104. * This function does not take any semaphores or spinlocks.
  105. */
  106. unsigned int ucb1x00_io_read(struct ucb1x00 *ucb)
  107. {
  108. return ucb1x00_reg_read(ucb, UCB_IO_DATA);
  109. }
  110. static void ucb1x00_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  111. {
  112. struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
  113. unsigned long flags;
  114. spin_lock_irqsave(&ucb->io_lock, flags);
  115. if (value)
  116. ucb->io_out |= 1 << offset;
  117. else
  118. ucb->io_out &= ~(1 << offset);
  119. ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
  120. spin_unlock_irqrestore(&ucb->io_lock, flags);
  121. }
  122. static int ucb1x00_gpio_get(struct gpio_chip *chip, unsigned offset)
  123. {
  124. struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
  125. return ucb1x00_reg_read(ucb, UCB_IO_DATA) & (1 << offset);
  126. }
  127. static int ucb1x00_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  128. {
  129. struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
  130. unsigned long flags;
  131. spin_lock_irqsave(&ucb->io_lock, flags);
  132. ucb->io_dir &= ~(1 << offset);
  133. ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
  134. spin_unlock_irqrestore(&ucb->io_lock, flags);
  135. return 0;
  136. }
  137. static int ucb1x00_gpio_direction_output(struct gpio_chip *chip, unsigned offset
  138. , int value)
  139. {
  140. struct ucb1x00 *ucb = container_of(chip, struct ucb1x00, gpio);
  141. unsigned long flags;
  142. spin_lock_irqsave(&ucb->io_lock, flags);
  143. ucb->io_dir |= (1 << offset);
  144. ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
  145. if (value)
  146. ucb->io_out |= 1 << offset;
  147. else
  148. ucb->io_out &= ~(1 << offset);
  149. ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out);
  150. spin_unlock_irqrestore(&ucb->io_lock, flags);
  151. return 0;
  152. }
  153. /*
  154. * UCB1300 data sheet says we must:
  155. * 1. enable ADC => 5us (including reference startup time)
  156. * 2. select input => 51*tsibclk => 4.3us
  157. * 3. start conversion => 102*tsibclk => 8.5us
  158. * (tsibclk = 1/11981000)
  159. * Period between SIB 128-bit frames = 10.7us
  160. */
  161. /**
  162. * ucb1x00_adc_enable - enable the ADC converter
  163. * @ucb: UCB1x00 structure describing chip
  164. *
  165. * Enable the ucb1x00 and ADC converter on the UCB1x00 for use.
  166. * Any code wishing to use the ADC converter must call this
  167. * function prior to using it.
  168. *
  169. * This function takes the ADC semaphore to prevent two or more
  170. * concurrent uses, and therefore may sleep. As a result, it
  171. * can only be called from process context, not interrupt
  172. * context.
  173. *
  174. * You should release the ADC as soon as possible using
  175. * ucb1x00_adc_disable.
  176. */
  177. void ucb1x00_adc_enable(struct ucb1x00 *ucb)
  178. {
  179. down(&ucb->adc_sem);
  180. ucb->adc_cr |= UCB_ADC_ENA;
  181. ucb1x00_enable(ucb);
  182. ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
  183. }
  184. /**
  185. * ucb1x00_adc_read - read the specified ADC channel
  186. * @ucb: UCB1x00 structure describing chip
  187. * @adc_channel: ADC channel mask
  188. * @sync: wait for syncronisation pulse.
  189. *
  190. * Start an ADC conversion and wait for the result. Note that
  191. * synchronised ADC conversions (via the ADCSYNC pin) must wait
  192. * until the trigger is asserted and the conversion is finished.
  193. *
  194. * This function currently spins waiting for the conversion to
  195. * complete (2 frames max without sync).
  196. *
  197. * If called for a synchronised ADC conversion, it may sleep
  198. * with the ADC semaphore held.
  199. */
  200. unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync)
  201. {
  202. unsigned int val;
  203. if (sync)
  204. adc_channel |= UCB_ADC_SYNC_ENA;
  205. ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel);
  206. ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START);
  207. for (;;) {
  208. val = ucb1x00_reg_read(ucb, UCB_ADC_DATA);
  209. if (val & UCB_ADC_DAT_VAL)
  210. break;
  211. /* yield to other processes */
  212. set_current_state(TASK_INTERRUPTIBLE);
  213. schedule_timeout(1);
  214. }
  215. return UCB_ADC_DAT(val);
  216. }
  217. /**
  218. * ucb1x00_adc_disable - disable the ADC converter
  219. * @ucb: UCB1x00 structure describing chip
  220. *
  221. * Disable the ADC converter and release the ADC semaphore.
  222. */
  223. void ucb1x00_adc_disable(struct ucb1x00 *ucb)
  224. {
  225. ucb->adc_cr &= ~UCB_ADC_ENA;
  226. ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr);
  227. ucb1x00_disable(ucb);
  228. up(&ucb->adc_sem);
  229. }
  230. /*
  231. * UCB1x00 Interrupt handling.
  232. *
  233. * The UCB1x00 can generate interrupts when the SIBCLK is stopped.
  234. * Since we need to read an internal register, we must re-enable
  235. * SIBCLK to talk to the chip. We leave the clock running until
  236. * we have finished processing all interrupts from the chip.
  237. */
  238. static irqreturn_t ucb1x00_irq(int irqnr, void *devid)
  239. {
  240. struct ucb1x00 *ucb = devid;
  241. struct ucb1x00_irq *irq;
  242. unsigned int isr, i;
  243. ucb1x00_enable(ucb);
  244. isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS);
  245. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr);
  246. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
  247. for (i = 0, irq = ucb->irq_handler; i < 16 && isr; i++, isr >>= 1, irq++)
  248. if (isr & 1 && irq->fn)
  249. irq->fn(i, irq->devid);
  250. ucb1x00_disable(ucb);
  251. return IRQ_HANDLED;
  252. }
  253. /**
  254. * ucb1x00_hook_irq - hook a UCB1x00 interrupt
  255. * @ucb: UCB1x00 structure describing chip
  256. * @idx: interrupt index
  257. * @fn: function to call when interrupt is triggered
  258. * @devid: device id to pass to interrupt handler
  259. *
  260. * Hook the specified interrupt. You can only register one handler
  261. * for each interrupt source. The interrupt source is not enabled
  262. * by this function; use ucb1x00_enable_irq instead.
  263. *
  264. * Interrupt handlers will be called with other interrupts enabled.
  265. *
  266. * Returns zero on success, or one of the following errors:
  267. * -EINVAL if the interrupt index is invalid
  268. * -EBUSY if the interrupt has already been hooked
  269. */
  270. int ucb1x00_hook_irq(struct ucb1x00 *ucb, unsigned int idx, void (*fn)(int, void *), void *devid)
  271. {
  272. struct ucb1x00_irq *irq;
  273. int ret = -EINVAL;
  274. if (idx < 16) {
  275. irq = ucb->irq_handler + idx;
  276. ret = -EBUSY;
  277. spin_lock_irq(&ucb->lock);
  278. if (irq->fn == NULL) {
  279. irq->devid = devid;
  280. irq->fn = fn;
  281. ret = 0;
  282. }
  283. spin_unlock_irq(&ucb->lock);
  284. }
  285. return ret;
  286. }
  287. /**
  288. * ucb1x00_enable_irq - enable an UCB1x00 interrupt source
  289. * @ucb: UCB1x00 structure describing chip
  290. * @idx: interrupt index
  291. * @edges: interrupt edges to enable
  292. *
  293. * Enable the specified interrupt to trigger on %UCB_RISING,
  294. * %UCB_FALLING or both edges. The interrupt should have been
  295. * hooked by ucb1x00_hook_irq.
  296. */
  297. void ucb1x00_enable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges)
  298. {
  299. unsigned long flags;
  300. if (idx < 16) {
  301. spin_lock_irqsave(&ucb->lock, flags);
  302. ucb1x00_enable(ucb);
  303. if (edges & UCB_RISING) {
  304. ucb->irq_ris_enbl |= 1 << idx;
  305. ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
  306. }
  307. if (edges & UCB_FALLING) {
  308. ucb->irq_fal_enbl |= 1 << idx;
  309. ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
  310. }
  311. ucb1x00_disable(ucb);
  312. spin_unlock_irqrestore(&ucb->lock, flags);
  313. }
  314. }
  315. /**
  316. * ucb1x00_disable_irq - disable an UCB1x00 interrupt source
  317. * @ucb: UCB1x00 structure describing chip
  318. * @edges: interrupt edges to disable
  319. *
  320. * Disable the specified interrupt triggering on the specified
  321. * (%UCB_RISING, %UCB_FALLING or both) edges.
  322. */
  323. void ucb1x00_disable_irq(struct ucb1x00 *ucb, unsigned int idx, int edges)
  324. {
  325. unsigned long flags;
  326. if (idx < 16) {
  327. spin_lock_irqsave(&ucb->lock, flags);
  328. ucb1x00_enable(ucb);
  329. if (edges & UCB_RISING) {
  330. ucb->irq_ris_enbl &= ~(1 << idx);
  331. ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
  332. }
  333. if (edges & UCB_FALLING) {
  334. ucb->irq_fal_enbl &= ~(1 << idx);
  335. ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
  336. }
  337. ucb1x00_disable(ucb);
  338. spin_unlock_irqrestore(&ucb->lock, flags);
  339. }
  340. }
  341. /**
  342. * ucb1x00_free_irq - disable and free the specified UCB1x00 interrupt
  343. * @ucb: UCB1x00 structure describing chip
  344. * @idx: interrupt index
  345. * @devid: device id.
  346. *
  347. * Disable the interrupt source and remove the handler. devid must
  348. * match the devid passed when hooking the interrupt.
  349. *
  350. * Returns zero on success, or one of the following errors:
  351. * -EINVAL if the interrupt index is invalid
  352. * -ENOENT if devid does not match
  353. */
  354. int ucb1x00_free_irq(struct ucb1x00 *ucb, unsigned int idx, void *devid)
  355. {
  356. struct ucb1x00_irq *irq;
  357. int ret;
  358. if (idx >= 16)
  359. goto bad;
  360. irq = ucb->irq_handler + idx;
  361. ret = -ENOENT;
  362. spin_lock_irq(&ucb->lock);
  363. if (irq->devid == devid) {
  364. ucb->irq_ris_enbl &= ~(1 << idx);
  365. ucb->irq_fal_enbl &= ~(1 << idx);
  366. ucb1x00_enable(ucb);
  367. ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl);
  368. ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl);
  369. ucb1x00_disable(ucb);
  370. irq->fn = NULL;
  371. irq->devid = NULL;
  372. ret = 0;
  373. }
  374. spin_unlock_irq(&ucb->lock);
  375. return ret;
  376. bad:
  377. printk(KERN_ERR "Freeing bad UCB1x00 irq %d\n", idx);
  378. return -EINVAL;
  379. }
  380. static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv)
  381. {
  382. struct ucb1x00_dev *dev;
  383. int ret = -ENOMEM;
  384. dev = kmalloc(sizeof(struct ucb1x00_dev), GFP_KERNEL);
  385. if (dev) {
  386. dev->ucb = ucb;
  387. dev->drv = drv;
  388. ret = drv->add(dev);
  389. if (ret == 0) {
  390. list_add(&dev->dev_node, &ucb->devs);
  391. list_add(&dev->drv_node, &drv->devs);
  392. } else {
  393. kfree(dev);
  394. }
  395. }
  396. return ret;
  397. }
  398. static void ucb1x00_remove_dev(struct ucb1x00_dev *dev)
  399. {
  400. dev->drv->remove(dev);
  401. list_del(&dev->dev_node);
  402. list_del(&dev->drv_node);
  403. kfree(dev);
  404. }
  405. /*
  406. * Try to probe our interrupt, rather than relying on lots of
  407. * hard-coded machine dependencies. For reference, the expected
  408. * IRQ mappings are:
  409. *
  410. * Machine Default IRQ
  411. * adsbitsy IRQ_GPCIN4
  412. * cerf IRQ_GPIO_UCB1200_IRQ
  413. * flexanet IRQ_GPIO_GUI
  414. * freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ
  415. * graphicsclient ADS_EXT_IRQ(8)
  416. * graphicsmaster ADS_EXT_IRQ(8)
  417. * lart LART_IRQ_UCB1200
  418. * omnimeter IRQ_GPIO23
  419. * pfs168 IRQ_GPIO_UCB1300_IRQ
  420. * simpad IRQ_GPIO_UCB1300_IRQ
  421. * shannon SHANNON_IRQ_GPIO_IRQ_CODEC
  422. * yopy IRQ_GPIO_UCB1200_IRQ
  423. */
  424. static int ucb1x00_detect_irq(struct ucb1x00 *ucb)
  425. {
  426. unsigned long mask;
  427. mask = probe_irq_on();
  428. if (!mask) {
  429. probe_irq_off(mask);
  430. return NO_IRQ;
  431. }
  432. /*
  433. * Enable the ADC interrupt.
  434. */
  435. ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC);
  436. ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC);
  437. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
  438. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
  439. /*
  440. * Cause an ADC interrupt.
  441. */
  442. ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
  443. ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
  444. /*
  445. * Wait for the conversion to complete.
  446. */
  447. while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0);
  448. ucb1x00_reg_write(ucb, UCB_ADC_CR, 0);
  449. /*
  450. * Disable and clear interrupt.
  451. */
  452. ucb1x00_reg_write(ucb, UCB_IE_RIS, 0);
  453. ucb1x00_reg_write(ucb, UCB_IE_FAL, 0);
  454. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
  455. ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0);
  456. /*
  457. * Read triggered interrupt.
  458. */
  459. return probe_irq_off(mask);
  460. }
  461. static void ucb1x00_release(struct device *dev)
  462. {
  463. struct ucb1x00 *ucb = classdev_to_ucb1x00(dev);
  464. kfree(ucb);
  465. }
  466. static struct class ucb1x00_class = {
  467. .name = "ucb1x00",
  468. .dev_release = ucb1x00_release,
  469. };
  470. static int ucb1x00_probe(struct mcp *mcp)
  471. {
  472. const struct mcp_device_id *mid;
  473. struct ucb1x00 *ucb;
  474. struct ucb1x00_driver *drv;
  475. struct ucb1x00_plat_data *pdata;
  476. unsigned int id;
  477. int ret = -ENODEV;
  478. int temp;
  479. mcp_enable(mcp);
  480. id = mcp_reg_read(mcp, UCB_ID);
  481. mid = mcp_get_device_id(mcp);
  482. if (mid && mid->driver_data) {
  483. if (id != mid->driver_data) {
  484. printk(KERN_WARNING "%s wrong ID %04x found: %04x\n",
  485. mid->name, (unsigned int) mid->driver_data, id);
  486. goto err_disable;
  487. }
  488. } else {
  489. mid = &ucb1x00_id[1];
  490. while (mid->driver_data) {
  491. if (id == mid->driver_data)
  492. break;
  493. mid++;
  494. }
  495. printk(KERN_WARNING "%s ID not found: %04x\n",
  496. ucb1x00_id[0].name, id);
  497. goto err_disable;
  498. }
  499. ucb = kzalloc(sizeof(struct ucb1x00), GFP_KERNEL);
  500. ret = -ENOMEM;
  501. if (!ucb)
  502. goto err_disable;
  503. pdata = mcp->attached_device.platform_data;
  504. ucb->dev.class = &ucb1x00_class;
  505. ucb->dev.parent = &mcp->attached_device;
  506. dev_set_name(&ucb->dev, mid->name);
  507. spin_lock_init(&ucb->lock);
  508. spin_lock_init(&ucb->io_lock);
  509. sema_init(&ucb->adc_sem, 1);
  510. ucb->id = mid;
  511. ucb->mcp = mcp;
  512. ucb->irq = ucb1x00_detect_irq(ucb);
  513. if (ucb->irq == NO_IRQ) {
  514. printk(KERN_ERR "%s: IRQ probe failed\n", mid->name);
  515. ret = -ENODEV;
  516. goto err_free;
  517. }
  518. ucb->gpio.base = -1;
  519. if (pdata && (pdata->gpio_base >= 0)) {
  520. ucb->gpio.label = dev_name(&ucb->dev);
  521. ucb->gpio.base = pdata->gpio_base;
  522. ucb->gpio.ngpio = 10;
  523. ucb->gpio.set = ucb1x00_gpio_set;
  524. ucb->gpio.get = ucb1x00_gpio_get;
  525. ucb->gpio.direction_input = ucb1x00_gpio_direction_input;
  526. ucb->gpio.direction_output = ucb1x00_gpio_direction_output;
  527. ret = gpiochip_add(&ucb->gpio);
  528. if (ret)
  529. goto err_free;
  530. } else
  531. dev_info(&ucb->dev, "gpio_base not set so no gpiolib support");
  532. ret = request_irq(ucb->irq, ucb1x00_irq, IRQF_TRIGGER_RISING,
  533. mid->name, ucb);
  534. if (ret) {
  535. printk(KERN_ERR "%s: unable to grab irq%d: %d\n",
  536. mid->name, ucb->irq, ret);
  537. goto err_gpio;
  538. }
  539. mcp_set_drvdata(mcp, ucb);
  540. ret = device_register(&ucb->dev);
  541. if (ret)
  542. goto err_irq;
  543. INIT_LIST_HEAD(&ucb->devs);
  544. mutex_lock(&ucb1x00_mutex);
  545. list_add(&ucb->node, &ucb1x00_devices);
  546. list_for_each_entry(drv, &ucb1x00_drivers, node) {
  547. ucb1x00_add_dev(ucb, drv);
  548. }
  549. mutex_unlock(&ucb1x00_mutex);
  550. goto out;
  551. err_irq:
  552. free_irq(ucb->irq, ucb);
  553. err_gpio:
  554. if (ucb->gpio.base != -1)
  555. temp = gpiochip_remove(&ucb->gpio);
  556. err_free:
  557. kfree(ucb);
  558. err_disable:
  559. mcp_disable(mcp);
  560. out:
  561. return ret;
  562. }
  563. static void ucb1x00_remove(struct mcp *mcp)
  564. {
  565. struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
  566. struct list_head *l, *n;
  567. int ret;
  568. mutex_lock(&ucb1x00_mutex);
  569. list_del(&ucb->node);
  570. list_for_each_safe(l, n, &ucb->devs) {
  571. struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node);
  572. ucb1x00_remove_dev(dev);
  573. }
  574. mutex_unlock(&ucb1x00_mutex);
  575. if (ucb->gpio.base != -1) {
  576. ret = gpiochip_remove(&ucb->gpio);
  577. if (ret)
  578. dev_err(&ucb->dev, "Can't remove gpio chip: %d\n", ret);
  579. }
  580. free_irq(ucb->irq, ucb);
  581. device_unregister(&ucb->dev);
  582. }
  583. int ucb1x00_register_driver(struct ucb1x00_driver *drv)
  584. {
  585. struct ucb1x00 *ucb;
  586. INIT_LIST_HEAD(&drv->devs);
  587. mutex_lock(&ucb1x00_mutex);
  588. list_add(&drv->node, &ucb1x00_drivers);
  589. list_for_each_entry(ucb, &ucb1x00_devices, node) {
  590. ucb1x00_add_dev(ucb, drv);
  591. }
  592. mutex_unlock(&ucb1x00_mutex);
  593. return 0;
  594. }
  595. void ucb1x00_unregister_driver(struct ucb1x00_driver *drv)
  596. {
  597. struct list_head *n, *l;
  598. mutex_lock(&ucb1x00_mutex);
  599. list_del(&drv->node);
  600. list_for_each_safe(l, n, &drv->devs) {
  601. struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node);
  602. ucb1x00_remove_dev(dev);
  603. }
  604. mutex_unlock(&ucb1x00_mutex);
  605. }
  606. static int ucb1x00_suspend(struct mcp *mcp, pm_message_t state)
  607. {
  608. struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
  609. struct ucb1x00_dev *dev;
  610. mutex_lock(&ucb1x00_mutex);
  611. list_for_each_entry(dev, &ucb->devs, dev_node) {
  612. if (dev->drv->suspend)
  613. dev->drv->suspend(dev, state);
  614. }
  615. mutex_unlock(&ucb1x00_mutex);
  616. return 0;
  617. }
  618. static int ucb1x00_resume(struct mcp *mcp)
  619. {
  620. struct ucb1x00 *ucb = mcp_get_drvdata(mcp);
  621. struct ucb1x00_dev *dev;
  622. ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir);
  623. mutex_lock(&ucb1x00_mutex);
  624. list_for_each_entry(dev, &ucb->devs, dev_node) {
  625. if (dev->drv->resume)
  626. dev->drv->resume(dev);
  627. }
  628. mutex_unlock(&ucb1x00_mutex);
  629. return 0;
  630. }
  631. static struct mcp_driver ucb1x00_driver = {
  632. .drv = {
  633. .name = "ucb1x00",
  634. },
  635. .probe = ucb1x00_probe,
  636. .remove = ucb1x00_remove,
  637. .suspend = ucb1x00_suspend,
  638. .resume = ucb1x00_resume,
  639. .id_table = ucb1x00_id,
  640. };
  641. static int __init ucb1x00_init(void)
  642. {
  643. int ret = class_register(&ucb1x00_class);
  644. if (ret == 0) {
  645. ret = mcp_driver_register(&ucb1x00_driver);
  646. if (ret)
  647. class_unregister(&ucb1x00_class);
  648. }
  649. return ret;
  650. }
  651. static void __exit ucb1x00_exit(void)
  652. {
  653. mcp_driver_unregister(&ucb1x00_driver);
  654. class_unregister(&ucb1x00_class);
  655. }
  656. module_init(ucb1x00_init);
  657. module_exit(ucb1x00_exit);
  658. EXPORT_SYMBOL(ucb1x00_io_set_dir);
  659. EXPORT_SYMBOL(ucb1x00_io_write);
  660. EXPORT_SYMBOL(ucb1x00_io_read);
  661. EXPORT_SYMBOL(ucb1x00_adc_enable);
  662. EXPORT_SYMBOL(ucb1x00_adc_read);
  663. EXPORT_SYMBOL(ucb1x00_adc_disable);
  664. EXPORT_SYMBOL(ucb1x00_hook_irq);
  665. EXPORT_SYMBOL(ucb1x00_free_irq);
  666. EXPORT_SYMBOL(ucb1x00_enable_irq);
  667. EXPORT_SYMBOL(ucb1x00_disable_irq);
  668. EXPORT_SYMBOL(ucb1x00_register_driver);
  669. EXPORT_SYMBOL(ucb1x00_unregister_driver);
  670. MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
  671. MODULE_DESCRIPTION("UCB1x00 core driver");
  672. MODULE_LICENSE("GPL");