radeon_cs.c 15 KB

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  1. /*
  2. * Copyright 2008 Jerome Glisse.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors:
  25. * Jerome Glisse <glisse@freedesktop.org>
  26. */
  27. #include "drmP.h"
  28. #include "radeon_drm.h"
  29. #include "radeon_reg.h"
  30. #include "radeon.h"
  31. void r100_cs_dump_packet(struct radeon_cs_parser *p,
  32. struct radeon_cs_packet *pkt);
  33. int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
  34. {
  35. struct drm_device *ddev = p->rdev->ddev;
  36. struct radeon_cs_chunk *chunk;
  37. unsigned i, j;
  38. bool duplicate;
  39. if (p->chunk_relocs_idx == -1) {
  40. return 0;
  41. }
  42. chunk = &p->chunks[p->chunk_relocs_idx];
  43. /* FIXME: we assume that each relocs use 4 dwords */
  44. p->nrelocs = chunk->length_dw / 4;
  45. p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
  46. if (p->relocs_ptr == NULL) {
  47. return -ENOMEM;
  48. }
  49. p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
  50. if (p->relocs == NULL) {
  51. return -ENOMEM;
  52. }
  53. for (i = 0; i < p->nrelocs; i++) {
  54. struct drm_radeon_cs_reloc *r;
  55. duplicate = false;
  56. r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
  57. for (j = 0; j < i; j++) {
  58. if (r->handle == p->relocs[j].handle) {
  59. p->relocs_ptr[i] = &p->relocs[j];
  60. duplicate = true;
  61. break;
  62. }
  63. }
  64. if (!duplicate) {
  65. p->relocs[i].gobj = drm_gem_object_lookup(ddev,
  66. p->filp,
  67. r->handle);
  68. if (p->relocs[i].gobj == NULL) {
  69. DRM_ERROR("gem object lookup failed 0x%x\n",
  70. r->handle);
  71. return -ENOENT;
  72. }
  73. p->relocs_ptr[i] = &p->relocs[i];
  74. p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
  75. p->relocs[i].lobj.bo = p->relocs[i].robj;
  76. p->relocs[i].lobj.wdomain = r->write_domain;
  77. p->relocs[i].lobj.rdomain = r->read_domains;
  78. p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
  79. p->relocs[i].handle = r->handle;
  80. p->relocs[i].flags = r->flags;
  81. radeon_bo_list_add_object(&p->relocs[i].lobj,
  82. &p->validated);
  83. if (p->relocs[i].robj->tbo.sync_obj && !(r->flags & RADEON_RELOC_DONT_SYNC)) {
  84. struct radeon_fence *fence = p->relocs[i].robj->tbo.sync_obj;
  85. if (!radeon_fence_signaled(fence)) {
  86. p->sync_to_ring[fence->ring] = true;
  87. }
  88. }
  89. } else
  90. p->relocs[i].handle = 0;
  91. }
  92. return radeon_bo_list_validate(&p->validated);
  93. }
  94. static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
  95. {
  96. p->priority = priority;
  97. switch (ring) {
  98. default:
  99. DRM_ERROR("unknown ring id: %d\n", ring);
  100. return -EINVAL;
  101. case RADEON_CS_RING_GFX:
  102. p->ring = RADEON_RING_TYPE_GFX_INDEX;
  103. break;
  104. case RADEON_CS_RING_COMPUTE:
  105. /* for now */
  106. p->ring = RADEON_RING_TYPE_GFX_INDEX;
  107. break;
  108. }
  109. return 0;
  110. }
  111. static int radeon_cs_sync_rings(struct radeon_cs_parser *p)
  112. {
  113. int i, r;
  114. for (i = 0; i < RADEON_NUM_RINGS; ++i) {
  115. /* no need to sync to our own or unused rings */
  116. if (i == p->ring || !p->sync_to_ring[i] || !p->rdev->ring[i].ready)
  117. continue;
  118. if (!p->ib->fence->semaphore) {
  119. r = radeon_semaphore_create(p->rdev, &p->ib->fence->semaphore);
  120. if (r)
  121. return r;
  122. }
  123. r = radeon_ring_lock(p->rdev, &p->rdev->ring[i], 3);
  124. if (r)
  125. return r;
  126. radeon_semaphore_emit_signal(p->rdev, i, p->ib->fence->semaphore);
  127. radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[i]);
  128. r = radeon_ring_lock(p->rdev, &p->rdev->ring[p->ring], 3);
  129. if (r)
  130. return r;
  131. radeon_semaphore_emit_wait(p->rdev, p->ring, p->ib->fence->semaphore);
  132. radeon_ring_unlock_commit(p->rdev, &p->rdev->ring[p->ring]);
  133. }
  134. return 0;
  135. }
  136. int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
  137. {
  138. struct drm_radeon_cs *cs = data;
  139. uint64_t *chunk_array_ptr;
  140. unsigned size, i;
  141. u32 ring = RADEON_CS_RING_GFX;
  142. s32 priority = 0;
  143. if (!cs->num_chunks) {
  144. return 0;
  145. }
  146. /* get chunks */
  147. INIT_LIST_HEAD(&p->validated);
  148. p->idx = 0;
  149. p->chunk_ib_idx = -1;
  150. p->chunk_relocs_idx = -1;
  151. p->chunk_flags_idx = -1;
  152. p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
  153. if (p->chunks_array == NULL) {
  154. return -ENOMEM;
  155. }
  156. chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
  157. if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
  158. sizeof(uint64_t)*cs->num_chunks)) {
  159. return -EFAULT;
  160. }
  161. p->cs_flags = 0;
  162. p->nchunks = cs->num_chunks;
  163. p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
  164. if (p->chunks == NULL) {
  165. return -ENOMEM;
  166. }
  167. for (i = 0; i < p->nchunks; i++) {
  168. struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
  169. struct drm_radeon_cs_chunk user_chunk;
  170. uint32_t __user *cdata;
  171. chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
  172. if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
  173. sizeof(struct drm_radeon_cs_chunk))) {
  174. return -EFAULT;
  175. }
  176. p->chunks[i].length_dw = user_chunk.length_dw;
  177. p->chunks[i].kdata = NULL;
  178. p->chunks[i].chunk_id = user_chunk.chunk_id;
  179. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
  180. p->chunk_relocs_idx = i;
  181. }
  182. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
  183. p->chunk_ib_idx = i;
  184. /* zero length IB isn't useful */
  185. if (p->chunks[i].length_dw == 0)
  186. return -EINVAL;
  187. }
  188. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
  189. p->chunk_flags_idx = i;
  190. /* zero length flags aren't useful */
  191. if (p->chunks[i].length_dw == 0)
  192. return -EINVAL;
  193. }
  194. p->chunks[i].length_dw = user_chunk.length_dw;
  195. p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
  196. cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
  197. if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
  198. (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
  199. size = p->chunks[i].length_dw * sizeof(uint32_t);
  200. p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
  201. if (p->chunks[i].kdata == NULL) {
  202. return -ENOMEM;
  203. }
  204. if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
  205. p->chunks[i].user_ptr, size)) {
  206. return -EFAULT;
  207. }
  208. if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
  209. p->cs_flags = p->chunks[i].kdata[0];
  210. if (p->chunks[i].length_dw > 1)
  211. ring = p->chunks[i].kdata[1];
  212. if (p->chunks[i].length_dw > 2)
  213. priority = (s32)p->chunks[i].kdata[2];
  214. }
  215. }
  216. }
  217. if ((p->cs_flags & RADEON_CS_USE_VM) &&
  218. !p->rdev->vm_manager.enabled) {
  219. DRM_ERROR("VM not active on asic!\n");
  220. if (p->chunk_relocs_idx != -1)
  221. kfree(p->chunks[p->chunk_relocs_idx].kdata);
  222. if (p->chunk_flags_idx != -1)
  223. kfree(p->chunks[p->chunk_flags_idx].kdata);
  224. return -EINVAL;
  225. }
  226. if (radeon_cs_get_ring(p, ring, priority)) {
  227. if (p->chunk_relocs_idx != -1)
  228. kfree(p->chunks[p->chunk_relocs_idx].kdata);
  229. if (p->chunk_flags_idx != -1)
  230. kfree(p->chunks[p->chunk_flags_idx].kdata);
  231. return -EINVAL;
  232. }
  233. /* deal with non-vm */
  234. if ((p->chunk_ib_idx != -1) &&
  235. ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
  236. (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
  237. if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
  238. DRM_ERROR("cs IB too big: %d\n",
  239. p->chunks[p->chunk_ib_idx].length_dw);
  240. return -EINVAL;
  241. }
  242. p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
  243. p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
  244. if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
  245. p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
  246. kfree(p->chunks[p->chunk_ib_idx].kpage[0]);
  247. kfree(p->chunks[p->chunk_ib_idx].kpage[1]);
  248. return -ENOMEM;
  249. }
  250. p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
  251. p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
  252. p->chunks[p->chunk_ib_idx].last_copied_page = -1;
  253. p->chunks[p->chunk_ib_idx].last_page_index =
  254. ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
  255. }
  256. return 0;
  257. }
  258. /**
  259. * cs_parser_fini() - clean parser states
  260. * @parser: parser structure holding parsing context.
  261. * @error: error number
  262. *
  263. * If error is set than unvalidate buffer, otherwise just free memory
  264. * used by parsing context.
  265. **/
  266. static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
  267. {
  268. unsigned i;
  269. if (!error && parser->ib)
  270. ttm_eu_fence_buffer_objects(&parser->validated,
  271. parser->ib->fence);
  272. else
  273. ttm_eu_backoff_reservation(&parser->validated);
  274. if (parser->relocs != NULL) {
  275. for (i = 0; i < parser->nrelocs; i++) {
  276. if (parser->relocs[i].gobj)
  277. drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
  278. }
  279. }
  280. kfree(parser->track);
  281. kfree(parser->relocs);
  282. kfree(parser->relocs_ptr);
  283. for (i = 0; i < parser->nchunks; i++) {
  284. kfree(parser->chunks[i].kdata);
  285. kfree(parser->chunks[i].kpage[0]);
  286. kfree(parser->chunks[i].kpage[1]);
  287. }
  288. kfree(parser->chunks);
  289. kfree(parser->chunks_array);
  290. radeon_ib_free(parser->rdev, &parser->ib);
  291. }
  292. static int radeon_cs_ib_chunk(struct radeon_device *rdev,
  293. struct radeon_cs_parser *parser)
  294. {
  295. struct radeon_cs_chunk *ib_chunk;
  296. int r;
  297. if (parser->chunk_ib_idx == -1)
  298. return 0;
  299. if (parser->cs_flags & RADEON_CS_USE_VM)
  300. return 0;
  301. ib_chunk = &parser->chunks[parser->chunk_ib_idx];
  302. /* Copy the packet into the IB, the parser will read from the
  303. * input memory (cached) and write to the IB (which can be
  304. * uncached).
  305. */
  306. r = radeon_ib_get(rdev, parser->ring, &parser->ib,
  307. ib_chunk->length_dw * 4);
  308. if (r) {
  309. DRM_ERROR("Failed to get ib !\n");
  310. return r;
  311. }
  312. parser->ib->length_dw = ib_chunk->length_dw;
  313. r = radeon_cs_parse(parser);
  314. if (r || parser->parser_error) {
  315. DRM_ERROR("Invalid command stream !\n");
  316. return r;
  317. }
  318. r = radeon_cs_finish_pages(parser);
  319. if (r) {
  320. DRM_ERROR("Invalid command stream !\n");
  321. return r;
  322. }
  323. r = radeon_cs_sync_rings(parser);
  324. if (r) {
  325. DRM_ERROR("Failed to synchronize rings !\n");
  326. }
  327. parser->ib->vm_id = 0;
  328. r = radeon_ib_schedule(rdev, parser->ib);
  329. if (r) {
  330. DRM_ERROR("Failed to schedule IB !\n");
  331. }
  332. return 0;
  333. }
  334. static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
  335. struct radeon_vm *vm)
  336. {
  337. struct radeon_bo_list *lobj;
  338. struct radeon_bo *bo;
  339. int r;
  340. list_for_each_entry(lobj, &parser->validated, tv.head) {
  341. bo = lobj->bo;
  342. r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
  343. if (r) {
  344. return r;
  345. }
  346. }
  347. return 0;
  348. }
  349. static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
  350. struct radeon_cs_parser *parser)
  351. {
  352. struct radeon_cs_chunk *ib_chunk;
  353. struct radeon_fpriv *fpriv = parser->filp->driver_priv;
  354. struct radeon_vm *vm = &fpriv->vm;
  355. int r;
  356. if (parser->chunk_ib_idx == -1)
  357. return 0;
  358. if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
  359. return 0;
  360. ib_chunk = &parser->chunks[parser->chunk_ib_idx];
  361. if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
  362. DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
  363. return -EINVAL;
  364. }
  365. r = radeon_ib_get(rdev, parser->ring, &parser->ib,
  366. ib_chunk->length_dw * 4);
  367. if (r) {
  368. DRM_ERROR("Failed to get ib !\n");
  369. return r;
  370. }
  371. parser->ib->length_dw = ib_chunk->length_dw;
  372. /* Copy the packet into the IB */
  373. if (DRM_COPY_FROM_USER(parser->ib->ptr, ib_chunk->user_ptr,
  374. ib_chunk->length_dw * 4)) {
  375. return -EFAULT;
  376. }
  377. r = radeon_ring_ib_parse(rdev, parser->ring, parser->ib);
  378. if (r) {
  379. return r;
  380. }
  381. mutex_lock(&vm->mutex);
  382. r = radeon_vm_bind(rdev, vm);
  383. if (r) {
  384. goto out;
  385. }
  386. r = radeon_bo_vm_update_pte(parser, vm);
  387. if (r) {
  388. goto out;
  389. }
  390. r = radeon_cs_sync_rings(parser);
  391. if (r) {
  392. DRM_ERROR("Failed to synchronize rings !\n");
  393. }
  394. parser->ib->vm_id = vm->id;
  395. /* ib pool is bind at 0 in virtual address space to gpu_addr is the
  396. * offset inside the pool bo
  397. */
  398. parser->ib->gpu_addr = parser->ib->sa_bo.offset;
  399. r = radeon_ib_schedule(rdev, parser->ib);
  400. out:
  401. if (!r) {
  402. if (vm->fence) {
  403. radeon_fence_unref(&vm->fence);
  404. }
  405. vm->fence = radeon_fence_ref(parser->ib->fence);
  406. }
  407. mutex_unlock(&fpriv->vm.mutex);
  408. return r;
  409. }
  410. int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
  411. {
  412. struct radeon_device *rdev = dev->dev_private;
  413. struct radeon_cs_parser parser;
  414. int r;
  415. radeon_mutex_lock(&rdev->cs_mutex);
  416. /* initialize parser */
  417. memset(&parser, 0, sizeof(struct radeon_cs_parser));
  418. parser.filp = filp;
  419. parser.rdev = rdev;
  420. parser.dev = rdev->dev;
  421. parser.family = rdev->family;
  422. r = radeon_cs_parser_init(&parser, data);
  423. if (r) {
  424. DRM_ERROR("Failed to initialize parser !\n");
  425. radeon_cs_parser_fini(&parser, r);
  426. radeon_mutex_unlock(&rdev->cs_mutex);
  427. return r;
  428. }
  429. r = radeon_cs_parser_relocs(&parser);
  430. if (r) {
  431. if (r != -ERESTARTSYS)
  432. DRM_ERROR("Failed to parse relocation %d!\n", r);
  433. radeon_cs_parser_fini(&parser, r);
  434. radeon_mutex_unlock(&rdev->cs_mutex);
  435. return r;
  436. }
  437. r = radeon_cs_ib_chunk(rdev, &parser);
  438. if (r) {
  439. goto out;
  440. }
  441. r = radeon_cs_ib_vm_chunk(rdev, &parser);
  442. if (r) {
  443. goto out;
  444. }
  445. out:
  446. radeon_cs_parser_fini(&parser, r);
  447. radeon_mutex_unlock(&rdev->cs_mutex);
  448. return r;
  449. }
  450. int radeon_cs_finish_pages(struct radeon_cs_parser *p)
  451. {
  452. struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  453. int i;
  454. int size = PAGE_SIZE;
  455. for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
  456. if (i == ibc->last_page_index) {
  457. size = (ibc->length_dw * 4) % PAGE_SIZE;
  458. if (size == 0)
  459. size = PAGE_SIZE;
  460. }
  461. if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
  462. ibc->user_ptr + (i * PAGE_SIZE),
  463. size))
  464. return -EFAULT;
  465. }
  466. return 0;
  467. }
  468. int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
  469. {
  470. int new_page;
  471. struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
  472. int i;
  473. int size = PAGE_SIZE;
  474. for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
  475. if (DRM_COPY_FROM_USER(p->ib->ptr + (i * (PAGE_SIZE/4)),
  476. ibc->user_ptr + (i * PAGE_SIZE),
  477. PAGE_SIZE)) {
  478. p->parser_error = -EFAULT;
  479. return 0;
  480. }
  481. }
  482. new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
  483. if (pg_idx == ibc->last_page_index) {
  484. size = (ibc->length_dw * 4) % PAGE_SIZE;
  485. if (size == 0)
  486. size = PAGE_SIZE;
  487. }
  488. if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
  489. ibc->user_ptr + (pg_idx * PAGE_SIZE),
  490. size)) {
  491. p->parser_error = -EFAULT;
  492. return 0;
  493. }
  494. /* copy to IB here */
  495. memcpy((void *)(p->ib->ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
  496. ibc->last_copied_page = pg_idx;
  497. ibc->kpage_idx[new_page] = pg_idx;
  498. return new_page;
  499. }