tpm_tis.c 22 KB

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  1. /*
  2. * Copyright (C) 2005, 2006 IBM Corporation
  3. *
  4. * Authors:
  5. * Leendert van Doorn <leendert@watson.ibm.com>
  6. * Kylene Hall <kjhall@us.ibm.com>
  7. *
  8. * Maintained by: <tpmdd-devel@lists.sourceforge.net>
  9. *
  10. * Device driver for TCG/TCPA TPM (trusted platform module).
  11. * Specifications at www.trustedcomputinggroup.org
  12. *
  13. * This device driver implements the TPM interface as defined in
  14. * the TCG TPM Interface Spec version 1.2, revision 1.0.
  15. *
  16. * This program is free software; you can redistribute it and/or
  17. * modify it under the terms of the GNU General Public License as
  18. * published by the Free Software Foundation, version 2 of the
  19. * License.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/moduleparam.h>
  24. #include <linux/pnp.h>
  25. #include <linux/slab.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/wait.h>
  28. #include <linux/acpi.h>
  29. #include <linux/freezer.h>
  30. #include "tpm.h"
  31. enum tis_access {
  32. TPM_ACCESS_VALID = 0x80,
  33. TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
  34. TPM_ACCESS_REQUEST_PENDING = 0x04,
  35. TPM_ACCESS_REQUEST_USE = 0x02,
  36. };
  37. enum tis_status {
  38. TPM_STS_VALID = 0x80,
  39. TPM_STS_COMMAND_READY = 0x40,
  40. TPM_STS_GO = 0x20,
  41. TPM_STS_DATA_AVAIL = 0x10,
  42. TPM_STS_DATA_EXPECT = 0x08,
  43. };
  44. enum tis_int_flags {
  45. TPM_GLOBAL_INT_ENABLE = 0x80000000,
  46. TPM_INTF_BURST_COUNT_STATIC = 0x100,
  47. TPM_INTF_CMD_READY_INT = 0x080,
  48. TPM_INTF_INT_EDGE_FALLING = 0x040,
  49. TPM_INTF_INT_EDGE_RISING = 0x020,
  50. TPM_INTF_INT_LEVEL_LOW = 0x010,
  51. TPM_INTF_INT_LEVEL_HIGH = 0x008,
  52. TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
  53. TPM_INTF_STS_VALID_INT = 0x002,
  54. TPM_INTF_DATA_AVAIL_INT = 0x001,
  55. };
  56. enum tis_defaults {
  57. TIS_MEM_BASE = 0xFED40000,
  58. TIS_MEM_LEN = 0x5000,
  59. TIS_SHORT_TIMEOUT = 750, /* ms */
  60. TIS_LONG_TIMEOUT = 2000, /* 2 sec */
  61. };
  62. #define TPM_ACCESS(l) (0x0000 | ((l) << 12))
  63. #define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
  64. #define TPM_INT_VECTOR(l) (0x000C | ((l) << 12))
  65. #define TPM_INT_STATUS(l) (0x0010 | ((l) << 12))
  66. #define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12))
  67. #define TPM_STS(l) (0x0018 | ((l) << 12))
  68. #define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))
  69. #define TPM_DID_VID(l) (0x0F00 | ((l) << 12))
  70. #define TPM_RID(l) (0x0F04 | ((l) << 12))
  71. static LIST_HEAD(tis_chips);
  72. static DEFINE_SPINLOCK(tis_lock);
  73. #if defined(CONFIG_PNP) && defined(CONFIG_ACPI)
  74. static int is_itpm(struct pnp_dev *dev)
  75. {
  76. struct acpi_device *acpi = pnp_acpi_device(dev);
  77. struct acpi_hardware_id *id;
  78. list_for_each_entry(id, &acpi->pnp.ids, list) {
  79. if (!strcmp("INTC0102", id->id))
  80. return 1;
  81. }
  82. return 0;
  83. }
  84. #else
  85. static inline int is_itpm(struct pnp_dev *dev)
  86. {
  87. return 0;
  88. }
  89. #endif
  90. static int check_locality(struct tpm_chip *chip, int l)
  91. {
  92. if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
  93. (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
  94. (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID))
  95. return chip->vendor.locality = l;
  96. return -1;
  97. }
  98. static void release_locality(struct tpm_chip *chip, int l, int force)
  99. {
  100. if (force || (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
  101. (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) ==
  102. (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID))
  103. iowrite8(TPM_ACCESS_ACTIVE_LOCALITY,
  104. chip->vendor.iobase + TPM_ACCESS(l));
  105. }
  106. static int request_locality(struct tpm_chip *chip, int l)
  107. {
  108. unsigned long stop, timeout;
  109. long rc;
  110. if (check_locality(chip, l) >= 0)
  111. return l;
  112. iowrite8(TPM_ACCESS_REQUEST_USE,
  113. chip->vendor.iobase + TPM_ACCESS(l));
  114. stop = jiffies + chip->vendor.timeout_a;
  115. if (chip->vendor.irq) {
  116. again:
  117. timeout = stop - jiffies;
  118. if ((long)timeout <= 0)
  119. return -1;
  120. rc = wait_event_interruptible_timeout(chip->vendor.int_queue,
  121. (check_locality
  122. (chip, l) >= 0),
  123. timeout);
  124. if (rc > 0)
  125. return l;
  126. if (rc == -ERESTARTSYS && freezing(current)) {
  127. clear_thread_flag(TIF_SIGPENDING);
  128. goto again;
  129. }
  130. } else {
  131. /* wait for burstcount */
  132. do {
  133. if (check_locality(chip, l) >= 0)
  134. return l;
  135. msleep(TPM_TIMEOUT);
  136. }
  137. while (time_before(jiffies, stop));
  138. }
  139. return -1;
  140. }
  141. static u8 tpm_tis_status(struct tpm_chip *chip)
  142. {
  143. return ioread8(chip->vendor.iobase +
  144. TPM_STS(chip->vendor.locality));
  145. }
  146. static void tpm_tis_ready(struct tpm_chip *chip)
  147. {
  148. /* this causes the current command to be aborted */
  149. iowrite8(TPM_STS_COMMAND_READY,
  150. chip->vendor.iobase + TPM_STS(chip->vendor.locality));
  151. }
  152. static int get_burstcount(struct tpm_chip *chip)
  153. {
  154. unsigned long stop;
  155. int burstcnt;
  156. /* wait for burstcount */
  157. /* which timeout value, spec has 2 answers (c & d) */
  158. stop = jiffies + chip->vendor.timeout_d;
  159. do {
  160. burstcnt = ioread8(chip->vendor.iobase +
  161. TPM_STS(chip->vendor.locality) + 1);
  162. burstcnt += ioread8(chip->vendor.iobase +
  163. TPM_STS(chip->vendor.locality) +
  164. 2) << 8;
  165. if (burstcnt)
  166. return burstcnt;
  167. msleep(TPM_TIMEOUT);
  168. } while (time_before(jiffies, stop));
  169. return -EBUSY;
  170. }
  171. static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
  172. {
  173. int size = 0, burstcnt;
  174. while (size < count &&
  175. wait_for_tpm_stat(chip,
  176. TPM_STS_DATA_AVAIL | TPM_STS_VALID,
  177. chip->vendor.timeout_c,
  178. &chip->vendor.read_queue)
  179. == 0) {
  180. burstcnt = get_burstcount(chip);
  181. for (; burstcnt > 0 && size < count; burstcnt--)
  182. buf[size++] = ioread8(chip->vendor.iobase +
  183. TPM_DATA_FIFO(chip->vendor.
  184. locality));
  185. }
  186. return size;
  187. }
  188. static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
  189. {
  190. int size = 0;
  191. int expected, status;
  192. if (count < TPM_HEADER_SIZE) {
  193. size = -EIO;
  194. goto out;
  195. }
  196. /* read first 10 bytes, including tag, paramsize, and result */
  197. if ((size =
  198. recv_data(chip, buf, TPM_HEADER_SIZE)) < TPM_HEADER_SIZE) {
  199. dev_err(chip->dev, "Unable to read header\n");
  200. goto out;
  201. }
  202. expected = be32_to_cpu(*(__be32 *) (buf + 2));
  203. if (expected > count) {
  204. size = -EIO;
  205. goto out;
  206. }
  207. if ((size +=
  208. recv_data(chip, &buf[TPM_HEADER_SIZE],
  209. expected - TPM_HEADER_SIZE)) < expected) {
  210. dev_err(chip->dev, "Unable to read remainder of result\n");
  211. size = -ETIME;
  212. goto out;
  213. }
  214. wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
  215. &chip->vendor.int_queue);
  216. status = tpm_tis_status(chip);
  217. if (status & TPM_STS_DATA_AVAIL) { /* retry? */
  218. dev_err(chip->dev, "Error left over data\n");
  219. size = -EIO;
  220. goto out;
  221. }
  222. out:
  223. tpm_tis_ready(chip);
  224. release_locality(chip, chip->vendor.locality, 0);
  225. return size;
  226. }
  227. static bool itpm;
  228. module_param(itpm, bool, 0444);
  229. MODULE_PARM_DESC(itpm, "Force iTPM workarounds (found on some Lenovo laptops)");
  230. /*
  231. * If interrupts are used (signaled by an irq set in the vendor structure)
  232. * tpm.c can skip polling for the data to be available as the interrupt is
  233. * waited for here
  234. */
  235. static int tpm_tis_send_data(struct tpm_chip *chip, u8 *buf, size_t len)
  236. {
  237. int rc, status, burstcnt;
  238. size_t count = 0;
  239. if (request_locality(chip, 0) < 0)
  240. return -EBUSY;
  241. status = tpm_tis_status(chip);
  242. if ((status & TPM_STS_COMMAND_READY) == 0) {
  243. tpm_tis_ready(chip);
  244. if (wait_for_tpm_stat
  245. (chip, TPM_STS_COMMAND_READY, chip->vendor.timeout_b,
  246. &chip->vendor.int_queue) < 0) {
  247. rc = -ETIME;
  248. goto out_err;
  249. }
  250. }
  251. while (count < len - 1) {
  252. burstcnt = get_burstcount(chip);
  253. for (; burstcnt > 0 && count < len - 1; burstcnt--) {
  254. iowrite8(buf[count], chip->vendor.iobase +
  255. TPM_DATA_FIFO(chip->vendor.locality));
  256. count++;
  257. }
  258. wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
  259. &chip->vendor.int_queue);
  260. status = tpm_tis_status(chip);
  261. if (!itpm && (status & TPM_STS_DATA_EXPECT) == 0) {
  262. rc = -EIO;
  263. goto out_err;
  264. }
  265. }
  266. /* write last byte */
  267. iowrite8(buf[count],
  268. chip->vendor.iobase + TPM_DATA_FIFO(chip->vendor.locality));
  269. wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
  270. &chip->vendor.int_queue);
  271. status = tpm_tis_status(chip);
  272. if ((status & TPM_STS_DATA_EXPECT) != 0) {
  273. rc = -EIO;
  274. goto out_err;
  275. }
  276. return 0;
  277. out_err:
  278. tpm_tis_ready(chip);
  279. release_locality(chip, chip->vendor.locality, 0);
  280. return rc;
  281. }
  282. /*
  283. * If interrupts are used (signaled by an irq set in the vendor structure)
  284. * tpm.c can skip polling for the data to be available as the interrupt is
  285. * waited for here
  286. */
  287. static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len)
  288. {
  289. int rc;
  290. u32 ordinal;
  291. rc = tpm_tis_send_data(chip, buf, len);
  292. if (rc < 0)
  293. return rc;
  294. /* go and do it */
  295. iowrite8(TPM_STS_GO,
  296. chip->vendor.iobase + TPM_STS(chip->vendor.locality));
  297. if (chip->vendor.irq) {
  298. ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
  299. if (wait_for_tpm_stat
  300. (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID,
  301. tpm_calc_ordinal_duration(chip, ordinal),
  302. &chip->vendor.read_queue) < 0) {
  303. rc = -ETIME;
  304. goto out_err;
  305. }
  306. }
  307. return len;
  308. out_err:
  309. tpm_tis_ready(chip);
  310. release_locality(chip, chip->vendor.locality, 0);
  311. return rc;
  312. }
  313. /*
  314. * Early probing for iTPM with STS_DATA_EXPECT flaw.
  315. * Try sending command without itpm flag set and if that
  316. * fails, repeat with itpm flag set.
  317. */
  318. static int probe_itpm(struct tpm_chip *chip)
  319. {
  320. int rc = 0;
  321. u8 cmd_getticks[] = {
  322. 0x00, 0xc1, 0x00, 0x00, 0x00, 0x0a,
  323. 0x00, 0x00, 0x00, 0xf1
  324. };
  325. size_t len = sizeof(cmd_getticks);
  326. int rem_itpm = itpm;
  327. itpm = 0;
  328. rc = tpm_tis_send_data(chip, cmd_getticks, len);
  329. if (rc == 0)
  330. goto out;
  331. tpm_tis_ready(chip);
  332. release_locality(chip, chip->vendor.locality, 0);
  333. itpm = 1;
  334. rc = tpm_tis_send_data(chip, cmd_getticks, len);
  335. if (rc == 0) {
  336. dev_info(chip->dev, "Detected an iTPM.\n");
  337. rc = 1;
  338. } else
  339. rc = -EFAULT;
  340. out:
  341. itpm = rem_itpm;
  342. tpm_tis_ready(chip);
  343. /* some TPMs need a break here otherwise they will not work
  344. * correctly on the immediately subsequent command */
  345. msleep(chip->vendor.timeout_b);
  346. release_locality(chip, chip->vendor.locality, 0);
  347. return rc;
  348. }
  349. static const struct file_operations tis_ops = {
  350. .owner = THIS_MODULE,
  351. .llseek = no_llseek,
  352. .open = tpm_open,
  353. .read = tpm_read,
  354. .write = tpm_write,
  355. .release = tpm_release,
  356. };
  357. static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL);
  358. static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL);
  359. static DEVICE_ATTR(enabled, S_IRUGO, tpm_show_enabled, NULL);
  360. static DEVICE_ATTR(active, S_IRUGO, tpm_show_active, NULL);
  361. static DEVICE_ATTR(owned, S_IRUGO, tpm_show_owned, NULL);
  362. static DEVICE_ATTR(temp_deactivated, S_IRUGO, tpm_show_temp_deactivated,
  363. NULL);
  364. static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps_1_2, NULL);
  365. static DEVICE_ATTR(cancel, S_IWUSR | S_IWGRP, NULL, tpm_store_cancel);
  366. static DEVICE_ATTR(durations, S_IRUGO, tpm_show_durations, NULL);
  367. static DEVICE_ATTR(timeouts, S_IRUGO, tpm_show_timeouts, NULL);
  368. static struct attribute *tis_attrs[] = {
  369. &dev_attr_pubek.attr,
  370. &dev_attr_pcrs.attr,
  371. &dev_attr_enabled.attr,
  372. &dev_attr_active.attr,
  373. &dev_attr_owned.attr,
  374. &dev_attr_temp_deactivated.attr,
  375. &dev_attr_caps.attr,
  376. &dev_attr_cancel.attr,
  377. &dev_attr_durations.attr,
  378. &dev_attr_timeouts.attr, NULL,
  379. };
  380. static struct attribute_group tis_attr_grp = {
  381. .attrs = tis_attrs
  382. };
  383. static struct tpm_vendor_specific tpm_tis = {
  384. .status = tpm_tis_status,
  385. .recv = tpm_tis_recv,
  386. .send = tpm_tis_send,
  387. .cancel = tpm_tis_ready,
  388. .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
  389. .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
  390. .req_canceled = TPM_STS_COMMAND_READY,
  391. .attr_group = &tis_attr_grp,
  392. .miscdev = {
  393. .fops = &tis_ops,},
  394. };
  395. static irqreturn_t tis_int_probe(int irq, void *dev_id)
  396. {
  397. struct tpm_chip *chip = dev_id;
  398. u32 interrupt;
  399. interrupt = ioread32(chip->vendor.iobase +
  400. TPM_INT_STATUS(chip->vendor.locality));
  401. if (interrupt == 0)
  402. return IRQ_NONE;
  403. chip->vendor.probed_irq = irq;
  404. /* Clear interrupts handled with TPM_EOI */
  405. iowrite32(interrupt,
  406. chip->vendor.iobase +
  407. TPM_INT_STATUS(chip->vendor.locality));
  408. return IRQ_HANDLED;
  409. }
  410. static irqreturn_t tis_int_handler(int dummy, void *dev_id)
  411. {
  412. struct tpm_chip *chip = dev_id;
  413. u32 interrupt;
  414. int i;
  415. interrupt = ioread32(chip->vendor.iobase +
  416. TPM_INT_STATUS(chip->vendor.locality));
  417. if (interrupt == 0)
  418. return IRQ_NONE;
  419. if (interrupt & TPM_INTF_DATA_AVAIL_INT)
  420. wake_up_interruptible(&chip->vendor.read_queue);
  421. if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT)
  422. for (i = 0; i < 5; i++)
  423. if (check_locality(chip, i) >= 0)
  424. break;
  425. if (interrupt &
  426. (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT |
  427. TPM_INTF_CMD_READY_INT))
  428. wake_up_interruptible(&chip->vendor.int_queue);
  429. /* Clear interrupts handled with TPM_EOI */
  430. iowrite32(interrupt,
  431. chip->vendor.iobase +
  432. TPM_INT_STATUS(chip->vendor.locality));
  433. ioread32(chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality));
  434. return IRQ_HANDLED;
  435. }
  436. static bool interrupts = 1;
  437. module_param(interrupts, bool, 0444);
  438. MODULE_PARM_DESC(interrupts, "Enable interrupts");
  439. static int tpm_tis_init(struct device *dev, resource_size_t start,
  440. resource_size_t len, unsigned int irq)
  441. {
  442. u32 vendor, intfcaps, intmask;
  443. int rc, i, irq_s, irq_e;
  444. struct tpm_chip *chip;
  445. if (!(chip = tpm_register_hardware(dev, &tpm_tis)))
  446. return -ENODEV;
  447. chip->vendor.iobase = ioremap(start, len);
  448. if (!chip->vendor.iobase) {
  449. rc = -EIO;
  450. goto out_err;
  451. }
  452. /* Default timeouts */
  453. chip->vendor.timeout_a = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
  454. chip->vendor.timeout_b = msecs_to_jiffies(TIS_LONG_TIMEOUT);
  455. chip->vendor.timeout_c = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
  456. chip->vendor.timeout_d = msecs_to_jiffies(TIS_SHORT_TIMEOUT);
  457. if (request_locality(chip, 0) != 0) {
  458. rc = -ENODEV;
  459. goto out_err;
  460. }
  461. vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
  462. dev_info(dev,
  463. "1.2 TPM (device-id 0x%X, rev-id %d)\n",
  464. vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0)));
  465. if (!itpm) {
  466. itpm = probe_itpm(chip);
  467. if (itpm < 0) {
  468. rc = -ENODEV;
  469. goto out_err;
  470. }
  471. }
  472. if (itpm)
  473. dev_info(dev, "Intel iTPM workaround enabled\n");
  474. /* Figure out the capabilities */
  475. intfcaps =
  476. ioread32(chip->vendor.iobase +
  477. TPM_INTF_CAPS(chip->vendor.locality));
  478. dev_dbg(dev, "TPM interface capabilities (0x%x):\n",
  479. intfcaps);
  480. if (intfcaps & TPM_INTF_BURST_COUNT_STATIC)
  481. dev_dbg(dev, "\tBurst Count Static\n");
  482. if (intfcaps & TPM_INTF_CMD_READY_INT)
  483. dev_dbg(dev, "\tCommand Ready Int Support\n");
  484. if (intfcaps & TPM_INTF_INT_EDGE_FALLING)
  485. dev_dbg(dev, "\tInterrupt Edge Falling\n");
  486. if (intfcaps & TPM_INTF_INT_EDGE_RISING)
  487. dev_dbg(dev, "\tInterrupt Edge Rising\n");
  488. if (intfcaps & TPM_INTF_INT_LEVEL_LOW)
  489. dev_dbg(dev, "\tInterrupt Level Low\n");
  490. if (intfcaps & TPM_INTF_INT_LEVEL_HIGH)
  491. dev_dbg(dev, "\tInterrupt Level High\n");
  492. if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT)
  493. dev_dbg(dev, "\tLocality Change Int Support\n");
  494. if (intfcaps & TPM_INTF_STS_VALID_INT)
  495. dev_dbg(dev, "\tSts Valid Int Support\n");
  496. if (intfcaps & TPM_INTF_DATA_AVAIL_INT)
  497. dev_dbg(dev, "\tData Avail Int Support\n");
  498. /* get the timeouts before testing for irqs */
  499. if (tpm_get_timeouts(chip)) {
  500. dev_err(dev, "Could not get TPM timeouts and durations\n");
  501. rc = -ENODEV;
  502. goto out_err;
  503. }
  504. if (tpm_do_selftest(chip)) {
  505. dev_err(dev, "TPM self test failed\n");
  506. rc = -ENODEV;
  507. goto out_err;
  508. }
  509. /* INTERRUPT Setup */
  510. init_waitqueue_head(&chip->vendor.read_queue);
  511. init_waitqueue_head(&chip->vendor.int_queue);
  512. intmask =
  513. ioread32(chip->vendor.iobase +
  514. TPM_INT_ENABLE(chip->vendor.locality));
  515. intmask |= TPM_INTF_CMD_READY_INT
  516. | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
  517. | TPM_INTF_STS_VALID_INT;
  518. iowrite32(intmask,
  519. chip->vendor.iobase +
  520. TPM_INT_ENABLE(chip->vendor.locality));
  521. if (interrupts)
  522. chip->vendor.irq = irq;
  523. if (interrupts && !chip->vendor.irq) {
  524. irq_s =
  525. ioread8(chip->vendor.iobase +
  526. TPM_INT_VECTOR(chip->vendor.locality));
  527. if (irq_s) {
  528. irq_e = irq_s;
  529. } else {
  530. irq_s = 3;
  531. irq_e = 15;
  532. }
  533. for (i = irq_s; i <= irq_e && chip->vendor.irq == 0; i++) {
  534. iowrite8(i, chip->vendor.iobase +
  535. TPM_INT_VECTOR(chip->vendor.locality));
  536. if (request_irq
  537. (i, tis_int_probe, IRQF_SHARED,
  538. chip->vendor.miscdev.name, chip) != 0) {
  539. dev_info(chip->dev,
  540. "Unable to request irq: %d for probe\n",
  541. i);
  542. continue;
  543. }
  544. /* Clear all existing */
  545. iowrite32(ioread32
  546. (chip->vendor.iobase +
  547. TPM_INT_STATUS(chip->vendor.locality)),
  548. chip->vendor.iobase +
  549. TPM_INT_STATUS(chip->vendor.locality));
  550. /* Turn on */
  551. iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
  552. chip->vendor.iobase +
  553. TPM_INT_ENABLE(chip->vendor.locality));
  554. chip->vendor.probed_irq = 0;
  555. /* Generate Interrupts */
  556. tpm_gen_interrupt(chip);
  557. chip->vendor.irq = chip->vendor.probed_irq;
  558. /* free_irq will call into tis_int_probe;
  559. clear all irqs we haven't seen while doing
  560. tpm_gen_interrupt */
  561. iowrite32(ioread32
  562. (chip->vendor.iobase +
  563. TPM_INT_STATUS(chip->vendor.locality)),
  564. chip->vendor.iobase +
  565. TPM_INT_STATUS(chip->vendor.locality));
  566. /* Turn off */
  567. iowrite32(intmask,
  568. chip->vendor.iobase +
  569. TPM_INT_ENABLE(chip->vendor.locality));
  570. free_irq(i, chip);
  571. }
  572. }
  573. if (chip->vendor.irq) {
  574. iowrite8(chip->vendor.irq,
  575. chip->vendor.iobase +
  576. TPM_INT_VECTOR(chip->vendor.locality));
  577. if (request_irq
  578. (chip->vendor.irq, tis_int_handler, IRQF_SHARED,
  579. chip->vendor.miscdev.name, chip) != 0) {
  580. dev_info(chip->dev,
  581. "Unable to request irq: %d for use\n",
  582. chip->vendor.irq);
  583. chip->vendor.irq = 0;
  584. } else {
  585. /* Clear all existing */
  586. iowrite32(ioread32
  587. (chip->vendor.iobase +
  588. TPM_INT_STATUS(chip->vendor.locality)),
  589. chip->vendor.iobase +
  590. TPM_INT_STATUS(chip->vendor.locality));
  591. /* Turn on */
  592. iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
  593. chip->vendor.iobase +
  594. TPM_INT_ENABLE(chip->vendor.locality));
  595. }
  596. }
  597. INIT_LIST_HEAD(&chip->vendor.list);
  598. spin_lock(&tis_lock);
  599. list_add(&chip->vendor.list, &tis_chips);
  600. spin_unlock(&tis_lock);
  601. return 0;
  602. out_err:
  603. if (chip->vendor.iobase)
  604. iounmap(chip->vendor.iobase);
  605. tpm_remove_hardware(chip->dev);
  606. return rc;
  607. }
  608. static void tpm_tis_reenable_interrupts(struct tpm_chip *chip)
  609. {
  610. u32 intmask;
  611. /* reenable interrupts that device may have lost or
  612. BIOS/firmware may have disabled */
  613. iowrite8(chip->vendor.irq, chip->vendor.iobase +
  614. TPM_INT_VECTOR(chip->vendor.locality));
  615. intmask =
  616. ioread32(chip->vendor.iobase +
  617. TPM_INT_ENABLE(chip->vendor.locality));
  618. intmask |= TPM_INTF_CMD_READY_INT
  619. | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
  620. | TPM_INTF_STS_VALID_INT | TPM_GLOBAL_INT_ENABLE;
  621. iowrite32(intmask,
  622. chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality));
  623. }
  624. #ifdef CONFIG_PNP
  625. static int __devinit tpm_tis_pnp_init(struct pnp_dev *pnp_dev,
  626. const struct pnp_device_id *pnp_id)
  627. {
  628. resource_size_t start, len;
  629. unsigned int irq = 0;
  630. start = pnp_mem_start(pnp_dev, 0);
  631. len = pnp_mem_len(pnp_dev, 0);
  632. if (pnp_irq_valid(pnp_dev, 0))
  633. irq = pnp_irq(pnp_dev, 0);
  634. else
  635. interrupts = 0;
  636. if (is_itpm(pnp_dev))
  637. itpm = 1;
  638. return tpm_tis_init(&pnp_dev->dev, start, len, irq);
  639. }
  640. static int tpm_tis_pnp_suspend(struct pnp_dev *dev, pm_message_t msg)
  641. {
  642. return tpm_pm_suspend(&dev->dev, msg);
  643. }
  644. static int tpm_tis_pnp_resume(struct pnp_dev *dev)
  645. {
  646. struct tpm_chip *chip = pnp_get_drvdata(dev);
  647. int ret;
  648. if (chip->vendor.irq)
  649. tpm_tis_reenable_interrupts(chip);
  650. ret = tpm_pm_resume(&dev->dev);
  651. if (!ret)
  652. tpm_do_selftest(chip);
  653. return ret;
  654. }
  655. static struct pnp_device_id tpm_pnp_tbl[] __devinitdata = {
  656. {"PNP0C31", 0}, /* TPM */
  657. {"ATM1200", 0}, /* Atmel */
  658. {"IFX0102", 0}, /* Infineon */
  659. {"BCM0101", 0}, /* Broadcom */
  660. {"BCM0102", 0}, /* Broadcom */
  661. {"NSC1200", 0}, /* National */
  662. {"ICO0102", 0}, /* Intel */
  663. /* Add new here */
  664. {"", 0}, /* User Specified */
  665. {"", 0} /* Terminator */
  666. };
  667. MODULE_DEVICE_TABLE(pnp, tpm_pnp_tbl);
  668. static __devexit void tpm_tis_pnp_remove(struct pnp_dev *dev)
  669. {
  670. struct tpm_chip *chip = pnp_get_drvdata(dev);
  671. tpm_dev_vendor_release(chip);
  672. kfree(chip);
  673. }
  674. static struct pnp_driver tis_pnp_driver = {
  675. .name = "tpm_tis",
  676. .id_table = tpm_pnp_tbl,
  677. .probe = tpm_tis_pnp_init,
  678. .suspend = tpm_tis_pnp_suspend,
  679. .resume = tpm_tis_pnp_resume,
  680. .remove = tpm_tis_pnp_remove,
  681. };
  682. #define TIS_HID_USR_IDX sizeof(tpm_pnp_tbl)/sizeof(struct pnp_device_id) -2
  683. module_param_string(hid, tpm_pnp_tbl[TIS_HID_USR_IDX].id,
  684. sizeof(tpm_pnp_tbl[TIS_HID_USR_IDX].id), 0444);
  685. MODULE_PARM_DESC(hid, "Set additional specific HID for this driver to probe");
  686. #endif
  687. static int tpm_tis_suspend(struct platform_device *dev, pm_message_t msg)
  688. {
  689. return tpm_pm_suspend(&dev->dev, msg);
  690. }
  691. static int tpm_tis_resume(struct platform_device *dev)
  692. {
  693. struct tpm_chip *chip = dev_get_drvdata(&dev->dev);
  694. if (chip->vendor.irq)
  695. tpm_tis_reenable_interrupts(chip);
  696. return tpm_pm_resume(&dev->dev);
  697. }
  698. static struct platform_driver tis_drv = {
  699. .driver = {
  700. .name = "tpm_tis",
  701. .owner = THIS_MODULE,
  702. },
  703. .suspend = tpm_tis_suspend,
  704. .resume = tpm_tis_resume,
  705. };
  706. static struct platform_device *pdev;
  707. static bool force;
  708. module_param(force, bool, 0444);
  709. MODULE_PARM_DESC(force, "Force device probe rather than using ACPI entry");
  710. static int __init init_tis(void)
  711. {
  712. int rc;
  713. #ifdef CONFIG_PNP
  714. if (!force)
  715. return pnp_register_driver(&tis_pnp_driver);
  716. #endif
  717. rc = platform_driver_register(&tis_drv);
  718. if (rc < 0)
  719. return rc;
  720. if (IS_ERR(pdev=platform_device_register_simple("tpm_tis", -1, NULL, 0)))
  721. return PTR_ERR(pdev);
  722. if((rc=tpm_tis_init(&pdev->dev, TIS_MEM_BASE, TIS_MEM_LEN, 0)) != 0) {
  723. platform_device_unregister(pdev);
  724. platform_driver_unregister(&tis_drv);
  725. }
  726. return rc;
  727. }
  728. static void __exit cleanup_tis(void)
  729. {
  730. struct tpm_vendor_specific *i, *j;
  731. struct tpm_chip *chip;
  732. spin_lock(&tis_lock);
  733. list_for_each_entry_safe(i, j, &tis_chips, list) {
  734. chip = to_tpm_chip(i);
  735. tpm_remove_hardware(chip->dev);
  736. iowrite32(~TPM_GLOBAL_INT_ENABLE &
  737. ioread32(chip->vendor.iobase +
  738. TPM_INT_ENABLE(chip->vendor.
  739. locality)),
  740. chip->vendor.iobase +
  741. TPM_INT_ENABLE(chip->vendor.locality));
  742. release_locality(chip, chip->vendor.locality, 1);
  743. if (chip->vendor.irq)
  744. free_irq(chip->vendor.irq, chip);
  745. iounmap(i->iobase);
  746. list_del(&i->list);
  747. }
  748. spin_unlock(&tis_lock);
  749. #ifdef CONFIG_PNP
  750. if (!force) {
  751. pnp_unregister_driver(&tis_pnp_driver);
  752. return;
  753. }
  754. #endif
  755. platform_device_unregister(pdev);
  756. platform_driver_unregister(&tis_drv);
  757. }
  758. module_init(init_tis);
  759. module_exit(cleanup_tis);
  760. MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
  761. MODULE_DESCRIPTION("TPM Driver");
  762. MODULE_VERSION("2.0");
  763. MODULE_LICENSE("GPL");