p2041si-post.dtsi 7.9 KB

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  1. /*
  2. * P2041/P2040 Silicon/SoC Device Tree Source (post include)
  3. *
  4. * Copyright 2011 Freescale Semiconductor Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. * * Redistributions of source code must retain the above copyright
  9. * notice, this list of conditions and the following disclaimer.
  10. * * Redistributions in binary form must reproduce the above copyright
  11. * notice, this list of conditions and the following disclaimer in the
  12. * documentation and/or other materials provided with the distribution.
  13. * * Neither the name of Freescale Semiconductor nor the
  14. * names of its contributors may be used to endorse or promote products
  15. * derived from this software without specific prior written permission.
  16. *
  17. *
  18. * ALTERNATIVELY, this software may be distributed under the terms of the
  19. * GNU General Public License ("GPL") as published by the Free Software
  20. * Foundation, either version 2 of that License or (at your option) any
  21. * later version.
  22. *
  23. * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24. * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26. * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. &lbc {
  35. compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
  36. interrupts = <25 2 0 0>;
  37. #address-cells = <2>;
  38. #size-cells = <1>;
  39. };
  40. /* controller at 0x200000 */
  41. &pci0 {
  42. compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
  43. device_type = "pci";
  44. #size-cells = <2>;
  45. #address-cells = <3>;
  46. bus-range = <0x0 0xff>;
  47. clock-frequency = <33333333>;
  48. interrupts = <16 2 1 15>;
  49. pcie@0 {
  50. reg = <0 0 0 0 0>;
  51. #interrupt-cells = <1>;
  52. #size-cells = <2>;
  53. #address-cells = <3>;
  54. device_type = "pci";
  55. interrupts = <16 2 1 15>;
  56. interrupt-map-mask = <0xf800 0 0 7>;
  57. interrupt-map = <
  58. /* IDSEL 0x0 */
  59. 0000 0 0 1 &mpic 40 1 0 0
  60. 0000 0 0 2 &mpic 1 1 0 0
  61. 0000 0 0 3 &mpic 2 1 0 0
  62. 0000 0 0 4 &mpic 3 1 0 0
  63. >;
  64. };
  65. };
  66. /* controller at 0x201000 */
  67. &pci1 {
  68. compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
  69. device_type = "pci";
  70. #size-cells = <2>;
  71. #address-cells = <3>;
  72. bus-range = <0 0xff>;
  73. clock-frequency = <33333333>;
  74. interrupts = <16 2 1 14>;
  75. pcie@0 {
  76. reg = <0 0 0 0 0>;
  77. #interrupt-cells = <1>;
  78. #size-cells = <2>;
  79. #address-cells = <3>;
  80. device_type = "pci";
  81. interrupts = <16 2 1 14>;
  82. interrupt-map-mask = <0xf800 0 0 7>;
  83. interrupt-map = <
  84. /* IDSEL 0x0 */
  85. 0000 0 0 1 &mpic 41 1 0 0
  86. 0000 0 0 2 &mpic 5 1 0 0
  87. 0000 0 0 3 &mpic 6 1 0 0
  88. 0000 0 0 4 &mpic 7 1 0 0
  89. >;
  90. };
  91. };
  92. /* controller at 0x202000 */
  93. &pci2 {
  94. compatible = "fsl,p2041-pcie", "fsl,qoriq-pcie-v2.2";
  95. device_type = "pci";
  96. #size-cells = <2>;
  97. #address-cells = <3>;
  98. bus-range = <0x0 0xff>;
  99. clock-frequency = <33333333>;
  100. interrupts = <16 2 1 13>;
  101. pcie@0 {
  102. reg = <0 0 0 0 0>;
  103. #interrupt-cells = <1>;
  104. #size-cells = <2>;
  105. #address-cells = <3>;
  106. device_type = "pci";
  107. interrupts = <16 2 1 13>;
  108. interrupt-map-mask = <0xf800 0 0 7>;
  109. interrupt-map = <
  110. /* IDSEL 0x0 */
  111. 0000 0 0 1 &mpic 42 1 0 0
  112. 0000 0 0 2 &mpic 9 1 0 0
  113. 0000 0 0 3 &mpic 10 1 0 0
  114. 0000 0 0 4 &mpic 11 1 0 0
  115. >;
  116. };
  117. };
  118. &rio {
  119. compatible = "fsl,srio";
  120. interrupts = <16 2 1 11>;
  121. #address-cells = <2>;
  122. #size-cells = <2>;
  123. ranges;
  124. port1 {
  125. #address-cells = <2>;
  126. #size-cells = <2>;
  127. cell-index = <1>;
  128. };
  129. port2 {
  130. #address-cells = <2>;
  131. #size-cells = <2>;
  132. cell-index = <2>;
  133. };
  134. };
  135. &dcsr {
  136. #address-cells = <1>;
  137. #size-cells = <1>;
  138. compatible = "fsl,dcsr", "simple-bus";
  139. dcsr-epu@0 {
  140. compatible = "fsl,dcsr-epu";
  141. interrupts = <52 2 0 0
  142. 84 2 0 0
  143. 85 2 0 0>;
  144. reg = <0x0 0x1000>;
  145. };
  146. dcsr-npc {
  147. compatible = "fsl,dcsr-npc";
  148. reg = <0x1000 0x1000 0x1000000 0x8000>;
  149. };
  150. dcsr-nxc@2000 {
  151. compatible = "fsl,dcsr-nxc";
  152. reg = <0x2000 0x1000>;
  153. };
  154. dcsr-corenet {
  155. compatible = "fsl,dcsr-corenet";
  156. reg = <0x8000 0x1000 0xB0000 0x1000>;
  157. };
  158. dcsr-dpaa@9000 {
  159. compatible = "fsl,p2041-dcsr-dpaa", "fsl,dcsr-dpaa";
  160. reg = <0x9000 0x1000>;
  161. };
  162. dcsr-ocn@11000 {
  163. compatible = "fsl,p2041-dcsr-ocn", "fsl,dcsr-ocn";
  164. reg = <0x11000 0x1000>;
  165. };
  166. dcsr-ddr@12000 {
  167. compatible = "fsl,dcsr-ddr";
  168. dev-handle = <&ddr1>;
  169. reg = <0x12000 0x1000>;
  170. };
  171. dcsr-nal@18000 {
  172. compatible = "fsl,p2041-dcsr-nal", "fsl,dcsr-nal";
  173. reg = <0x18000 0x1000>;
  174. };
  175. dcsr-rcpm@22000 {
  176. compatible = "fsl,p2041-dcsr-rcpm", "fsl,dcsr-rcpm";
  177. reg = <0x22000 0x1000>;
  178. };
  179. dcsr-cpu-sb-proxy@40000 {
  180. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  181. cpu-handle = <&cpu0>;
  182. reg = <0x40000 0x1000>;
  183. };
  184. dcsr-cpu-sb-proxy@41000 {
  185. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  186. cpu-handle = <&cpu1>;
  187. reg = <0x41000 0x1000>;
  188. };
  189. dcsr-cpu-sb-proxy@42000 {
  190. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  191. cpu-handle = <&cpu2>;
  192. reg = <0x42000 0x1000>;
  193. };
  194. dcsr-cpu-sb-proxy@43000 {
  195. compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
  196. cpu-handle = <&cpu3>;
  197. reg = <0x43000 0x1000>;
  198. };
  199. };
  200. &soc {
  201. #address-cells = <1>;
  202. #size-cells = <1>;
  203. device_type = "soc";
  204. compatible = "simple-bus";
  205. soc-sram-error {
  206. compatible = "fsl,soc-sram-error";
  207. interrupts = <16 2 1 29>;
  208. };
  209. corenet-law@0 {
  210. compatible = "fsl,corenet-law";
  211. reg = <0x0 0x1000>;
  212. fsl,num-laws = <32>;
  213. };
  214. ddr1: memory-controller@8000 {
  215. compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
  216. reg = <0x8000 0x1000>;
  217. interrupts = <16 2 1 23>;
  218. };
  219. cpc: l3-cache-controller@10000 {
  220. compatible = "fsl,p2041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
  221. reg = <0x10000 0x1000>;
  222. interrupts = <16 2 1 27>;
  223. };
  224. corenet-cf@18000 {
  225. compatible = "fsl,corenet-cf";
  226. reg = <0x18000 0x1000>;
  227. interrupts = <16 2 1 31>;
  228. fsl,ccf-num-csdids = <32>;
  229. fsl,ccf-num-snoopids = <32>;
  230. };
  231. iommu@20000 {
  232. compatible = "fsl,pamu-v1.0", "fsl,pamu";
  233. reg = <0x20000 0x4000>;
  234. interrupts = <
  235. 24 2 0 0
  236. 16 2 1 30>;
  237. };
  238. /include/ "qoriq-mpic.dtsi"
  239. guts: global-utilities@e0000 {
  240. compatible = "fsl,qoriq-device-config-1.0";
  241. reg = <0xe0000 0xe00>;
  242. fsl,has-rstcr;
  243. #sleep-cells = <1>;
  244. fsl,liodn-bits = <12>;
  245. };
  246. pins: global-utilities@e0e00 {
  247. compatible = "fsl,qoriq-pin-control-1.0";
  248. reg = <0xe0e00 0x200>;
  249. #sleep-cells = <2>;
  250. };
  251. clockgen: global-utilities@e1000 {
  252. compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
  253. reg = <0xe1000 0x1000>;
  254. clock-frequency = <0>;
  255. };
  256. rcpm: global-utilities@e2000 {
  257. compatible = "fsl,qoriq-rcpm-1.0";
  258. reg = <0xe2000 0x1000>;
  259. #sleep-cells = <1>;
  260. };
  261. sfp: sfp@e8000 {
  262. compatible = "fsl,p2041-sfp", "fsl,qoriq-sfp-1.0";
  263. reg = <0xe8000 0x1000>;
  264. };
  265. serdes: serdes@ea000 {
  266. compatible = "fsl,p2041-serdes";
  267. reg = <0xea000 0x1000>;
  268. };
  269. /include/ "qoriq-dma-0.dtsi"
  270. /include/ "qoriq-dma-1.dtsi"
  271. /include/ "qoriq-espi-0.dtsi"
  272. spi@110000 {
  273. fsl,espi-num-chipselects = <4>;
  274. };
  275. /include/ "qoriq-esdhc-0.dtsi"
  276. sdhc@114000 {
  277. sdhci,auto-cmd12;
  278. };
  279. /include/ "qoriq-i2c-0.dtsi"
  280. /include/ "qoriq-i2c-1.dtsi"
  281. /include/ "qoriq-duart-0.dtsi"
  282. /include/ "qoriq-duart-1.dtsi"
  283. /include/ "qoriq-gpio-0.dtsi"
  284. /include/ "qoriq-usb2-mph-0.dtsi"
  285. usb0: usb@210000 {
  286. phy_type = "utmi";
  287. port0;
  288. };
  289. /include/ "qoriq-usb2-dr-0.dtsi"
  290. usb1: usb@211000 {
  291. dr_mode = "host";
  292. phy_type = "utmi";
  293. };
  294. /include/ "qoriq-sata2-0.dtsi"
  295. /include/ "qoriq-sata2-1.dtsi"
  296. /include/ "qoriq-sec4.2-0.dtsi"
  297. };