malta-int.c 20 KB

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  1. /*
  2. * Carsten Langgaard, carstenl@mips.com
  3. * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
  4. * Copyright (C) 2001 Ralf Baechle
  5. *
  6. * This program is free software; you can distribute it and/or modify it
  7. * under the terms of the GNU General Public License (Version 2) as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  13. * for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along
  16. * with this program; if not, write to the Free Software Foundation, Inc.,
  17. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  18. *
  19. * Routines for generic manipulation of the interrupts found on the MIPS
  20. * Malta board.
  21. * The interrupt controller is located in the South Bridge a PIIX4 device
  22. * with two internal 82C95 interrupt controllers.
  23. */
  24. #include <linux/init.h>
  25. #include <linux/irq.h>
  26. #include <linux/sched.h>
  27. #include <linux/smp.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/io.h>
  30. #include <linux/kernel_stat.h>
  31. #include <linux/kernel.h>
  32. #include <linux/random.h>
  33. #include <asm/traps.h>
  34. #include <asm/i8259.h>
  35. #include <asm/irq_cpu.h>
  36. #include <asm/irq_regs.h>
  37. #include <asm/mips-boards/malta.h>
  38. #include <asm/mips-boards/maltaint.h>
  39. #include <asm/mips-boards/piix4.h>
  40. #include <asm/gt64120.h>
  41. #include <asm/mips-boards/generic.h>
  42. #include <asm/mips-boards/msc01_pci.h>
  43. #include <asm/msc01_ic.h>
  44. #include <asm/gic.h>
  45. #include <asm/gcmpregs.h>
  46. int gcmp_present = -1;
  47. int gic_present;
  48. static unsigned long _msc01_biu_base;
  49. static unsigned long _gcmp_base;
  50. static unsigned int ipi_map[NR_CPUS];
  51. static DEFINE_RAW_SPINLOCK(mips_irq_lock);
  52. static inline int mips_pcibios_iack(void)
  53. {
  54. int irq;
  55. /*
  56. * Determine highest priority pending interrupt by performing
  57. * a PCI Interrupt Acknowledge cycle.
  58. */
  59. switch (mips_revision_sconid) {
  60. case MIPS_REVISION_SCON_SOCIT:
  61. case MIPS_REVISION_SCON_ROCIT:
  62. case MIPS_REVISION_SCON_SOCITSC:
  63. case MIPS_REVISION_SCON_SOCITSCP:
  64. MSC_READ(MSC01_PCI_IACK, irq);
  65. irq &= 0xff;
  66. break;
  67. case MIPS_REVISION_SCON_GT64120:
  68. irq = GT_READ(GT_PCI0_IACK_OFS);
  69. irq &= 0xff;
  70. break;
  71. case MIPS_REVISION_SCON_BONITO:
  72. /* The following will generate a PCI IACK cycle on the
  73. * Bonito controller. It's a little bit kludgy, but it
  74. * was the easiest way to implement it in hardware at
  75. * the given time.
  76. */
  77. BONITO_PCIMAP_CFG = 0x20000;
  78. /* Flush Bonito register block */
  79. (void) BONITO_PCIMAP_CFG;
  80. iob(); /* sync */
  81. irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
  82. iob(); /* sync */
  83. irq &= 0xff;
  84. BONITO_PCIMAP_CFG = 0;
  85. break;
  86. default:
  87. printk(KERN_WARNING "Unknown system controller.\n");
  88. return -1;
  89. }
  90. return irq;
  91. }
  92. static inline int get_int(void)
  93. {
  94. unsigned long flags;
  95. int irq;
  96. raw_spin_lock_irqsave(&mips_irq_lock, flags);
  97. irq = mips_pcibios_iack();
  98. /*
  99. * The only way we can decide if an interrupt is spurious
  100. * is by checking the 8259 registers. This needs a spinlock
  101. * on an SMP system, so leave it up to the generic code...
  102. */
  103. raw_spin_unlock_irqrestore(&mips_irq_lock, flags);
  104. return irq;
  105. }
  106. static void malta_hw0_irqdispatch(void)
  107. {
  108. int irq;
  109. irq = get_int();
  110. if (irq < 0) {
  111. /* interrupt has already been cleared */
  112. return;
  113. }
  114. do_IRQ(MALTA_INT_BASE + irq);
  115. }
  116. static void malta_ipi_irqdispatch(void)
  117. {
  118. int irq;
  119. irq = gic_get_int();
  120. if (irq < 0)
  121. return; /* interrupt has already been cleared */
  122. do_IRQ(MIPS_GIC_IRQ_BASE + irq);
  123. }
  124. static void corehi_irqdispatch(void)
  125. {
  126. unsigned int intedge, intsteer, pcicmd, pcibadaddr;
  127. unsigned int pcimstat, intisr, inten, intpol;
  128. unsigned int intrcause, datalo, datahi;
  129. struct pt_regs *regs = get_irq_regs();
  130. printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
  131. printk(KERN_EMERG "epc : %08lx\nStatus: %08lx\n"
  132. "Cause : %08lx\nbadVaddr : %08lx\n",
  133. regs->cp0_epc, regs->cp0_status,
  134. regs->cp0_cause, regs->cp0_badvaddr);
  135. /* Read all the registers and then print them as there is a
  136. problem with interspersed printk's upsetting the Bonito controller.
  137. Do it for the others too.
  138. */
  139. switch (mips_revision_sconid) {
  140. case MIPS_REVISION_SCON_SOCIT:
  141. case MIPS_REVISION_SCON_ROCIT:
  142. case MIPS_REVISION_SCON_SOCITSC:
  143. case MIPS_REVISION_SCON_SOCITSCP:
  144. ll_msc_irq();
  145. break;
  146. case MIPS_REVISION_SCON_GT64120:
  147. intrcause = GT_READ(GT_INTRCAUSE_OFS);
  148. datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
  149. datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
  150. printk(KERN_EMERG "GT_INTRCAUSE = %08x\n", intrcause);
  151. printk(KERN_EMERG "GT_CPUERR_ADDR = %02x%08x\n",
  152. datahi, datalo);
  153. break;
  154. case MIPS_REVISION_SCON_BONITO:
  155. pcibadaddr = BONITO_PCIBADADDR;
  156. pcimstat = BONITO_PCIMSTAT;
  157. intisr = BONITO_INTISR;
  158. inten = BONITO_INTEN;
  159. intpol = BONITO_INTPOL;
  160. intedge = BONITO_INTEDGE;
  161. intsteer = BONITO_INTSTEER;
  162. pcicmd = BONITO_PCICMD;
  163. printk(KERN_EMERG "BONITO_INTISR = %08x\n", intisr);
  164. printk(KERN_EMERG "BONITO_INTEN = %08x\n", inten);
  165. printk(KERN_EMERG "BONITO_INTPOL = %08x\n", intpol);
  166. printk(KERN_EMERG "BONITO_INTEDGE = %08x\n", intedge);
  167. printk(KERN_EMERG "BONITO_INTSTEER = %08x\n", intsteer);
  168. printk(KERN_EMERG "BONITO_PCICMD = %08x\n", pcicmd);
  169. printk(KERN_EMERG "BONITO_PCIBADADDR = %08x\n", pcibadaddr);
  170. printk(KERN_EMERG "BONITO_PCIMSTAT = %08x\n", pcimstat);
  171. break;
  172. }
  173. die("CoreHi interrupt", regs);
  174. }
  175. static inline int clz(unsigned long x)
  176. {
  177. __asm__(
  178. " .set push \n"
  179. " .set mips32 \n"
  180. " clz %0, %1 \n"
  181. " .set pop \n"
  182. : "=r" (x)
  183. : "r" (x));
  184. return x;
  185. }
  186. /*
  187. * Version of ffs that only looks at bits 12..15.
  188. */
  189. static inline unsigned int irq_ffs(unsigned int pending)
  190. {
  191. #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
  192. return -clz(pending) + 31 - CAUSEB_IP;
  193. #else
  194. unsigned int a0 = 7;
  195. unsigned int t0;
  196. t0 = pending & 0xf000;
  197. t0 = t0 < 1;
  198. t0 = t0 << 2;
  199. a0 = a0 - t0;
  200. pending = pending << t0;
  201. t0 = pending & 0xc000;
  202. t0 = t0 < 1;
  203. t0 = t0 << 1;
  204. a0 = a0 - t0;
  205. pending = pending << t0;
  206. t0 = pending & 0x8000;
  207. t0 = t0 < 1;
  208. /* t0 = t0 << 2; */
  209. a0 = a0 - t0;
  210. /* pending = pending << t0; */
  211. return a0;
  212. #endif
  213. }
  214. /*
  215. * IRQs on the Malta board look basically (barring software IRQs which we
  216. * don't use at all and all external interrupt sources are combined together
  217. * on hardware interrupt 0 (MIPS IRQ 2)) like:
  218. *
  219. * MIPS IRQ Source
  220. * -------- ------
  221. * 0 Software (ignored)
  222. * 1 Software (ignored)
  223. * 2 Combined hardware interrupt (hw0)
  224. * 3 Hardware (ignored)
  225. * 4 Hardware (ignored)
  226. * 5 Hardware (ignored)
  227. * 6 Hardware (ignored)
  228. * 7 R4k timer (what we use)
  229. *
  230. * We handle the IRQ according to _our_ priority which is:
  231. *
  232. * Highest ---- R4k Timer
  233. * Lowest ---- Combined hardware interrupt
  234. *
  235. * then we just return, if multiple IRQs are pending then we will just take
  236. * another exception, big deal.
  237. */
  238. asmlinkage void plat_irq_dispatch(void)
  239. {
  240. unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
  241. int irq;
  242. irq = irq_ffs(pending);
  243. if (irq == MIPSCPU_INT_I8259A)
  244. malta_hw0_irqdispatch();
  245. else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()]))
  246. malta_ipi_irqdispatch();
  247. else if (irq >= 0)
  248. do_IRQ(MIPS_CPU_IRQ_BASE + irq);
  249. else
  250. spurious_interrupt();
  251. }
  252. #ifdef CONFIG_MIPS_MT_SMP
  253. #define GIC_MIPS_CPU_IPI_RESCHED_IRQ 3
  254. #define GIC_MIPS_CPU_IPI_CALL_IRQ 4
  255. #define MIPS_CPU_IPI_RESCHED_IRQ 0 /* SW int 0 for resched */
  256. #define C_RESCHED C_SW0
  257. #define MIPS_CPU_IPI_CALL_IRQ 1 /* SW int 1 for resched */
  258. #define C_CALL C_SW1
  259. static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
  260. static void ipi_resched_dispatch(void)
  261. {
  262. do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
  263. }
  264. static void ipi_call_dispatch(void)
  265. {
  266. do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
  267. }
  268. static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
  269. {
  270. scheduler_ipi();
  271. return IRQ_HANDLED;
  272. }
  273. static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
  274. {
  275. smp_call_function_interrupt();
  276. return IRQ_HANDLED;
  277. }
  278. static struct irqaction irq_resched = {
  279. .handler = ipi_resched_interrupt,
  280. .flags = IRQF_PERCPU,
  281. .name = "IPI_resched"
  282. };
  283. static struct irqaction irq_call = {
  284. .handler = ipi_call_interrupt,
  285. .flags = IRQF_PERCPU,
  286. .name = "IPI_call"
  287. };
  288. #endif /* CONFIG_MIPS_MT_SMP */
  289. static int gic_resched_int_base;
  290. static int gic_call_int_base;
  291. #define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
  292. #define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
  293. unsigned int plat_ipi_call_int_xlate(unsigned int cpu)
  294. {
  295. return GIC_CALL_INT(cpu);
  296. }
  297. unsigned int plat_ipi_resched_int_xlate(unsigned int cpu)
  298. {
  299. return GIC_RESCHED_INT(cpu);
  300. }
  301. static struct irqaction i8259irq = {
  302. .handler = no_action,
  303. .name = "XT-PIC cascade",
  304. .flags = IRQF_NO_THREAD,
  305. };
  306. static struct irqaction corehi_irqaction = {
  307. .handler = no_action,
  308. .name = "CoreHi",
  309. .flags = IRQF_NO_THREAD,
  310. };
  311. static msc_irqmap_t __initdata msc_irqmap[] = {
  312. {MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
  313. {MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
  314. };
  315. static int __initdata msc_nr_irqs = ARRAY_SIZE(msc_irqmap);
  316. static msc_irqmap_t __initdata msc_eicirqmap[] = {
  317. {MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
  318. {MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
  319. {MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
  320. {MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
  321. {MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
  322. {MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
  323. {MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
  324. {MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
  325. {MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
  326. {MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
  327. };
  328. static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
  329. /*
  330. * This GIC specific tabular array defines the association between External
  331. * Interrupts and CPUs/Core Interrupts. The nature of the External
  332. * Interrupts is also defined here - polarity/trigger.
  333. */
  334. #define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK
  335. #define X GIC_UNUSED
  336. static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
  337. { X, X, X, X, 0 },
  338. { X, X, X, X, 0 },
  339. { X, X, X, X, 0 },
  340. { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
  341. { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
  342. { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
  343. { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
  344. { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
  345. { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
  346. { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
  347. { X, X, X, X, 0 },
  348. { X, X, X, X, 0 },
  349. { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
  350. { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
  351. { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
  352. { X, X, X, X, 0 },
  353. /* The remainder of this table is initialised by fill_ipi_map */
  354. };
  355. #undef X
  356. /*
  357. * GCMP needs to be detected before any SMP initialisation
  358. */
  359. int __init gcmp_probe(unsigned long addr, unsigned long size)
  360. {
  361. if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) {
  362. gcmp_present = 0;
  363. return gcmp_present;
  364. }
  365. if (gcmp_present >= 0)
  366. return gcmp_present;
  367. _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
  368. _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
  369. gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR;
  370. if (gcmp_present)
  371. pr_debug("GCMP present\n");
  372. return gcmp_present;
  373. }
  374. /* Return the number of IOCU's present */
  375. int __init gcmp_niocu(void)
  376. {
  377. return gcmp_present ?
  378. (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF :
  379. 0;
  380. }
  381. /* Set GCMP region attributes */
  382. void __init gcmp_setregion(int region, unsigned long base,
  383. unsigned long mask, int type)
  384. {
  385. GCMPGCBn(CMxBASE, region) = base;
  386. GCMPGCBn(CMxMASK, region) = mask | type;
  387. }
  388. #if defined(CONFIG_MIPS_MT_SMP)
  389. static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin)
  390. {
  391. int intr = baseintr + cpu;
  392. gic_intr_map[intr].cpunum = cpu;
  393. gic_intr_map[intr].pin = cpupin;
  394. gic_intr_map[intr].polarity = GIC_POL_POS;
  395. gic_intr_map[intr].trigtype = GIC_TRIG_EDGE;
  396. gic_intr_map[intr].flags = GIC_FLAG_IPI;
  397. ipi_map[cpu] |= (1 << (cpupin + 2));
  398. }
  399. static void __init fill_ipi_map(void)
  400. {
  401. int cpu;
  402. for (cpu = 0; cpu < NR_CPUS; cpu++) {
  403. fill_ipi_map1(gic_resched_int_base, cpu, GIC_CPU_INT1);
  404. fill_ipi_map1(gic_call_int_base, cpu, GIC_CPU_INT2);
  405. }
  406. }
  407. #endif
  408. void __init arch_init_ipiirq(int irq, struct irqaction *action)
  409. {
  410. setup_irq(irq, action);
  411. irq_set_handler(irq, handle_percpu_irq);
  412. }
  413. void __init arch_init_irq(void)
  414. {
  415. init_i8259_irqs();
  416. if (!cpu_has_veic)
  417. mips_cpu_irq_init();
  418. if (gcmp_present) {
  419. GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
  420. gic_present = 1;
  421. } else {
  422. if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) {
  423. _msc01_biu_base = (unsigned long)
  424. ioremap_nocache(MSC01_BIU_REG_BASE,
  425. MSC01_BIU_ADDRSPACE_SZ);
  426. gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
  427. MSC01_SC_CFG_GICPRES_MSK) >>
  428. MSC01_SC_CFG_GICPRES_SHF;
  429. }
  430. }
  431. if (gic_present)
  432. pr_debug("GIC present\n");
  433. switch (mips_revision_sconid) {
  434. case MIPS_REVISION_SCON_SOCIT:
  435. case MIPS_REVISION_SCON_ROCIT:
  436. if (cpu_has_veic)
  437. init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
  438. MSC01E_INT_BASE, msc_eicirqmap,
  439. msc_nr_eicirqs);
  440. else
  441. init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
  442. MSC01C_INT_BASE, msc_irqmap,
  443. msc_nr_irqs);
  444. break;
  445. case MIPS_REVISION_SCON_SOCITSC:
  446. case MIPS_REVISION_SCON_SOCITSCP:
  447. if (cpu_has_veic)
  448. init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
  449. MSC01E_INT_BASE, msc_eicirqmap,
  450. msc_nr_eicirqs);
  451. else
  452. init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
  453. MSC01C_INT_BASE, msc_irqmap,
  454. msc_nr_irqs);
  455. }
  456. if (cpu_has_veic) {
  457. set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
  458. set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
  459. setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
  460. setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
  461. } else if (cpu_has_vint) {
  462. set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
  463. set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
  464. #ifdef CONFIG_MIPS_MT_SMTC
  465. setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
  466. (0x100 << MIPSCPU_INT_I8259A));
  467. setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
  468. &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
  469. /*
  470. * Temporary hack to ensure that the subsidiary device
  471. * interrupts coing in via the i8259A, but associated
  472. * with low IRQ numbers, will restore the Status.IM
  473. * value associated with the i8259A.
  474. */
  475. {
  476. int i;
  477. for (i = 0; i < 16; i++)
  478. irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
  479. }
  480. #else /* Not SMTC */
  481. setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
  482. setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
  483. &corehi_irqaction);
  484. #endif /* CONFIG_MIPS_MT_SMTC */
  485. } else {
  486. setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
  487. setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
  488. &corehi_irqaction);
  489. }
  490. if (gic_present) {
  491. /* FIXME */
  492. int i;
  493. #if defined(CONFIG_MIPS_MT_SMP)
  494. gic_call_int_base = GIC_NUM_INTRS - NR_CPUS;
  495. gic_resched_int_base = gic_call_int_base - NR_CPUS;
  496. fill_ipi_map();
  497. #endif
  498. gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
  499. ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
  500. if (!gcmp_present) {
  501. /* Enable the GIC */
  502. i = REG(_msc01_biu_base, MSC01_SC_CFG);
  503. REG(_msc01_biu_base, MSC01_SC_CFG) =
  504. (i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
  505. pr_debug("GIC Enabled\n");
  506. }
  507. #if defined(CONFIG_MIPS_MT_SMP)
  508. /* set up ipi interrupts */
  509. if (cpu_has_vint) {
  510. set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);
  511. set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch);
  512. }
  513. /* Argh.. this really needs sorting out.. */
  514. printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status());
  515. write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4);
  516. printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
  517. write_c0_status(0x1100dc00);
  518. printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
  519. for (i = 0; i < NR_CPUS; i++) {
  520. arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
  521. GIC_RESCHED_INT(i), &irq_resched);
  522. arch_init_ipiirq(MIPS_GIC_IRQ_BASE +
  523. GIC_CALL_INT(i), &irq_call);
  524. }
  525. #endif
  526. } else {
  527. #if defined(CONFIG_MIPS_MT_SMP)
  528. /* set up ipi interrupts */
  529. if (cpu_has_veic) {
  530. set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
  531. set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
  532. cpu_ipi_resched_irq = MSC01E_INT_SW0;
  533. cpu_ipi_call_irq = MSC01E_INT_SW1;
  534. } else {
  535. if (cpu_has_vint) {
  536. set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
  537. set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
  538. }
  539. cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
  540. cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
  541. }
  542. arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched);
  543. arch_init_ipiirq(cpu_ipi_call_irq, &irq_call);
  544. #endif
  545. }
  546. }
  547. void malta_be_init(void)
  548. {
  549. if (gcmp_present) {
  550. /* Could change CM error mask register */
  551. }
  552. }
  553. static char *tr[8] = {
  554. "mem", "gcr", "gic", "mmio",
  555. "0x04", "0x05", "0x06", "0x07"
  556. };
  557. static char *mcmd[32] = {
  558. [0x00] = "0x00",
  559. [0x01] = "Legacy Write",
  560. [0x02] = "Legacy Read",
  561. [0x03] = "0x03",
  562. [0x04] = "0x04",
  563. [0x05] = "0x05",
  564. [0x06] = "0x06",
  565. [0x07] = "0x07",
  566. [0x08] = "Coherent Read Own",
  567. [0x09] = "Coherent Read Share",
  568. [0x0a] = "Coherent Read Discard",
  569. [0x0b] = "Coherent Ready Share Always",
  570. [0x0c] = "Coherent Upgrade",
  571. [0x0d] = "Coherent Writeback",
  572. [0x0e] = "0x0e",
  573. [0x0f] = "0x0f",
  574. [0x10] = "Coherent Copyback",
  575. [0x11] = "Coherent Copyback Invalidate",
  576. [0x12] = "Coherent Invalidate",
  577. [0x13] = "Coherent Write Invalidate",
  578. [0x14] = "Coherent Completion Sync",
  579. [0x15] = "0x15",
  580. [0x16] = "0x16",
  581. [0x17] = "0x17",
  582. [0x18] = "0x18",
  583. [0x19] = "0x19",
  584. [0x1a] = "0x1a",
  585. [0x1b] = "0x1b",
  586. [0x1c] = "0x1c",
  587. [0x1d] = "0x1d",
  588. [0x1e] = "0x1e",
  589. [0x1f] = "0x1f"
  590. };
  591. static char *core[8] = {
  592. "Invalid/OK", "Invalid/Data",
  593. "Shared/OK", "Shared/Data",
  594. "Modified/OK", "Modified/Data",
  595. "Exclusive/OK", "Exclusive/Data"
  596. };
  597. static char *causes[32] = {
  598. "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
  599. "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
  600. "0x08", "0x09", "0x0a", "0x0b",
  601. "0x0c", "0x0d", "0x0e", "0x0f",
  602. "0x10", "0x11", "0x12", "0x13",
  603. "0x14", "0x15", "0x16", "INTVN_WR_ERR",
  604. "INTVN_RD_ERR", "0x19", "0x1a", "0x1b",
  605. "0x1c", "0x1d", "0x1e", "0x1f"
  606. };
  607. int malta_be_handler(struct pt_regs *regs, int is_fixup)
  608. {
  609. /* This duplicates the handling in do_be which seems wrong */
  610. int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
  611. if (gcmp_present) {
  612. unsigned long cm_error = GCMPGCB(GCMEC);
  613. unsigned long cm_addr = GCMPGCB(GCMEA);
  614. unsigned long cm_other = GCMPGCB(GCMEO);
  615. unsigned long cause, ocause;
  616. char buf[256];
  617. cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK);
  618. if (cause != 0) {
  619. cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF;
  620. if (cause < 16) {
  621. unsigned long cca_bits = (cm_error >> 15) & 7;
  622. unsigned long tr_bits = (cm_error >> 12) & 7;
  623. unsigned long mcmd_bits = (cm_error >> 7) & 0x1f;
  624. unsigned long stag_bits = (cm_error >> 3) & 15;
  625. unsigned long sport_bits = (cm_error >> 0) & 7;
  626. snprintf(buf, sizeof(buf),
  627. "CCA=%lu TR=%s MCmd=%s STag=%lu "
  628. "SPort=%lu\n",
  629. cca_bits, tr[tr_bits], mcmd[mcmd_bits],
  630. stag_bits, sport_bits);
  631. } else {
  632. /* glob state & sresp together */
  633. unsigned long c3_bits = (cm_error >> 18) & 7;
  634. unsigned long c2_bits = (cm_error >> 15) & 7;
  635. unsigned long c1_bits = (cm_error >> 12) & 7;
  636. unsigned long c0_bits = (cm_error >> 9) & 7;
  637. unsigned long sc_bit = (cm_error >> 8) & 1;
  638. unsigned long mcmd_bits = (cm_error >> 3) & 0x1f;
  639. unsigned long sport_bits = (cm_error >> 0) & 7;
  640. snprintf(buf, sizeof(buf),
  641. "C3=%s C2=%s C1=%s C0=%s SC=%s "
  642. "MCmd=%s SPort=%lu\n",
  643. core[c3_bits], core[c2_bits],
  644. core[c1_bits], core[c0_bits],
  645. sc_bit ? "True" : "False",
  646. mcmd[mcmd_bits], sport_bits);
  647. }
  648. ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >>
  649. GCMP_GCB_GMEO_ERROR_2ND_SHF;
  650. printk("CM_ERROR=%08lx %s <%s>\n", cm_error,
  651. causes[cause], buf);
  652. printk("CM_ADDR =%08lx\n", cm_addr);
  653. printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
  654. /* reprime cause register */
  655. GCMPGCB(GCMEC) = 0;
  656. }
  657. }
  658. return retval;
  659. }