ezkit.c 22 KB

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  1. /*
  2. * Copyright 2004-2009 Analog Devices Inc.
  3. * 2005 National ICT Australia (NICTA)
  4. * Aidan Williams <aidan@nicta.com.au>
  5. *
  6. * Licensed under the GPL-2
  7. */
  8. #include <linux/device.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/mtd/mtd.h>
  11. #include <linux/mtd/physmap.h>
  12. #include <linux/mtd/partitions.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/spi/flash.h>
  15. #include <linux/irq.h>
  16. #include <linux/interrupt.h>
  17. #include <asm/bfin5xx_spi.h>
  18. #include <asm/dma.h>
  19. #include <asm/gpio.h>
  20. #include <asm/nand.h>
  21. #include <asm/portmux.h>
  22. #include <asm/dpmc.h>
  23. #include <linux/input.h>
  24. /*
  25. * Name the Board for the /proc/cpuinfo
  26. */
  27. const char bfin_board_name[] = "ADI BF538-EZKIT";
  28. /*
  29. * Driver needs to know address, irq and flag pin.
  30. */
  31. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  32. static struct platform_device rtc_device = {
  33. .name = "rtc-bfin",
  34. .id = -1,
  35. };
  36. #endif
  37. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  38. #ifdef CONFIG_SERIAL_BFIN_UART0
  39. static struct resource bfin_uart0_resources[] = {
  40. {
  41. .start = UART0_THR,
  42. .end = UART0_GCTL+2,
  43. .flags = IORESOURCE_MEM,
  44. },
  45. {
  46. .start = IRQ_UART0_TX,
  47. .end = IRQ_UART0_TX,
  48. .flags = IORESOURCE_IRQ,
  49. },
  50. {
  51. .start = IRQ_UART0_RX,
  52. .end = IRQ_UART0_RX,
  53. .flags = IORESOURCE_IRQ,
  54. },
  55. {
  56. .start = IRQ_UART0_ERROR,
  57. .end = IRQ_UART0_ERROR,
  58. .flags = IORESOURCE_IRQ,
  59. },
  60. {
  61. .start = CH_UART0_TX,
  62. .end = CH_UART0_TX,
  63. .flags = IORESOURCE_DMA,
  64. },
  65. {
  66. .start = CH_UART0_RX,
  67. .end = CH_UART0_RX,
  68. .flags = IORESOURCE_DMA,
  69. },
  70. #ifdef CONFIG_BFIN_UART0_CTSRTS
  71. { /* CTS pin */
  72. .start = GPIO_PG7,
  73. .end = GPIO_PG7,
  74. .flags = IORESOURCE_IO,
  75. },
  76. { /* RTS pin */
  77. .start = GPIO_PG6,
  78. .end = GPIO_PG6,
  79. .flags = IORESOURCE_IO,
  80. },
  81. #endif
  82. };
  83. static unsigned short bfin_uart0_peripherals[] = {
  84. P_UART0_TX, P_UART0_RX, 0
  85. };
  86. static struct platform_device bfin_uart0_device = {
  87. .name = "bfin-uart",
  88. .id = 0,
  89. .num_resources = ARRAY_SIZE(bfin_uart0_resources),
  90. .resource = bfin_uart0_resources,
  91. .dev = {
  92. .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
  93. },
  94. };
  95. #endif
  96. #ifdef CONFIG_SERIAL_BFIN_UART1
  97. static struct resource bfin_uart1_resources[] = {
  98. {
  99. .start = UART1_THR,
  100. .end = UART1_GCTL+2,
  101. .flags = IORESOURCE_MEM,
  102. },
  103. {
  104. .start = IRQ_UART1_TX,
  105. .end = IRQ_UART1_TX,
  106. .flags = IORESOURCE_IRQ,
  107. },
  108. {
  109. .start = IRQ_UART1_RX,
  110. .end = IRQ_UART1_RX,
  111. .flags = IORESOURCE_IRQ,
  112. },
  113. {
  114. .start = IRQ_UART1_ERROR,
  115. .end = IRQ_UART1_ERROR,
  116. .flags = IORESOURCE_IRQ,
  117. },
  118. {
  119. .start = CH_UART1_TX,
  120. .end = CH_UART1_TX,
  121. .flags = IORESOURCE_DMA,
  122. },
  123. {
  124. .start = CH_UART1_RX,
  125. .end = CH_UART1_RX,
  126. .flags = IORESOURCE_DMA,
  127. },
  128. };
  129. static unsigned short bfin_uart1_peripherals[] = {
  130. P_UART1_TX, P_UART1_RX, 0
  131. };
  132. static struct platform_device bfin_uart1_device = {
  133. .name = "bfin-uart",
  134. .id = 1,
  135. .num_resources = ARRAY_SIZE(bfin_uart1_resources),
  136. .resource = bfin_uart1_resources,
  137. .dev = {
  138. .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
  139. },
  140. };
  141. #endif
  142. #ifdef CONFIG_SERIAL_BFIN_UART2
  143. static struct resource bfin_uart2_resources[] = {
  144. {
  145. .start = UART2_THR,
  146. .end = UART2_GCTL+2,
  147. .flags = IORESOURCE_MEM,
  148. },
  149. {
  150. .start = IRQ_UART2_TX,
  151. .end = IRQ_UART2_TX,
  152. .flags = IORESOURCE_IRQ,
  153. },
  154. {
  155. .start = IRQ_UART2_RX,
  156. .end = IRQ_UART2_RX,
  157. .flags = IORESOURCE_IRQ,
  158. },
  159. {
  160. .start = IRQ_UART2_ERROR,
  161. .end = IRQ_UART2_ERROR,
  162. .flags = IORESOURCE_IRQ,
  163. },
  164. {
  165. .start = CH_UART2_TX,
  166. .end = CH_UART2_TX,
  167. .flags = IORESOURCE_DMA,
  168. },
  169. {
  170. .start = CH_UART2_RX,
  171. .end = CH_UART2_RX,
  172. .flags = IORESOURCE_DMA,
  173. },
  174. };
  175. static unsigned short bfin_uart2_peripherals[] = {
  176. P_UART2_TX, P_UART2_RX, 0
  177. };
  178. static struct platform_device bfin_uart2_device = {
  179. .name = "bfin-uart",
  180. .id = 2,
  181. .num_resources = ARRAY_SIZE(bfin_uart2_resources),
  182. .resource = bfin_uart2_resources,
  183. .dev = {
  184. .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
  185. },
  186. };
  187. #endif
  188. #endif
  189. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  190. #ifdef CONFIG_BFIN_SIR0
  191. static struct resource bfin_sir0_resources[] = {
  192. {
  193. .start = 0xFFC00400,
  194. .end = 0xFFC004FF,
  195. .flags = IORESOURCE_MEM,
  196. },
  197. {
  198. .start = IRQ_UART0_RX,
  199. .end = IRQ_UART0_RX+1,
  200. .flags = IORESOURCE_IRQ,
  201. },
  202. {
  203. .start = CH_UART0_RX,
  204. .end = CH_UART0_RX+1,
  205. .flags = IORESOURCE_DMA,
  206. },
  207. };
  208. static struct platform_device bfin_sir0_device = {
  209. .name = "bfin_sir",
  210. .id = 0,
  211. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  212. .resource = bfin_sir0_resources,
  213. };
  214. #endif
  215. #ifdef CONFIG_BFIN_SIR1
  216. static struct resource bfin_sir1_resources[] = {
  217. {
  218. .start = 0xFFC02000,
  219. .end = 0xFFC020FF,
  220. .flags = IORESOURCE_MEM,
  221. },
  222. {
  223. .start = IRQ_UART1_RX,
  224. .end = IRQ_UART1_RX+1,
  225. .flags = IORESOURCE_IRQ,
  226. },
  227. {
  228. .start = CH_UART1_RX,
  229. .end = CH_UART1_RX+1,
  230. .flags = IORESOURCE_DMA,
  231. },
  232. };
  233. static struct platform_device bfin_sir1_device = {
  234. .name = "bfin_sir",
  235. .id = 1,
  236. .num_resources = ARRAY_SIZE(bfin_sir1_resources),
  237. .resource = bfin_sir1_resources,
  238. };
  239. #endif
  240. #ifdef CONFIG_BFIN_SIR2
  241. static struct resource bfin_sir2_resources[] = {
  242. {
  243. .start = 0xFFC02100,
  244. .end = 0xFFC021FF,
  245. .flags = IORESOURCE_MEM,
  246. },
  247. {
  248. .start = IRQ_UART2_RX,
  249. .end = IRQ_UART2_RX+1,
  250. .flags = IORESOURCE_IRQ,
  251. },
  252. {
  253. .start = CH_UART2_RX,
  254. .end = CH_UART2_RX+1,
  255. .flags = IORESOURCE_DMA,
  256. },
  257. };
  258. static struct platform_device bfin_sir2_device = {
  259. .name = "bfin_sir",
  260. .id = 2,
  261. .num_resources = ARRAY_SIZE(bfin_sir2_resources),
  262. .resource = bfin_sir2_resources,
  263. };
  264. #endif
  265. #endif
  266. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  267. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  268. static struct resource bfin_sport0_uart_resources[] = {
  269. {
  270. .start = SPORT0_TCR1,
  271. .end = SPORT0_MRCS3+4,
  272. .flags = IORESOURCE_MEM,
  273. },
  274. {
  275. .start = IRQ_SPORT0_RX,
  276. .end = IRQ_SPORT0_RX+1,
  277. .flags = IORESOURCE_IRQ,
  278. },
  279. {
  280. .start = IRQ_SPORT0_ERROR,
  281. .end = IRQ_SPORT0_ERROR,
  282. .flags = IORESOURCE_IRQ,
  283. },
  284. };
  285. static unsigned short bfin_sport0_peripherals[] = {
  286. P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
  287. P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
  288. };
  289. static struct platform_device bfin_sport0_uart_device = {
  290. .name = "bfin-sport-uart",
  291. .id = 0,
  292. .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
  293. .resource = bfin_sport0_uart_resources,
  294. .dev = {
  295. .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
  296. },
  297. };
  298. #endif
  299. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  300. static struct resource bfin_sport1_uart_resources[] = {
  301. {
  302. .start = SPORT1_TCR1,
  303. .end = SPORT1_MRCS3+4,
  304. .flags = IORESOURCE_MEM,
  305. },
  306. {
  307. .start = IRQ_SPORT1_RX,
  308. .end = IRQ_SPORT1_RX+1,
  309. .flags = IORESOURCE_IRQ,
  310. },
  311. {
  312. .start = IRQ_SPORT1_ERROR,
  313. .end = IRQ_SPORT1_ERROR,
  314. .flags = IORESOURCE_IRQ,
  315. },
  316. };
  317. static unsigned short bfin_sport1_peripherals[] = {
  318. P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
  319. P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
  320. };
  321. static struct platform_device bfin_sport1_uart_device = {
  322. .name = "bfin-sport-uart",
  323. .id = 1,
  324. .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
  325. .resource = bfin_sport1_uart_resources,
  326. .dev = {
  327. .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
  328. },
  329. };
  330. #endif
  331. #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
  332. static struct resource bfin_sport2_uart_resources[] = {
  333. {
  334. .start = SPORT2_TCR1,
  335. .end = SPORT2_MRCS3+4,
  336. .flags = IORESOURCE_MEM,
  337. },
  338. {
  339. .start = IRQ_SPORT2_RX,
  340. .end = IRQ_SPORT2_RX+1,
  341. .flags = IORESOURCE_IRQ,
  342. },
  343. {
  344. .start = IRQ_SPORT2_ERROR,
  345. .end = IRQ_SPORT2_ERROR,
  346. .flags = IORESOURCE_IRQ,
  347. },
  348. };
  349. static unsigned short bfin_sport2_peripherals[] = {
  350. P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
  351. P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0
  352. };
  353. static struct platform_device bfin_sport2_uart_device = {
  354. .name = "bfin-sport-uart",
  355. .id = 2,
  356. .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources),
  357. .resource = bfin_sport2_uart_resources,
  358. .dev = {
  359. .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
  360. },
  361. };
  362. #endif
  363. #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
  364. static struct resource bfin_sport3_uart_resources[] = {
  365. {
  366. .start = SPORT3_TCR1,
  367. .end = SPORT3_MRCS3+4,
  368. .flags = IORESOURCE_MEM,
  369. },
  370. {
  371. .start = IRQ_SPORT3_RX,
  372. .end = IRQ_SPORT3_RX+1,
  373. .flags = IORESOURCE_IRQ,
  374. },
  375. {
  376. .start = IRQ_SPORT3_ERROR,
  377. .end = IRQ_SPORT3_ERROR,
  378. .flags = IORESOURCE_IRQ,
  379. },
  380. };
  381. static unsigned short bfin_sport3_peripherals[] = {
  382. P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
  383. P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0
  384. };
  385. static struct platform_device bfin_sport3_uart_device = {
  386. .name = "bfin-sport-uart",
  387. .id = 3,
  388. .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources),
  389. .resource = bfin_sport3_uart_resources,
  390. .dev = {
  391. .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
  392. },
  393. };
  394. #endif
  395. #endif
  396. #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
  397. static unsigned short bfin_can_peripherals[] = {
  398. P_CAN0_RX, P_CAN0_TX, 0
  399. };
  400. static struct resource bfin_can_resources[] = {
  401. {
  402. .start = 0xFFC02A00,
  403. .end = 0xFFC02FFF,
  404. .flags = IORESOURCE_MEM,
  405. },
  406. {
  407. .start = IRQ_CAN_RX,
  408. .end = IRQ_CAN_RX,
  409. .flags = IORESOURCE_IRQ,
  410. },
  411. {
  412. .start = IRQ_CAN_TX,
  413. .end = IRQ_CAN_TX,
  414. .flags = IORESOURCE_IRQ,
  415. },
  416. {
  417. .start = IRQ_CAN_ERROR,
  418. .end = IRQ_CAN_ERROR,
  419. .flags = IORESOURCE_IRQ,
  420. },
  421. };
  422. static struct platform_device bfin_can_device = {
  423. .name = "bfin_can",
  424. .num_resources = ARRAY_SIZE(bfin_can_resources),
  425. .resource = bfin_can_resources,
  426. .dev = {
  427. .platform_data = &bfin_can_peripherals, /* Passed to driver */
  428. },
  429. };
  430. #endif
  431. /*
  432. * USB-LAN EzExtender board
  433. * Driver needs to know address, irq and flag pin.
  434. */
  435. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  436. #include <linux/smc91x.h>
  437. static struct smc91x_platdata smc91x_info = {
  438. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  439. .leda = RPC_LED_100_10,
  440. .ledb = RPC_LED_TX_RX,
  441. };
  442. static struct resource smc91x_resources[] = {
  443. {
  444. .name = "smc91x-regs",
  445. .start = 0x20310300,
  446. .end = 0x20310300 + 16,
  447. .flags = IORESOURCE_MEM,
  448. }, {
  449. .start = IRQ_PF0,
  450. .end = IRQ_PF0,
  451. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  452. },
  453. };
  454. static struct platform_device smc91x_device = {
  455. .name = "smc91x",
  456. .id = 0,
  457. .num_resources = ARRAY_SIZE(smc91x_resources),
  458. .resource = smc91x_resources,
  459. .dev = {
  460. .platform_data = &smc91x_info,
  461. },
  462. };
  463. #endif
  464. #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
  465. /* all SPI peripherals info goes here */
  466. #if defined(CONFIG_MTD_M25P80) \
  467. || defined(CONFIG_MTD_M25P80_MODULE)
  468. /* SPI flash chip (m25p16) */
  469. static struct mtd_partition bfin_spi_flash_partitions[] = {
  470. {
  471. .name = "bootloader(spi)",
  472. .size = 0x00040000,
  473. .offset = 0,
  474. .mask_flags = MTD_CAP_ROM
  475. }, {
  476. .name = "linux kernel(spi)",
  477. .size = 0x1c0000,
  478. .offset = 0x40000
  479. }
  480. };
  481. static struct flash_platform_data bfin_spi_flash_data = {
  482. .name = "m25p80",
  483. .parts = bfin_spi_flash_partitions,
  484. .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
  485. .type = "m25p16",
  486. };
  487. static struct bfin5xx_spi_chip spi_flash_chip_info = {
  488. .enable_dma = 0, /* use dma transfer with this chip*/
  489. };
  490. #endif
  491. #if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
  492. #include <linux/spi/ad7879.h>
  493. static const struct ad7879_platform_data bfin_ad7879_ts_info = {
  494. .model = 7879, /* Model = AD7879 */
  495. .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
  496. .pressure_max = 10000,
  497. .pressure_min = 0,
  498. .first_conversion_delay = 3, /* wait 512us before do a first conversion */
  499. .acquisition_time = 1, /* 4us acquisition time per sample */
  500. .median = 2, /* do 8 measurements */
  501. .averaging = 1, /* take the average of 4 middle samples */
  502. .pen_down_acc_interval = 255, /* 9.4 ms */
  503. .gpio_export = 1, /* Export GPIO to gpiolib */
  504. .gpio_base = -1, /* Dynamic allocation */
  505. };
  506. #endif
  507. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  508. #include <asm/bfin-lq035q1.h>
  509. static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
  510. .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
  511. .ppi_mode = USE_RGB565_16_BIT_PPI,
  512. .use_bl = 0, /* let something else control the LCD Blacklight */
  513. .gpio_bl = GPIO_PF7,
  514. };
  515. static struct resource bfin_lq035q1_resources[] = {
  516. {
  517. .start = IRQ_PPI_ERROR,
  518. .end = IRQ_PPI_ERROR,
  519. .flags = IORESOURCE_IRQ,
  520. },
  521. };
  522. static struct platform_device bfin_lq035q1_device = {
  523. .name = "bfin-lq035q1",
  524. .id = -1,
  525. .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
  526. .resource = bfin_lq035q1_resources,
  527. .dev = {
  528. .platform_data = &bfin_lq035q1_data,
  529. },
  530. };
  531. #endif
  532. static struct spi_board_info bf538_spi_board_info[] __initdata = {
  533. #if defined(CONFIG_MTD_M25P80) \
  534. || defined(CONFIG_MTD_M25P80_MODULE)
  535. {
  536. /* the modalias must be the same as spi device driver name */
  537. .modalias = "m25p80", /* Name of spi_driver for this device */
  538. .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
  539. .bus_num = 0, /* Framework bus number */
  540. .chip_select = 1, /* SPI_SSEL1*/
  541. .platform_data = &bfin_spi_flash_data,
  542. .controller_data = &spi_flash_chip_info,
  543. .mode = SPI_MODE_3,
  544. },
  545. #endif
  546. #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
  547. {
  548. .modalias = "ad7879",
  549. .platform_data = &bfin_ad7879_ts_info,
  550. .irq = IRQ_PF3,
  551. .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
  552. .bus_num = 0,
  553. .chip_select = 1,
  554. .mode = SPI_CPHA | SPI_CPOL,
  555. },
  556. #endif
  557. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  558. {
  559. .modalias = "bfin-lq035q1-spi",
  560. .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
  561. .bus_num = 0,
  562. .chip_select = 2,
  563. .mode = SPI_CPHA | SPI_CPOL,
  564. },
  565. #endif
  566. #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  567. {
  568. .modalias = "spidev",
  569. .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
  570. .bus_num = 0,
  571. .chip_select = 1,
  572. },
  573. #endif
  574. };
  575. /* SPI (0) */
  576. static struct resource bfin_spi0_resource[] = {
  577. [0] = {
  578. .start = SPI0_REGBASE,
  579. .end = SPI0_REGBASE + 0xFF,
  580. .flags = IORESOURCE_MEM,
  581. },
  582. [1] = {
  583. .start = CH_SPI0,
  584. .end = CH_SPI0,
  585. .flags = IORESOURCE_DMA,
  586. },
  587. [2] = {
  588. .start = IRQ_SPI0,
  589. .end = IRQ_SPI0,
  590. .flags = IORESOURCE_IRQ,
  591. }
  592. };
  593. /* SPI (1) */
  594. static struct resource bfin_spi1_resource[] = {
  595. [0] = {
  596. .start = SPI1_REGBASE,
  597. .end = SPI1_REGBASE + 0xFF,
  598. .flags = IORESOURCE_MEM,
  599. },
  600. [1] = {
  601. .start = CH_SPI1,
  602. .end = CH_SPI1,
  603. .flags = IORESOURCE_DMA,
  604. },
  605. [2] = {
  606. .start = IRQ_SPI1,
  607. .end = IRQ_SPI1,
  608. .flags = IORESOURCE_IRQ,
  609. }
  610. };
  611. /* SPI (2) */
  612. static struct resource bfin_spi2_resource[] = {
  613. [0] = {
  614. .start = SPI2_REGBASE,
  615. .end = SPI2_REGBASE + 0xFF,
  616. .flags = IORESOURCE_MEM,
  617. },
  618. [1] = {
  619. .start = CH_SPI2,
  620. .end = CH_SPI2,
  621. .flags = IORESOURCE_DMA,
  622. },
  623. [2] = {
  624. .start = IRQ_SPI2,
  625. .end = IRQ_SPI2,
  626. .flags = IORESOURCE_IRQ,
  627. }
  628. };
  629. /* SPI controller data */
  630. static struct bfin5xx_spi_master bf538_spi_master_info0 = {
  631. .num_chipselect = 8,
  632. .enable_dma = 1, /* master has the ability to do dma transfer */
  633. .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
  634. };
  635. static struct platform_device bf538_spi_master0 = {
  636. .name = "bfin-spi",
  637. .id = 0, /* Bus number */
  638. .num_resources = ARRAY_SIZE(bfin_spi0_resource),
  639. .resource = bfin_spi0_resource,
  640. .dev = {
  641. .platform_data = &bf538_spi_master_info0, /* Passed to driver */
  642. },
  643. };
  644. static struct bfin5xx_spi_master bf538_spi_master_info1 = {
  645. .num_chipselect = 2,
  646. .enable_dma = 1, /* master has the ability to do dma transfer */
  647. .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
  648. };
  649. static struct platform_device bf538_spi_master1 = {
  650. .name = "bfin-spi",
  651. .id = 1, /* Bus number */
  652. .num_resources = ARRAY_SIZE(bfin_spi1_resource),
  653. .resource = bfin_spi1_resource,
  654. .dev = {
  655. .platform_data = &bf538_spi_master_info1, /* Passed to driver */
  656. },
  657. };
  658. static struct bfin5xx_spi_master bf538_spi_master_info2 = {
  659. .num_chipselect = 2,
  660. .enable_dma = 1, /* master has the ability to do dma transfer */
  661. .pin_req = {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
  662. };
  663. static struct platform_device bf538_spi_master2 = {
  664. .name = "bfin-spi",
  665. .id = 2, /* Bus number */
  666. .num_resources = ARRAY_SIZE(bfin_spi2_resource),
  667. .resource = bfin_spi2_resource,
  668. .dev = {
  669. .platform_data = &bf538_spi_master_info2, /* Passed to driver */
  670. },
  671. };
  672. #endif /* spi master and devices */
  673. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  674. static struct resource bfin_twi0_resource[] = {
  675. [0] = {
  676. .start = TWI0_REGBASE,
  677. .end = TWI0_REGBASE + 0xFF,
  678. .flags = IORESOURCE_MEM,
  679. },
  680. [1] = {
  681. .start = IRQ_TWI0,
  682. .end = IRQ_TWI0,
  683. .flags = IORESOURCE_IRQ,
  684. },
  685. };
  686. static struct platform_device i2c_bfin_twi0_device = {
  687. .name = "i2c-bfin-twi",
  688. .id = 0,
  689. .num_resources = ARRAY_SIZE(bfin_twi0_resource),
  690. .resource = bfin_twi0_resource,
  691. };
  692. #if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */
  693. static struct resource bfin_twi1_resource[] = {
  694. [0] = {
  695. .start = TWI1_REGBASE,
  696. .end = TWI1_REGBASE + 0xFF,
  697. .flags = IORESOURCE_MEM,
  698. },
  699. [1] = {
  700. .start = IRQ_TWI1,
  701. .end = IRQ_TWI1,
  702. .flags = IORESOURCE_IRQ,
  703. },
  704. };
  705. static struct platform_device i2c_bfin_twi1_device = {
  706. .name = "i2c-bfin-twi",
  707. .id = 1,
  708. .num_resources = ARRAY_SIZE(bfin_twi1_resource),
  709. .resource = bfin_twi1_resource,
  710. };
  711. #endif
  712. #endif
  713. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  714. #include <linux/gpio_keys.h>
  715. static struct gpio_keys_button bfin_gpio_keys_table[] = {
  716. {BTN_0, GPIO_PC7, 1, "gpio-keys: BTN0"},
  717. };
  718. static struct gpio_keys_platform_data bfin_gpio_keys_data = {
  719. .buttons = bfin_gpio_keys_table,
  720. .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
  721. };
  722. static struct platform_device bfin_device_gpiokeys = {
  723. .name = "gpio-keys",
  724. .dev = {
  725. .platform_data = &bfin_gpio_keys_data,
  726. },
  727. };
  728. #endif
  729. static const unsigned int cclk_vlev_datasheet[] =
  730. {
  731. /*
  732. * Internal VLEV BF538SBBC1533
  733. ****temporarily using these values until data sheet is updated
  734. */
  735. VRPAIR(VLEV_100, 150000000),
  736. VRPAIR(VLEV_100, 250000000),
  737. VRPAIR(VLEV_110, 276000000),
  738. VRPAIR(VLEV_115, 301000000),
  739. VRPAIR(VLEV_120, 525000000),
  740. VRPAIR(VLEV_125, 550000000),
  741. VRPAIR(VLEV_130, 600000000),
  742. };
  743. static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
  744. .tuple_tab = cclk_vlev_datasheet,
  745. .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
  746. .vr_settling_time = 25 /* us */,
  747. };
  748. static struct platform_device bfin_dpmc = {
  749. .name = "bfin dpmc",
  750. .dev = {
  751. .platform_data = &bfin_dmpc_vreg_data,
  752. },
  753. };
  754. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  755. static struct mtd_partition ezkit_partitions[] = {
  756. {
  757. .name = "bootloader(nor)",
  758. .size = 0x40000,
  759. .offset = 0,
  760. }, {
  761. .name = "linux kernel(nor)",
  762. .size = 0x180000,
  763. .offset = MTDPART_OFS_APPEND,
  764. }, {
  765. .name = "file system(nor)",
  766. .size = MTDPART_SIZ_FULL,
  767. .offset = MTDPART_OFS_APPEND,
  768. }
  769. };
  770. static struct physmap_flash_data ezkit_flash_data = {
  771. .width = 2,
  772. .parts = ezkit_partitions,
  773. .nr_parts = ARRAY_SIZE(ezkit_partitions),
  774. };
  775. static struct resource ezkit_flash_resource = {
  776. .start = 0x20000000,
  777. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  778. .end = 0x202fffff,
  779. #else
  780. .end = 0x203fffff,
  781. #endif
  782. .flags = IORESOURCE_MEM,
  783. };
  784. static struct platform_device ezkit_flash_device = {
  785. .name = "physmap-flash",
  786. .id = 0,
  787. .dev = {
  788. .platform_data = &ezkit_flash_data,
  789. },
  790. .num_resources = 1,
  791. .resource = &ezkit_flash_resource,
  792. };
  793. #endif
  794. static struct platform_device *cm_bf538_devices[] __initdata = {
  795. &bfin_dpmc,
  796. #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
  797. &rtc_device,
  798. #endif
  799. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  800. #ifdef CONFIG_SERIAL_BFIN_UART0
  801. &bfin_uart0_device,
  802. #endif
  803. #ifdef CONFIG_SERIAL_BFIN_UART1
  804. &bfin_uart1_device,
  805. #endif
  806. #ifdef CONFIG_SERIAL_BFIN_UART2
  807. &bfin_uart2_device,
  808. #endif
  809. #endif
  810. #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
  811. &bf538_spi_master0,
  812. &bf538_spi_master1,
  813. &bf538_spi_master2,
  814. #endif
  815. #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
  816. &i2c_bfin_twi0_device,
  817. &i2c_bfin_twi1_device,
  818. #endif
  819. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  820. #ifdef CONFIG_BFIN_SIR0
  821. &bfin_sir0_device,
  822. #endif
  823. #ifdef CONFIG_BFIN_SIR1
  824. &bfin_sir1_device,
  825. #endif
  826. #ifdef CONFIG_BFIN_SIR2
  827. &bfin_sir2_device,
  828. #endif
  829. #endif
  830. #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
  831. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  832. &bfin_sport0_uart_device,
  833. #endif
  834. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  835. &bfin_sport1_uart_device,
  836. #endif
  837. #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
  838. &bfin_sport2_uart_device,
  839. #endif
  840. #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
  841. &bfin_sport3_uart_device,
  842. #endif
  843. #endif
  844. #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
  845. &bfin_can_device,
  846. #endif
  847. #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
  848. &smc91x_device,
  849. #endif
  850. #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
  851. &bfin_lq035q1_device,
  852. #endif
  853. #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
  854. &bfin_device_gpiokeys,
  855. #endif
  856. #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
  857. &ezkit_flash_device,
  858. #endif
  859. };
  860. static int __init ezkit_init(void)
  861. {
  862. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  863. platform_add_devices(cm_bf538_devices, ARRAY_SIZE(cm_bf538_devices));
  864. #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
  865. spi_register_board_info(bf538_spi_board_info,
  866. ARRAY_SIZE(bf538_spi_board_info));
  867. #endif
  868. return 0;
  869. }
  870. arch_initcall(ezkit_init);
  871. static struct platform_device *ezkit_early_devices[] __initdata = {
  872. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  873. #ifdef CONFIG_SERIAL_BFIN_UART0
  874. &bfin_uart0_device,
  875. #endif
  876. #ifdef CONFIG_SERIAL_BFIN_UART1
  877. &bfin_uart1_device,
  878. #endif
  879. #ifdef CONFIG_SERIAL_BFIN_UART2
  880. &bfin_uart2_device,
  881. #endif
  882. #endif
  883. #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
  884. #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
  885. &bfin_sport0_uart_device,
  886. #endif
  887. #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
  888. &bfin_sport1_uart_device,
  889. #endif
  890. #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
  891. &bfin_sport2_uart_device,
  892. #endif
  893. #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
  894. &bfin_sport3_uart_device,
  895. #endif
  896. #endif
  897. };
  898. void __init native_machine_early_platform_add_devices(void)
  899. {
  900. printk(KERN_INFO "register early platform devices\n");
  901. early_platform_add_devices(ezkit_early_devices,
  902. ARRAY_SIZE(ezkit_early_devices));
  903. }