generic.c 10 KB

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  1. /*
  2. * linux/arch/arm/mach-sa1100/generic.c
  3. *
  4. * Author: Nicolas Pitre
  5. *
  6. * Code common to all SA11x0 machines.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/gpio.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/delay.h>
  17. #include <linux/pm.h>
  18. #include <linux/cpufreq.h>
  19. #include <linux/ioport.h>
  20. #include <linux/platform_device.h>
  21. #include <asm/div64.h>
  22. #include <mach/hardware.h>
  23. #include <asm/system.h>
  24. #include <asm/mach/map.h>
  25. #include <asm/mach/flash.h>
  26. #include <asm/irq.h>
  27. #include "generic.h"
  28. unsigned int reset_status;
  29. EXPORT_SYMBOL(reset_status);
  30. #define NR_FREQS 16
  31. /*
  32. * This table is setup for a 3.6864MHz Crystal.
  33. */
  34. static const unsigned short cclk_frequency_100khz[NR_FREQS] = {
  35. 590, /* 59.0 MHz */
  36. 737, /* 73.7 MHz */
  37. 885, /* 88.5 MHz */
  38. 1032, /* 103.2 MHz */
  39. 1180, /* 118.0 MHz */
  40. 1327, /* 132.7 MHz */
  41. 1475, /* 147.5 MHz */
  42. 1622, /* 162.2 MHz */
  43. 1769, /* 176.9 MHz */
  44. 1917, /* 191.7 MHz */
  45. 2064, /* 206.4 MHz */
  46. 2212, /* 221.2 MHz */
  47. 2359, /* 235.9 MHz */
  48. 2507, /* 250.7 MHz */
  49. 2654, /* 265.4 MHz */
  50. 2802 /* 280.2 MHz */
  51. };
  52. /* rounds up(!) */
  53. unsigned int sa11x0_freq_to_ppcr(unsigned int khz)
  54. {
  55. int i;
  56. khz /= 100;
  57. for (i = 0; i < NR_FREQS; i++)
  58. if (cclk_frequency_100khz[i] >= khz)
  59. break;
  60. return i;
  61. }
  62. unsigned int sa11x0_ppcr_to_freq(unsigned int idx)
  63. {
  64. unsigned int freq = 0;
  65. if (idx < NR_FREQS)
  66. freq = cclk_frequency_100khz[idx] * 100;
  67. return freq;
  68. }
  69. /* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
  70. * this platform, anyway.
  71. */
  72. int sa11x0_verify_speed(struct cpufreq_policy *policy)
  73. {
  74. unsigned int tmp;
  75. if (policy->cpu)
  76. return -EINVAL;
  77. cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
  78. /* make sure that at least one frequency is within the policy */
  79. tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100;
  80. if (tmp > policy->max)
  81. policy->max = tmp;
  82. cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
  83. return 0;
  84. }
  85. unsigned int sa11x0_getspeed(unsigned int cpu)
  86. {
  87. if (cpu)
  88. return 0;
  89. return cclk_frequency_100khz[PPCR & 0xf] * 100;
  90. }
  91. /*
  92. * Default power-off for SA1100
  93. */
  94. static void sa1100_power_off(void)
  95. {
  96. mdelay(100);
  97. local_irq_disable();
  98. /* disable internal oscillator, float CS lines */
  99. PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
  100. /* enable wake-up on GPIO0 (Assabet...) */
  101. PWER = GFER = GRER = 1;
  102. /*
  103. * set scratchpad to zero, just in case it is used as a
  104. * restart address by the bootloader.
  105. */
  106. PSPR = 0;
  107. /* enter sleep mode */
  108. PMCR = PMCR_SF;
  109. }
  110. void sa11x0_restart(char mode, const char *cmd)
  111. {
  112. if (mode == 's') {
  113. /* Jump into ROM at address 0 */
  114. soft_restart(0);
  115. } else {
  116. /* Use on-chip reset capability */
  117. RSRR = RSRR_SWR;
  118. }
  119. }
  120. static void sa11x0_register_device(struct platform_device *dev, void *data)
  121. {
  122. int err;
  123. dev->dev.platform_data = data;
  124. err = platform_device_register(dev);
  125. if (err)
  126. printk(KERN_ERR "Unable to register device %s: %d\n",
  127. dev->name, err);
  128. }
  129. static struct resource sa11x0udc_resources[] = {
  130. [0] = {
  131. .start = __PREG(Ser0UDCCR),
  132. .end = __PREG(Ser0UDCCR) + 0xffff,
  133. .flags = IORESOURCE_MEM,
  134. },
  135. [1] = {
  136. .start = IRQ_Ser0UDC,
  137. .end = IRQ_Ser0UDC,
  138. .flags = IORESOURCE_IRQ,
  139. },
  140. };
  141. static u64 sa11x0udc_dma_mask = 0xffffffffUL;
  142. static struct platform_device sa11x0udc_device = {
  143. .name = "sa11x0-udc",
  144. .id = -1,
  145. .dev = {
  146. .dma_mask = &sa11x0udc_dma_mask,
  147. .coherent_dma_mask = 0xffffffff,
  148. },
  149. .num_resources = ARRAY_SIZE(sa11x0udc_resources),
  150. .resource = sa11x0udc_resources,
  151. };
  152. static struct resource sa11x0uart1_resources[] = {
  153. [0] = {
  154. .start = __PREG(Ser1UTCR0),
  155. .end = __PREG(Ser1UTCR0) + 0xffff,
  156. .flags = IORESOURCE_MEM,
  157. },
  158. [1] = {
  159. .start = IRQ_Ser1UART,
  160. .end = IRQ_Ser1UART,
  161. .flags = IORESOURCE_IRQ,
  162. },
  163. };
  164. static struct platform_device sa11x0uart1_device = {
  165. .name = "sa11x0-uart",
  166. .id = 1,
  167. .num_resources = ARRAY_SIZE(sa11x0uart1_resources),
  168. .resource = sa11x0uart1_resources,
  169. };
  170. static struct resource sa11x0uart3_resources[] = {
  171. [0] = {
  172. .start = __PREG(Ser3UTCR0),
  173. .end = __PREG(Ser3UTCR0) + 0xffff,
  174. .flags = IORESOURCE_MEM,
  175. },
  176. [1] = {
  177. .start = IRQ_Ser3UART,
  178. .end = IRQ_Ser3UART,
  179. .flags = IORESOURCE_IRQ,
  180. },
  181. };
  182. static struct platform_device sa11x0uart3_device = {
  183. .name = "sa11x0-uart",
  184. .id = 3,
  185. .num_resources = ARRAY_SIZE(sa11x0uart3_resources),
  186. .resource = sa11x0uart3_resources,
  187. };
  188. static struct resource sa11x0mcp_resources[] = {
  189. [0] = {
  190. .start = __PREG(Ser4MCCR0),
  191. .end = __PREG(Ser4MCCR0) + 0x1C - 1,
  192. .flags = IORESOURCE_MEM,
  193. },
  194. [1] = {
  195. .start = __PREG(Ser4MCCR1),
  196. .end = __PREG(Ser4MCCR1) + 0x4 - 1,
  197. .flags = IORESOURCE_MEM,
  198. },
  199. [2] = {
  200. .start = IRQ_Ser4MCP,
  201. .end = IRQ_Ser4MCP,
  202. .flags = IORESOURCE_IRQ,
  203. },
  204. };
  205. static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
  206. static struct platform_device sa11x0mcp_device = {
  207. .name = "sa11x0-mcp",
  208. .id = -1,
  209. .dev = {
  210. .dma_mask = &sa11x0mcp_dma_mask,
  211. .coherent_dma_mask = 0xffffffff,
  212. },
  213. .num_resources = ARRAY_SIZE(sa11x0mcp_resources),
  214. .resource = sa11x0mcp_resources,
  215. };
  216. void sa11x0_register_mcp(struct mcp_plat_data *data)
  217. {
  218. sa11x0_register_device(&sa11x0mcp_device, data);
  219. }
  220. static struct resource sa11x0ssp_resources[] = {
  221. [0] = {
  222. .start = 0x80070000,
  223. .end = 0x8007ffff,
  224. .flags = IORESOURCE_MEM,
  225. },
  226. [1] = {
  227. .start = IRQ_Ser4SSP,
  228. .end = IRQ_Ser4SSP,
  229. .flags = IORESOURCE_IRQ,
  230. },
  231. };
  232. static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
  233. static struct platform_device sa11x0ssp_device = {
  234. .name = "sa11x0-ssp",
  235. .id = -1,
  236. .dev = {
  237. .dma_mask = &sa11x0ssp_dma_mask,
  238. .coherent_dma_mask = 0xffffffff,
  239. },
  240. .num_resources = ARRAY_SIZE(sa11x0ssp_resources),
  241. .resource = sa11x0ssp_resources,
  242. };
  243. static struct resource sa11x0fb_resources[] = {
  244. [0] = {
  245. .start = 0xb0100000,
  246. .end = 0xb010ffff,
  247. .flags = IORESOURCE_MEM,
  248. },
  249. [1] = {
  250. .start = IRQ_LCD,
  251. .end = IRQ_LCD,
  252. .flags = IORESOURCE_IRQ,
  253. },
  254. };
  255. static struct platform_device sa11x0fb_device = {
  256. .name = "sa11x0-fb",
  257. .id = -1,
  258. .dev = {
  259. .coherent_dma_mask = 0xffffffff,
  260. },
  261. .num_resources = ARRAY_SIZE(sa11x0fb_resources),
  262. .resource = sa11x0fb_resources,
  263. };
  264. static struct platform_device sa11x0pcmcia_device = {
  265. .name = "sa11x0-pcmcia",
  266. .id = -1,
  267. };
  268. static struct platform_device sa11x0mtd_device = {
  269. .name = "sa1100-mtd",
  270. .id = -1,
  271. };
  272. void sa11x0_register_mtd(struct flash_platform_data *flash,
  273. struct resource *res, int nr)
  274. {
  275. flash->name = "sa1100";
  276. sa11x0mtd_device.resource = res;
  277. sa11x0mtd_device.num_resources = nr;
  278. sa11x0_register_device(&sa11x0mtd_device, flash);
  279. }
  280. static struct resource sa11x0ir_resources[] = {
  281. {
  282. .start = __PREG(Ser2UTCR0),
  283. .end = __PREG(Ser2UTCR0) + 0x24 - 1,
  284. .flags = IORESOURCE_MEM,
  285. }, {
  286. .start = __PREG(Ser2HSCR0),
  287. .end = __PREG(Ser2HSCR0) + 0x1c - 1,
  288. .flags = IORESOURCE_MEM,
  289. }, {
  290. .start = __PREG(Ser2HSCR2),
  291. .end = __PREG(Ser2HSCR2) + 0x04 - 1,
  292. .flags = IORESOURCE_MEM,
  293. }, {
  294. .start = IRQ_Ser2ICP,
  295. .end = IRQ_Ser2ICP,
  296. .flags = IORESOURCE_IRQ,
  297. }
  298. };
  299. static struct platform_device sa11x0ir_device = {
  300. .name = "sa11x0-ir",
  301. .id = -1,
  302. .num_resources = ARRAY_SIZE(sa11x0ir_resources),
  303. .resource = sa11x0ir_resources,
  304. };
  305. void sa11x0_register_irda(struct irda_platform_data *irda)
  306. {
  307. sa11x0_register_device(&sa11x0ir_device, irda);
  308. }
  309. static struct resource sa11x0rtc_resources[] = {
  310. [0] = {
  311. .start = 0x90010000,
  312. .end = 0x900100ff,
  313. .flags = IORESOURCE_MEM,
  314. },
  315. [1] = {
  316. .start = IRQ_RTC1Hz,
  317. .end = IRQ_RTC1Hz,
  318. .flags = IORESOURCE_IRQ,
  319. },
  320. [2] = {
  321. .start = IRQ_RTCAlrm,
  322. .end = IRQ_RTCAlrm,
  323. .flags = IORESOURCE_IRQ,
  324. },
  325. };
  326. static struct platform_device sa11x0rtc_device = {
  327. .name = "sa1100-rtc",
  328. .id = -1,
  329. .resource = sa11x0rtc_resources,
  330. .num_resources = ARRAY_SIZE(sa11x0rtc_resources),
  331. };
  332. static struct platform_device *sa11x0_devices[] __initdata = {
  333. &sa11x0udc_device,
  334. &sa11x0uart1_device,
  335. &sa11x0uart3_device,
  336. &sa11x0ssp_device,
  337. &sa11x0pcmcia_device,
  338. &sa11x0fb_device,
  339. &sa11x0rtc_device,
  340. };
  341. static int __init sa1100_init(void)
  342. {
  343. pm_power_off = sa1100_power_off;
  344. return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
  345. }
  346. arch_initcall(sa1100_init);
  347. void (*sa1100fb_backlight_power)(int on);
  348. void (*sa1100fb_lcd_power)(int on);
  349. EXPORT_SYMBOL(sa1100fb_backlight_power);
  350. EXPORT_SYMBOL(sa1100fb_lcd_power);
  351. /*
  352. * Common I/O mapping:
  353. *
  354. * Typically, static virtual address mappings are as follow:
  355. *
  356. * 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.)
  357. * 0xf4000000-0xf4ffffff: SA-1111
  358. * 0xf5000000-0xf5ffffff: reserved (used by cache flushing area)
  359. * 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above)
  360. * 0xffff0000-0xffff0fff: SA1100 exception vectors
  361. * 0xffff2000-0xffff2fff: Minicache copy_user_page area
  362. *
  363. * Below 0xe8000000 is reserved for vm allocation.
  364. *
  365. * The machine specific code must provide the extra mapping beside the
  366. * default mapping provided here.
  367. */
  368. static struct map_desc standard_io_desc[] __initdata = {
  369. { /* PCM */
  370. .virtual = 0xf8000000,
  371. .pfn = __phys_to_pfn(0x80000000),
  372. .length = 0x00100000,
  373. .type = MT_DEVICE
  374. }, { /* SCM */
  375. .virtual = 0xfa000000,
  376. .pfn = __phys_to_pfn(0x90000000),
  377. .length = 0x00100000,
  378. .type = MT_DEVICE
  379. }, { /* MER */
  380. .virtual = 0xfc000000,
  381. .pfn = __phys_to_pfn(0xa0000000),
  382. .length = 0x00100000,
  383. .type = MT_DEVICE
  384. }, { /* LCD + DMA */
  385. .virtual = 0xfe000000,
  386. .pfn = __phys_to_pfn(0xb0000000),
  387. .length = 0x00200000,
  388. .type = MT_DEVICE
  389. },
  390. };
  391. void __init sa1100_map_io(void)
  392. {
  393. iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
  394. }
  395. /*
  396. * Disable the memory bus request/grant signals on the SA1110 to
  397. * ensure that we don't receive spurious memory requests. We set
  398. * the MBGNT signal false to ensure the SA1111 doesn't own the
  399. * SDRAM bus.
  400. */
  401. void __init sa1110_mb_disable(void)
  402. {
  403. unsigned long flags;
  404. local_irq_save(flags);
  405. PGSR &= ~GPIO_MBGNT;
  406. GPCR = GPIO_MBGNT;
  407. GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
  408. GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);
  409. local_irq_restore(flags);
  410. }
  411. /*
  412. * If the system is going to use the SA-1111 DMA engines, set up
  413. * the memory bus request/grant pins.
  414. */
  415. void __devinit sa1110_mb_enable(void)
  416. {
  417. unsigned long flags;
  418. local_irq_save(flags);
  419. PGSR &= ~GPIO_MBGNT;
  420. GPCR = GPIO_MBGNT;
  421. GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
  422. GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
  423. TUCR |= TUCR_MR;
  424. local_irq_restore(flags);
  425. }