clock.c 33 KB

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  1. /* linux/arch/arm/mach-s5pv210/clock.c
  2. *
  3. * Copyright (c) 2010 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com/
  5. *
  6. * S5PV210 - Clock support
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/list.h>
  16. #include <linux/errno.h>
  17. #include <linux/err.h>
  18. #include <linux/clk.h>
  19. #include <linux/device.h>
  20. #include <linux/io.h>
  21. #include <mach/map.h>
  22. #include <plat/cpu-freq.h>
  23. #include <mach/regs-clock.h>
  24. #include <plat/clock.h>
  25. #include <plat/cpu.h>
  26. #include <plat/pll.h>
  27. #include <plat/s5p-clock.h>
  28. #include <plat/clock-clksrc.h>
  29. #include "common.h"
  30. static unsigned long xtal;
  31. static struct clksrc_clk clk_mout_apll = {
  32. .clk = {
  33. .name = "mout_apll",
  34. },
  35. .sources = &clk_src_apll,
  36. .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  37. };
  38. static struct clksrc_clk clk_mout_epll = {
  39. .clk = {
  40. .name = "mout_epll",
  41. },
  42. .sources = &clk_src_epll,
  43. .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
  44. };
  45. static struct clksrc_clk clk_mout_mpll = {
  46. .clk = {
  47. .name = "mout_mpll",
  48. },
  49. .sources = &clk_src_mpll,
  50. .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  51. };
  52. static struct clk *clkset_armclk_list[] = {
  53. [0] = &clk_mout_apll.clk,
  54. [1] = &clk_mout_mpll.clk,
  55. };
  56. static struct clksrc_sources clkset_armclk = {
  57. .sources = clkset_armclk_list,
  58. .nr_sources = ARRAY_SIZE(clkset_armclk_list),
  59. };
  60. static struct clksrc_clk clk_armclk = {
  61. .clk = {
  62. .name = "armclk",
  63. },
  64. .sources = &clkset_armclk,
  65. .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
  66. .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
  67. };
  68. static struct clksrc_clk clk_hclk_msys = {
  69. .clk = {
  70. .name = "hclk_msys",
  71. .parent = &clk_armclk.clk,
  72. },
  73. .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
  74. };
  75. static struct clksrc_clk clk_pclk_msys = {
  76. .clk = {
  77. .name = "pclk_msys",
  78. .parent = &clk_hclk_msys.clk,
  79. },
  80. .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
  81. };
  82. static struct clksrc_clk clk_sclk_a2m = {
  83. .clk = {
  84. .name = "sclk_a2m",
  85. .parent = &clk_mout_apll.clk,
  86. },
  87. .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
  88. };
  89. static struct clk *clkset_hclk_sys_list[] = {
  90. [0] = &clk_mout_mpll.clk,
  91. [1] = &clk_sclk_a2m.clk,
  92. };
  93. static struct clksrc_sources clkset_hclk_sys = {
  94. .sources = clkset_hclk_sys_list,
  95. .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
  96. };
  97. static struct clksrc_clk clk_hclk_dsys = {
  98. .clk = {
  99. .name = "hclk_dsys",
  100. },
  101. .sources = &clkset_hclk_sys,
  102. .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
  103. .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
  104. };
  105. static struct clksrc_clk clk_pclk_dsys = {
  106. .clk = {
  107. .name = "pclk_dsys",
  108. .parent = &clk_hclk_dsys.clk,
  109. },
  110. .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
  111. };
  112. static struct clksrc_clk clk_hclk_psys = {
  113. .clk = {
  114. .name = "hclk_psys",
  115. },
  116. .sources = &clkset_hclk_sys,
  117. .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
  118. .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
  119. };
  120. static struct clksrc_clk clk_pclk_psys = {
  121. .clk = {
  122. .name = "pclk_psys",
  123. .parent = &clk_hclk_psys.clk,
  124. },
  125. .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
  126. };
  127. static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
  128. {
  129. return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
  130. }
  131. static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
  132. {
  133. return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
  134. }
  135. static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
  136. {
  137. return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
  138. }
  139. static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
  140. {
  141. return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
  142. }
  143. static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
  144. {
  145. return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
  146. }
  147. static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
  148. {
  149. return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
  150. }
  151. static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
  152. {
  153. return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
  154. }
  155. static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
  156. {
  157. return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
  158. }
  159. static struct clk clk_sclk_hdmi27m = {
  160. .name = "sclk_hdmi27m",
  161. .rate = 27000000,
  162. };
  163. static struct clk clk_sclk_hdmiphy = {
  164. .name = "sclk_hdmiphy",
  165. };
  166. static struct clk clk_sclk_usbphy0 = {
  167. .name = "sclk_usbphy0",
  168. };
  169. static struct clk clk_sclk_usbphy1 = {
  170. .name = "sclk_usbphy1",
  171. };
  172. static struct clk clk_pcmcdclk0 = {
  173. .name = "pcmcdclk",
  174. };
  175. static struct clk clk_pcmcdclk1 = {
  176. .name = "pcmcdclk",
  177. };
  178. static struct clk clk_pcmcdclk2 = {
  179. .name = "pcmcdclk",
  180. };
  181. static struct clk dummy_apb_pclk = {
  182. .name = "apb_pclk",
  183. .id = -1,
  184. };
  185. static struct clk *clkset_vpllsrc_list[] = {
  186. [0] = &clk_fin_vpll,
  187. [1] = &clk_sclk_hdmi27m,
  188. };
  189. static struct clksrc_sources clkset_vpllsrc = {
  190. .sources = clkset_vpllsrc_list,
  191. .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
  192. };
  193. static struct clksrc_clk clk_vpllsrc = {
  194. .clk = {
  195. .name = "vpll_src",
  196. .enable = s5pv210_clk_mask0_ctrl,
  197. .ctrlbit = (1 << 7),
  198. },
  199. .sources = &clkset_vpllsrc,
  200. .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
  201. };
  202. static struct clk *clkset_sclk_vpll_list[] = {
  203. [0] = &clk_vpllsrc.clk,
  204. [1] = &clk_fout_vpll,
  205. };
  206. static struct clksrc_sources clkset_sclk_vpll = {
  207. .sources = clkset_sclk_vpll_list,
  208. .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
  209. };
  210. static struct clksrc_clk clk_sclk_vpll = {
  211. .clk = {
  212. .name = "sclk_vpll",
  213. },
  214. .sources = &clkset_sclk_vpll,
  215. .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
  216. };
  217. static struct clk *clkset_moutdmc0src_list[] = {
  218. [0] = &clk_sclk_a2m.clk,
  219. [1] = &clk_mout_mpll.clk,
  220. [2] = NULL,
  221. [3] = NULL,
  222. };
  223. static struct clksrc_sources clkset_moutdmc0src = {
  224. .sources = clkset_moutdmc0src_list,
  225. .nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list),
  226. };
  227. static struct clksrc_clk clk_mout_dmc0 = {
  228. .clk = {
  229. .name = "mout_dmc0",
  230. },
  231. .sources = &clkset_moutdmc0src,
  232. .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
  233. };
  234. static struct clksrc_clk clk_sclk_dmc0 = {
  235. .clk = {
  236. .name = "sclk_dmc0",
  237. .parent = &clk_mout_dmc0.clk,
  238. },
  239. .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
  240. };
  241. static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
  242. {
  243. return clk_get_rate(clk->parent) / 2;
  244. }
  245. static struct clk_ops clk_hclk_imem_ops = {
  246. .get_rate = s5pv210_clk_imem_get_rate,
  247. };
  248. static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
  249. {
  250. return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
  251. }
  252. static struct clk_ops clk_fout_apll_ops = {
  253. .get_rate = s5pv210_clk_fout_apll_get_rate,
  254. };
  255. static struct clk init_clocks_off[] = {
  256. {
  257. .name = "dma",
  258. .devname = "dma-pl330.0",
  259. .parent = &clk_hclk_psys.clk,
  260. .enable = s5pv210_clk_ip0_ctrl,
  261. .ctrlbit = (1 << 3),
  262. }, {
  263. .name = "dma",
  264. .devname = "dma-pl330.1",
  265. .parent = &clk_hclk_psys.clk,
  266. .enable = s5pv210_clk_ip0_ctrl,
  267. .ctrlbit = (1 << 4),
  268. }, {
  269. .name = "rot",
  270. .parent = &clk_hclk_dsys.clk,
  271. .enable = s5pv210_clk_ip0_ctrl,
  272. .ctrlbit = (1<<29),
  273. }, {
  274. .name = "fimc",
  275. .devname = "s5pv210-fimc.0",
  276. .parent = &clk_hclk_dsys.clk,
  277. .enable = s5pv210_clk_ip0_ctrl,
  278. .ctrlbit = (1 << 24),
  279. }, {
  280. .name = "fimc",
  281. .devname = "s5pv210-fimc.1",
  282. .parent = &clk_hclk_dsys.clk,
  283. .enable = s5pv210_clk_ip0_ctrl,
  284. .ctrlbit = (1 << 25),
  285. }, {
  286. .name = "fimc",
  287. .devname = "s5pv210-fimc.2",
  288. .parent = &clk_hclk_dsys.clk,
  289. .enable = s5pv210_clk_ip0_ctrl,
  290. .ctrlbit = (1 << 26),
  291. }, {
  292. .name = "mfc",
  293. .devname = "s5p-mfc",
  294. .parent = &clk_pclk_psys.clk,
  295. .enable = s5pv210_clk_ip0_ctrl,
  296. .ctrlbit = (1 << 16),
  297. }, {
  298. .name = "dac",
  299. .devname = "s5p-sdo",
  300. .parent = &clk_hclk_dsys.clk,
  301. .enable = s5pv210_clk_ip1_ctrl,
  302. .ctrlbit = (1 << 10),
  303. }, {
  304. .name = "mixer",
  305. .devname = "s5p-mixer",
  306. .parent = &clk_hclk_dsys.clk,
  307. .enable = s5pv210_clk_ip1_ctrl,
  308. .ctrlbit = (1 << 9),
  309. }, {
  310. .name = "vp",
  311. .devname = "s5p-mixer",
  312. .parent = &clk_hclk_dsys.clk,
  313. .enable = s5pv210_clk_ip1_ctrl,
  314. .ctrlbit = (1 << 8),
  315. }, {
  316. .name = "hdmi",
  317. .devname = "s5pv210-hdmi",
  318. .parent = &clk_hclk_dsys.clk,
  319. .enable = s5pv210_clk_ip1_ctrl,
  320. .ctrlbit = (1 << 11),
  321. }, {
  322. .name = "hdmiphy",
  323. .devname = "s5pv210-hdmi",
  324. .enable = exynos4_clk_hdmiphy_ctrl,
  325. .ctrlbit = (1 << 0),
  326. }, {
  327. .name = "dacphy",
  328. .devname = "s5p-sdo",
  329. .enable = exynos4_clk_dac_ctrl,
  330. .ctrlbit = (1 << 0),
  331. }, {
  332. .name = "otg",
  333. .parent = &clk_hclk_psys.clk,
  334. .enable = s5pv210_clk_ip1_ctrl,
  335. .ctrlbit = (1<<16),
  336. }, {
  337. .name = "usb-host",
  338. .parent = &clk_hclk_psys.clk,
  339. .enable = s5pv210_clk_ip1_ctrl,
  340. .ctrlbit = (1<<17),
  341. }, {
  342. .name = "lcd",
  343. .parent = &clk_hclk_dsys.clk,
  344. .enable = s5pv210_clk_ip1_ctrl,
  345. .ctrlbit = (1<<0),
  346. }, {
  347. .name = "cfcon",
  348. .parent = &clk_hclk_psys.clk,
  349. .enable = s5pv210_clk_ip1_ctrl,
  350. .ctrlbit = (1<<25),
  351. }, {
  352. .name = "systimer",
  353. .parent = &clk_pclk_psys.clk,
  354. .enable = s5pv210_clk_ip3_ctrl,
  355. .ctrlbit = (1<<16),
  356. }, {
  357. .name = "watchdog",
  358. .parent = &clk_pclk_psys.clk,
  359. .enable = s5pv210_clk_ip3_ctrl,
  360. .ctrlbit = (1<<22),
  361. }, {
  362. .name = "rtc",
  363. .parent = &clk_pclk_psys.clk,
  364. .enable = s5pv210_clk_ip3_ctrl,
  365. .ctrlbit = (1<<15),
  366. }, {
  367. .name = "i2c",
  368. .devname = "s3c2440-i2c.0",
  369. .parent = &clk_pclk_psys.clk,
  370. .enable = s5pv210_clk_ip3_ctrl,
  371. .ctrlbit = (1<<7),
  372. }, {
  373. .name = "i2c",
  374. .devname = "s3c2440-i2c.1",
  375. .parent = &clk_pclk_psys.clk,
  376. .enable = s5pv210_clk_ip3_ctrl,
  377. .ctrlbit = (1 << 10),
  378. }, {
  379. .name = "i2c",
  380. .devname = "s3c2440-i2c.2",
  381. .parent = &clk_pclk_psys.clk,
  382. .enable = s5pv210_clk_ip3_ctrl,
  383. .ctrlbit = (1<<9),
  384. }, {
  385. .name = "i2c",
  386. .devname = "s3c2440-hdmiphy-i2c",
  387. .parent = &clk_pclk_psys.clk,
  388. .enable = s5pv210_clk_ip3_ctrl,
  389. .ctrlbit = (1 << 11),
  390. }, {
  391. .name = "spi",
  392. .devname = "s3c64xx-spi.0",
  393. .parent = &clk_pclk_psys.clk,
  394. .enable = s5pv210_clk_ip3_ctrl,
  395. .ctrlbit = (1<<12),
  396. }, {
  397. .name = "spi",
  398. .devname = "s3c64xx-spi.1",
  399. .parent = &clk_pclk_psys.clk,
  400. .enable = s5pv210_clk_ip3_ctrl,
  401. .ctrlbit = (1<<13),
  402. }, {
  403. .name = "spi",
  404. .devname = "s3c64xx-spi.2",
  405. .parent = &clk_pclk_psys.clk,
  406. .enable = s5pv210_clk_ip3_ctrl,
  407. .ctrlbit = (1<<14),
  408. }, {
  409. .name = "timers",
  410. .parent = &clk_pclk_psys.clk,
  411. .enable = s5pv210_clk_ip3_ctrl,
  412. .ctrlbit = (1<<23),
  413. }, {
  414. .name = "adc",
  415. .parent = &clk_pclk_psys.clk,
  416. .enable = s5pv210_clk_ip3_ctrl,
  417. .ctrlbit = (1<<24),
  418. }, {
  419. .name = "keypad",
  420. .parent = &clk_pclk_psys.clk,
  421. .enable = s5pv210_clk_ip3_ctrl,
  422. .ctrlbit = (1<<21),
  423. }, {
  424. .name = "iis",
  425. .devname = "samsung-i2s.0",
  426. .parent = &clk_p,
  427. .enable = s5pv210_clk_ip3_ctrl,
  428. .ctrlbit = (1<<4),
  429. }, {
  430. .name = "iis",
  431. .devname = "samsung-i2s.1",
  432. .parent = &clk_p,
  433. .enable = s5pv210_clk_ip3_ctrl,
  434. .ctrlbit = (1 << 5),
  435. }, {
  436. .name = "iis",
  437. .devname = "samsung-i2s.2",
  438. .parent = &clk_p,
  439. .enable = s5pv210_clk_ip3_ctrl,
  440. .ctrlbit = (1 << 6),
  441. }, {
  442. .name = "spdif",
  443. .parent = &clk_p,
  444. .enable = s5pv210_clk_ip3_ctrl,
  445. .ctrlbit = (1 << 0),
  446. },
  447. };
  448. static struct clk init_clocks[] = {
  449. {
  450. .name = "hclk_imem",
  451. .parent = &clk_hclk_msys.clk,
  452. .ctrlbit = (1 << 5),
  453. .enable = s5pv210_clk_ip0_ctrl,
  454. .ops = &clk_hclk_imem_ops,
  455. }, {
  456. .name = "uart",
  457. .devname = "s5pv210-uart.0",
  458. .parent = &clk_pclk_psys.clk,
  459. .enable = s5pv210_clk_ip3_ctrl,
  460. .ctrlbit = (1 << 17),
  461. }, {
  462. .name = "uart",
  463. .devname = "s5pv210-uart.1",
  464. .parent = &clk_pclk_psys.clk,
  465. .enable = s5pv210_clk_ip3_ctrl,
  466. .ctrlbit = (1 << 18),
  467. }, {
  468. .name = "uart",
  469. .devname = "s5pv210-uart.2",
  470. .parent = &clk_pclk_psys.clk,
  471. .enable = s5pv210_clk_ip3_ctrl,
  472. .ctrlbit = (1 << 19),
  473. }, {
  474. .name = "uart",
  475. .devname = "s5pv210-uart.3",
  476. .parent = &clk_pclk_psys.clk,
  477. .enable = s5pv210_clk_ip3_ctrl,
  478. .ctrlbit = (1 << 20),
  479. }, {
  480. .name = "sromc",
  481. .parent = &clk_hclk_psys.clk,
  482. .enable = s5pv210_clk_ip1_ctrl,
  483. .ctrlbit = (1 << 26),
  484. },
  485. };
  486. static struct clk clk_hsmmc0 = {
  487. .name = "hsmmc",
  488. .devname = "s3c-sdhci.0",
  489. .parent = &clk_hclk_psys.clk,
  490. .enable = s5pv210_clk_ip2_ctrl,
  491. .ctrlbit = (1<<16),
  492. };
  493. static struct clk clk_hsmmc1 = {
  494. .name = "hsmmc",
  495. .devname = "s3c-sdhci.1",
  496. .parent = &clk_hclk_psys.clk,
  497. .enable = s5pv210_clk_ip2_ctrl,
  498. .ctrlbit = (1<<17),
  499. };
  500. static struct clk clk_hsmmc2 = {
  501. .name = "hsmmc",
  502. .devname = "s3c-sdhci.2",
  503. .parent = &clk_hclk_psys.clk,
  504. .enable = s5pv210_clk_ip2_ctrl,
  505. .ctrlbit = (1<<18),
  506. };
  507. static struct clk clk_hsmmc3 = {
  508. .name = "hsmmc",
  509. .devname = "s3c-sdhci.3",
  510. .parent = &clk_hclk_psys.clk,
  511. .enable = s5pv210_clk_ip2_ctrl,
  512. .ctrlbit = (1<<19),
  513. };
  514. static struct clk *clkset_uart_list[] = {
  515. [6] = &clk_mout_mpll.clk,
  516. [7] = &clk_mout_epll.clk,
  517. };
  518. static struct clksrc_sources clkset_uart = {
  519. .sources = clkset_uart_list,
  520. .nr_sources = ARRAY_SIZE(clkset_uart_list),
  521. };
  522. static struct clk *clkset_group1_list[] = {
  523. [0] = &clk_sclk_a2m.clk,
  524. [1] = &clk_mout_mpll.clk,
  525. [2] = &clk_mout_epll.clk,
  526. [3] = &clk_sclk_vpll.clk,
  527. };
  528. static struct clksrc_sources clkset_group1 = {
  529. .sources = clkset_group1_list,
  530. .nr_sources = ARRAY_SIZE(clkset_group1_list),
  531. };
  532. static struct clk *clkset_sclk_onenand_list[] = {
  533. [0] = &clk_hclk_psys.clk,
  534. [1] = &clk_hclk_dsys.clk,
  535. };
  536. static struct clksrc_sources clkset_sclk_onenand = {
  537. .sources = clkset_sclk_onenand_list,
  538. .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list),
  539. };
  540. static struct clk *clkset_sclk_dac_list[] = {
  541. [0] = &clk_sclk_vpll.clk,
  542. [1] = &clk_sclk_hdmiphy,
  543. };
  544. static struct clksrc_sources clkset_sclk_dac = {
  545. .sources = clkset_sclk_dac_list,
  546. .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
  547. };
  548. static struct clksrc_clk clk_sclk_dac = {
  549. .clk = {
  550. .name = "sclk_dac",
  551. .enable = s5pv210_clk_mask0_ctrl,
  552. .ctrlbit = (1 << 2),
  553. },
  554. .sources = &clkset_sclk_dac,
  555. .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
  556. };
  557. static struct clksrc_clk clk_sclk_pixel = {
  558. .clk = {
  559. .name = "sclk_pixel",
  560. .parent = &clk_sclk_vpll.clk,
  561. },
  562. .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
  563. };
  564. static struct clk *clkset_sclk_hdmi_list[] = {
  565. [0] = &clk_sclk_pixel.clk,
  566. [1] = &clk_sclk_hdmiphy,
  567. };
  568. static struct clksrc_sources clkset_sclk_hdmi = {
  569. .sources = clkset_sclk_hdmi_list,
  570. .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
  571. };
  572. static struct clksrc_clk clk_sclk_hdmi = {
  573. .clk = {
  574. .name = "sclk_hdmi",
  575. .enable = s5pv210_clk_mask0_ctrl,
  576. .ctrlbit = (1 << 0),
  577. },
  578. .sources = &clkset_sclk_hdmi,
  579. .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
  580. };
  581. static struct clk *clkset_sclk_mixer_list[] = {
  582. [0] = &clk_sclk_dac.clk,
  583. [1] = &clk_sclk_hdmi.clk,
  584. };
  585. static struct clksrc_sources clkset_sclk_mixer = {
  586. .sources = clkset_sclk_mixer_list,
  587. .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
  588. };
  589. static struct clksrc_clk clk_sclk_mixer = {
  590. .clk = {
  591. .name = "sclk_mixer",
  592. .enable = s5pv210_clk_mask0_ctrl,
  593. .ctrlbit = (1 << 1),
  594. },
  595. .sources = &clkset_sclk_mixer,
  596. .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
  597. };
  598. static struct clksrc_clk *sclk_tv[] = {
  599. &clk_sclk_dac,
  600. &clk_sclk_pixel,
  601. &clk_sclk_hdmi,
  602. &clk_sclk_mixer,
  603. };
  604. static struct clk *clkset_sclk_audio0_list[] = {
  605. [0] = &clk_ext_xtal_mux,
  606. [1] = &clk_pcmcdclk0,
  607. [2] = &clk_sclk_hdmi27m,
  608. [3] = &clk_sclk_usbphy0,
  609. [4] = &clk_sclk_usbphy1,
  610. [5] = &clk_sclk_hdmiphy,
  611. [6] = &clk_mout_mpll.clk,
  612. [7] = &clk_mout_epll.clk,
  613. [8] = &clk_sclk_vpll.clk,
  614. };
  615. static struct clksrc_sources clkset_sclk_audio0 = {
  616. .sources = clkset_sclk_audio0_list,
  617. .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
  618. };
  619. static struct clksrc_clk clk_sclk_audio0 = {
  620. .clk = {
  621. .name = "sclk_audio",
  622. .devname = "soc-audio.0",
  623. .enable = s5pv210_clk_mask0_ctrl,
  624. .ctrlbit = (1 << 24),
  625. },
  626. .sources = &clkset_sclk_audio0,
  627. .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
  628. .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
  629. };
  630. static struct clk *clkset_sclk_audio1_list[] = {
  631. [0] = &clk_ext_xtal_mux,
  632. [1] = &clk_pcmcdclk1,
  633. [2] = &clk_sclk_hdmi27m,
  634. [3] = &clk_sclk_usbphy0,
  635. [4] = &clk_sclk_usbphy1,
  636. [5] = &clk_sclk_hdmiphy,
  637. [6] = &clk_mout_mpll.clk,
  638. [7] = &clk_mout_epll.clk,
  639. [8] = &clk_sclk_vpll.clk,
  640. };
  641. static struct clksrc_sources clkset_sclk_audio1 = {
  642. .sources = clkset_sclk_audio1_list,
  643. .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list),
  644. };
  645. static struct clksrc_clk clk_sclk_audio1 = {
  646. .clk = {
  647. .name = "sclk_audio",
  648. .devname = "soc-audio.1",
  649. .enable = s5pv210_clk_mask0_ctrl,
  650. .ctrlbit = (1 << 25),
  651. },
  652. .sources = &clkset_sclk_audio1,
  653. .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
  654. .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
  655. };
  656. static struct clk *clkset_sclk_audio2_list[] = {
  657. [0] = &clk_ext_xtal_mux,
  658. [1] = &clk_pcmcdclk0,
  659. [2] = &clk_sclk_hdmi27m,
  660. [3] = &clk_sclk_usbphy0,
  661. [4] = &clk_sclk_usbphy1,
  662. [5] = &clk_sclk_hdmiphy,
  663. [6] = &clk_mout_mpll.clk,
  664. [7] = &clk_mout_epll.clk,
  665. [8] = &clk_sclk_vpll.clk,
  666. };
  667. static struct clksrc_sources clkset_sclk_audio2 = {
  668. .sources = clkset_sclk_audio2_list,
  669. .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list),
  670. };
  671. static struct clksrc_clk clk_sclk_audio2 = {
  672. .clk = {
  673. .name = "sclk_audio",
  674. .devname = "soc-audio.2",
  675. .enable = s5pv210_clk_mask0_ctrl,
  676. .ctrlbit = (1 << 26),
  677. },
  678. .sources = &clkset_sclk_audio2,
  679. .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
  680. .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
  681. };
  682. static struct clk *clkset_sclk_spdif_list[] = {
  683. [0] = &clk_sclk_audio0.clk,
  684. [1] = &clk_sclk_audio1.clk,
  685. [2] = &clk_sclk_audio2.clk,
  686. };
  687. static struct clksrc_sources clkset_sclk_spdif = {
  688. .sources = clkset_sclk_spdif_list,
  689. .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
  690. };
  691. static struct clksrc_clk clk_sclk_spdif = {
  692. .clk = {
  693. .name = "sclk_spdif",
  694. .enable = s5pv210_clk_mask0_ctrl,
  695. .ctrlbit = (1 << 27),
  696. .ops = &s5p_sclk_spdif_ops,
  697. },
  698. .sources = &clkset_sclk_spdif,
  699. .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
  700. };
  701. static struct clk *clkset_group2_list[] = {
  702. [0] = &clk_ext_xtal_mux,
  703. [1] = &clk_xusbxti,
  704. [2] = &clk_sclk_hdmi27m,
  705. [3] = &clk_sclk_usbphy0,
  706. [4] = &clk_sclk_usbphy1,
  707. [5] = &clk_sclk_hdmiphy,
  708. [6] = &clk_mout_mpll.clk,
  709. [7] = &clk_mout_epll.clk,
  710. [8] = &clk_sclk_vpll.clk,
  711. };
  712. static struct clksrc_sources clkset_group2 = {
  713. .sources = clkset_group2_list,
  714. .nr_sources = ARRAY_SIZE(clkset_group2_list),
  715. };
  716. static struct clksrc_clk clksrcs[] = {
  717. {
  718. .clk = {
  719. .name = "sclk_dmc",
  720. },
  721. .sources = &clkset_group1,
  722. .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
  723. .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
  724. }, {
  725. .clk = {
  726. .name = "sclk_onenand",
  727. },
  728. .sources = &clkset_sclk_onenand,
  729. .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
  730. .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
  731. }, {
  732. .clk = {
  733. .name = "sclk_fimc",
  734. .devname = "s5pv210-fimc.0",
  735. .enable = s5pv210_clk_mask1_ctrl,
  736. .ctrlbit = (1 << 2),
  737. },
  738. .sources = &clkset_group2,
  739. .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
  740. .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
  741. }, {
  742. .clk = {
  743. .name = "sclk_fimc",
  744. .devname = "s5pv210-fimc.1",
  745. .enable = s5pv210_clk_mask1_ctrl,
  746. .ctrlbit = (1 << 3),
  747. },
  748. .sources = &clkset_group2,
  749. .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
  750. .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
  751. }, {
  752. .clk = {
  753. .name = "sclk_fimc",
  754. .devname = "s5pv210-fimc.2",
  755. .enable = s5pv210_clk_mask1_ctrl,
  756. .ctrlbit = (1 << 4),
  757. },
  758. .sources = &clkset_group2,
  759. .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
  760. .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
  761. }, {
  762. .clk = {
  763. .name = "sclk_cam0",
  764. .enable = s5pv210_clk_mask0_ctrl,
  765. .ctrlbit = (1 << 3),
  766. },
  767. .sources = &clkset_group2,
  768. .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
  769. .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
  770. }, {
  771. .clk = {
  772. .name = "sclk_cam1",
  773. .enable = s5pv210_clk_mask0_ctrl,
  774. .ctrlbit = (1 << 4),
  775. },
  776. .sources = &clkset_group2,
  777. .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
  778. .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
  779. }, {
  780. .clk = {
  781. .name = "sclk_fimd",
  782. .enable = s5pv210_clk_mask0_ctrl,
  783. .ctrlbit = (1 << 5),
  784. },
  785. .sources = &clkset_group2,
  786. .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
  787. .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
  788. }, {
  789. .clk = {
  790. .name = "sclk_mfc",
  791. .devname = "s5p-mfc",
  792. .enable = s5pv210_clk_ip0_ctrl,
  793. .ctrlbit = (1 << 16),
  794. },
  795. .sources = &clkset_group1,
  796. .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
  797. .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
  798. }, {
  799. .clk = {
  800. .name = "sclk_g2d",
  801. .enable = s5pv210_clk_ip0_ctrl,
  802. .ctrlbit = (1 << 12),
  803. },
  804. .sources = &clkset_group1,
  805. .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
  806. .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
  807. }, {
  808. .clk = {
  809. .name = "sclk_g3d",
  810. .enable = s5pv210_clk_ip0_ctrl,
  811. .ctrlbit = (1 << 8),
  812. },
  813. .sources = &clkset_group1,
  814. .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
  815. .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
  816. }, {
  817. .clk = {
  818. .name = "sclk_csis",
  819. .enable = s5pv210_clk_mask0_ctrl,
  820. .ctrlbit = (1 << 6),
  821. },
  822. .sources = &clkset_group2,
  823. .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
  824. .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
  825. }, {
  826. .clk = {
  827. .name = "sclk_pwi",
  828. .enable = s5pv210_clk_mask0_ctrl,
  829. .ctrlbit = (1 << 29),
  830. },
  831. .sources = &clkset_group2,
  832. .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
  833. .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
  834. }, {
  835. .clk = {
  836. .name = "sclk_pwm",
  837. .enable = s5pv210_clk_mask0_ctrl,
  838. .ctrlbit = (1 << 19),
  839. },
  840. .sources = &clkset_group2,
  841. .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
  842. .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
  843. },
  844. };
  845. static struct clksrc_clk clk_sclk_uart0 = {
  846. .clk = {
  847. .name = "uclk1",
  848. .devname = "s5pv210-uart.0",
  849. .enable = s5pv210_clk_mask0_ctrl,
  850. .ctrlbit = (1 << 12),
  851. },
  852. .sources = &clkset_uart,
  853. .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
  854. .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
  855. };
  856. static struct clksrc_clk clk_sclk_uart1 = {
  857. .clk = {
  858. .name = "uclk1",
  859. .devname = "s5pv210-uart.1",
  860. .enable = s5pv210_clk_mask0_ctrl,
  861. .ctrlbit = (1 << 13),
  862. },
  863. .sources = &clkset_uart,
  864. .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
  865. .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
  866. };
  867. static struct clksrc_clk clk_sclk_uart2 = {
  868. .clk = {
  869. .name = "uclk1",
  870. .devname = "s5pv210-uart.2",
  871. .enable = s5pv210_clk_mask0_ctrl,
  872. .ctrlbit = (1 << 14),
  873. },
  874. .sources = &clkset_uart,
  875. .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
  876. .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
  877. };
  878. static struct clksrc_clk clk_sclk_uart3 = {
  879. .clk = {
  880. .name = "uclk1",
  881. .devname = "s5pv210-uart.3",
  882. .enable = s5pv210_clk_mask0_ctrl,
  883. .ctrlbit = (1 << 15),
  884. },
  885. .sources = &clkset_uart,
  886. .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
  887. .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
  888. };
  889. static struct clksrc_clk clk_sclk_mmc0 = {
  890. .clk = {
  891. .name = "sclk_mmc",
  892. .devname = "s3c-sdhci.0",
  893. .enable = s5pv210_clk_mask0_ctrl,
  894. .ctrlbit = (1 << 8),
  895. },
  896. .sources = &clkset_group2,
  897. .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
  898. .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
  899. };
  900. static struct clksrc_clk clk_sclk_mmc1 = {
  901. .clk = {
  902. .name = "sclk_mmc",
  903. .devname = "s3c-sdhci.1",
  904. .enable = s5pv210_clk_mask0_ctrl,
  905. .ctrlbit = (1 << 9),
  906. },
  907. .sources = &clkset_group2,
  908. .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
  909. .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
  910. };
  911. static struct clksrc_clk clk_sclk_mmc2 = {
  912. .clk = {
  913. .name = "sclk_mmc",
  914. .devname = "s3c-sdhci.2",
  915. .enable = s5pv210_clk_mask0_ctrl,
  916. .ctrlbit = (1 << 10),
  917. },
  918. .sources = &clkset_group2,
  919. .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
  920. .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
  921. };
  922. static struct clksrc_clk clk_sclk_mmc3 = {
  923. .clk = {
  924. .name = "sclk_mmc",
  925. .devname = "s3c-sdhci.3",
  926. .enable = s5pv210_clk_mask0_ctrl,
  927. .ctrlbit = (1 << 11),
  928. },
  929. .sources = &clkset_group2,
  930. .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
  931. .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
  932. };
  933. static struct clksrc_clk clk_sclk_spi0 = {
  934. .clk = {
  935. .name = "sclk_spi",
  936. .devname = "s3c64xx-spi.0",
  937. .enable = s5pv210_clk_mask0_ctrl,
  938. .ctrlbit = (1 << 16),
  939. },
  940. .sources = &clkset_group2,
  941. .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
  942. .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
  943. };
  944. static struct clksrc_clk clk_sclk_spi1 = {
  945. .clk = {
  946. .name = "sclk_spi",
  947. .devname = "s3c64xx-spi.1",
  948. .enable = s5pv210_clk_mask0_ctrl,
  949. .ctrlbit = (1 << 17),
  950. },
  951. .sources = &clkset_group2,
  952. .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
  953. .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
  954. };
  955. static struct clksrc_clk *clksrc_cdev[] = {
  956. &clk_sclk_uart0,
  957. &clk_sclk_uart1,
  958. &clk_sclk_uart2,
  959. &clk_sclk_uart3,
  960. &clk_sclk_mmc0,
  961. &clk_sclk_mmc1,
  962. &clk_sclk_mmc2,
  963. &clk_sclk_mmc3,
  964. &clk_sclk_spi0,
  965. &clk_sclk_spi1,
  966. };
  967. static struct clk *clk_cdev[] = {
  968. &clk_hsmmc0,
  969. &clk_hsmmc1,
  970. &clk_hsmmc2,
  971. &clk_hsmmc3,
  972. };
  973. /* Clock initialisation code */
  974. static struct clksrc_clk *sysclks[] = {
  975. &clk_mout_apll,
  976. &clk_mout_epll,
  977. &clk_mout_mpll,
  978. &clk_armclk,
  979. &clk_hclk_msys,
  980. &clk_sclk_a2m,
  981. &clk_hclk_dsys,
  982. &clk_hclk_psys,
  983. &clk_pclk_msys,
  984. &clk_pclk_dsys,
  985. &clk_pclk_psys,
  986. &clk_vpllsrc,
  987. &clk_sclk_vpll,
  988. &clk_mout_dmc0,
  989. &clk_sclk_dmc0,
  990. &clk_sclk_audio0,
  991. &clk_sclk_audio1,
  992. &clk_sclk_audio2,
  993. &clk_sclk_spdif,
  994. };
  995. static u32 epll_div[][6] = {
  996. { 48000000, 0, 48, 3, 3, 0 },
  997. { 96000000, 0, 48, 3, 2, 0 },
  998. { 144000000, 1, 72, 3, 2, 0 },
  999. { 192000000, 0, 48, 3, 1, 0 },
  1000. { 288000000, 1, 72, 3, 1, 0 },
  1001. { 32750000, 1, 65, 3, 4, 35127 },
  1002. { 32768000, 1, 65, 3, 4, 35127 },
  1003. { 45158400, 0, 45, 3, 3, 10355 },
  1004. { 45000000, 0, 45, 3, 3, 10355 },
  1005. { 45158000, 0, 45, 3, 3, 10355 },
  1006. { 49125000, 0, 49, 3, 3, 9961 },
  1007. { 49152000, 0, 49, 3, 3, 9961 },
  1008. { 67737600, 1, 67, 3, 3, 48366 },
  1009. { 67738000, 1, 67, 3, 3, 48366 },
  1010. { 73800000, 1, 73, 3, 3, 47710 },
  1011. { 73728000, 1, 73, 3, 3, 47710 },
  1012. { 36000000, 1, 32, 3, 4, 0 },
  1013. { 60000000, 1, 60, 3, 3, 0 },
  1014. { 72000000, 1, 72, 3, 3, 0 },
  1015. { 80000000, 1, 80, 3, 3, 0 },
  1016. { 84000000, 0, 42, 3, 2, 0 },
  1017. { 50000000, 0, 50, 3, 3, 0 },
  1018. };
  1019. static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
  1020. {
  1021. unsigned int epll_con, epll_con_k;
  1022. unsigned int i;
  1023. /* Return if nothing changed */
  1024. if (clk->rate == rate)
  1025. return 0;
  1026. epll_con = __raw_readl(S5P_EPLL_CON);
  1027. epll_con_k = __raw_readl(S5P_EPLL_CON1);
  1028. epll_con_k &= ~PLL46XX_KDIV_MASK;
  1029. epll_con &= ~(1 << 27 |
  1030. PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
  1031. PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
  1032. PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
  1033. for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
  1034. if (epll_div[i][0] == rate) {
  1035. epll_con_k |= epll_div[i][5] << 0;
  1036. epll_con |= (epll_div[i][1] << 27 |
  1037. epll_div[i][2] << PLL46XX_MDIV_SHIFT |
  1038. epll_div[i][3] << PLL46XX_PDIV_SHIFT |
  1039. epll_div[i][4] << PLL46XX_SDIV_SHIFT);
  1040. break;
  1041. }
  1042. }
  1043. if (i == ARRAY_SIZE(epll_div)) {
  1044. printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
  1045. __func__);
  1046. return -EINVAL;
  1047. }
  1048. __raw_writel(epll_con, S5P_EPLL_CON);
  1049. __raw_writel(epll_con_k, S5P_EPLL_CON1);
  1050. printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
  1051. clk->rate, rate);
  1052. clk->rate = rate;
  1053. return 0;
  1054. }
  1055. static struct clk_ops s5pv210_epll_ops = {
  1056. .set_rate = s5pv210_epll_set_rate,
  1057. .get_rate = s5p_epll_get_rate,
  1058. };
  1059. static u32 vpll_div[][5] = {
  1060. { 54000000, 3, 53, 3, 0 },
  1061. { 108000000, 3, 53, 2, 0 },
  1062. };
  1063. static unsigned long s5pv210_vpll_get_rate(struct clk *clk)
  1064. {
  1065. return clk->rate;
  1066. }
  1067. static int s5pv210_vpll_set_rate(struct clk *clk, unsigned long rate)
  1068. {
  1069. unsigned int vpll_con;
  1070. unsigned int i;
  1071. /* Return if nothing changed */
  1072. if (clk->rate == rate)
  1073. return 0;
  1074. vpll_con = __raw_readl(S5P_VPLL_CON);
  1075. vpll_con &= ~(0x1 << 27 | \
  1076. PLL90XX_MDIV_MASK << PLL90XX_MDIV_SHIFT | \
  1077. PLL90XX_PDIV_MASK << PLL90XX_PDIV_SHIFT | \
  1078. PLL90XX_SDIV_MASK << PLL90XX_SDIV_SHIFT);
  1079. for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
  1080. if (vpll_div[i][0] == rate) {
  1081. vpll_con |= vpll_div[i][1] << PLL90XX_PDIV_SHIFT;
  1082. vpll_con |= vpll_div[i][2] << PLL90XX_MDIV_SHIFT;
  1083. vpll_con |= vpll_div[i][3] << PLL90XX_SDIV_SHIFT;
  1084. vpll_con |= vpll_div[i][4] << 27;
  1085. break;
  1086. }
  1087. }
  1088. if (i == ARRAY_SIZE(vpll_div)) {
  1089. printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
  1090. __func__);
  1091. return -EINVAL;
  1092. }
  1093. __raw_writel(vpll_con, S5P_VPLL_CON);
  1094. /* Wait for VPLL lock */
  1095. while (!(__raw_readl(S5P_VPLL_CON) & (1 << PLL90XX_LOCKED_SHIFT)))
  1096. continue;
  1097. clk->rate = rate;
  1098. return 0;
  1099. }
  1100. static struct clk_ops s5pv210_vpll_ops = {
  1101. .get_rate = s5pv210_vpll_get_rate,
  1102. .set_rate = s5pv210_vpll_set_rate,
  1103. };
  1104. void __init_or_cpufreq s5pv210_setup_clocks(void)
  1105. {
  1106. struct clk *xtal_clk;
  1107. unsigned long vpllsrc;
  1108. unsigned long armclk;
  1109. unsigned long hclk_msys;
  1110. unsigned long hclk_dsys;
  1111. unsigned long hclk_psys;
  1112. unsigned long pclk_msys;
  1113. unsigned long pclk_dsys;
  1114. unsigned long pclk_psys;
  1115. unsigned long apll;
  1116. unsigned long mpll;
  1117. unsigned long epll;
  1118. unsigned long vpll;
  1119. unsigned int ptr;
  1120. u32 clkdiv0, clkdiv1;
  1121. /* Set functions for clk_fout_epll */
  1122. clk_fout_epll.enable = s5p_epll_enable;
  1123. clk_fout_epll.ops = &s5pv210_epll_ops;
  1124. printk(KERN_DEBUG "%s: registering clocks\n", __func__);
  1125. clkdiv0 = __raw_readl(S5P_CLK_DIV0);
  1126. clkdiv1 = __raw_readl(S5P_CLK_DIV1);
  1127. printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
  1128. __func__, clkdiv0, clkdiv1);
  1129. xtal_clk = clk_get(NULL, "xtal");
  1130. BUG_ON(IS_ERR(xtal_clk));
  1131. xtal = clk_get_rate(xtal_clk);
  1132. clk_put(xtal_clk);
  1133. printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
  1134. apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
  1135. mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
  1136. epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
  1137. __raw_readl(S5P_EPLL_CON1), pll_4600);
  1138. vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
  1139. vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
  1140. clk_fout_apll.ops = &clk_fout_apll_ops;
  1141. clk_fout_mpll.rate = mpll;
  1142. clk_fout_epll.rate = epll;
  1143. clk_fout_vpll.ops = &s5pv210_vpll_ops;
  1144. clk_fout_vpll.rate = vpll;
  1145. printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
  1146. apll, mpll, epll, vpll);
  1147. armclk = clk_get_rate(&clk_armclk.clk);
  1148. hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
  1149. hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
  1150. hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
  1151. pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
  1152. pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
  1153. pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
  1154. printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
  1155. "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
  1156. armclk, hclk_msys, hclk_dsys, hclk_psys,
  1157. pclk_msys, pclk_dsys, pclk_psys);
  1158. clk_f.rate = armclk;
  1159. clk_h.rate = hclk_psys;
  1160. clk_p.rate = pclk_psys;
  1161. for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
  1162. s3c_set_clksrc(&clksrcs[ptr], true);
  1163. }
  1164. static struct clk *clks[] __initdata = {
  1165. &clk_sclk_hdmi27m,
  1166. &clk_sclk_hdmiphy,
  1167. &clk_sclk_usbphy0,
  1168. &clk_sclk_usbphy1,
  1169. &clk_pcmcdclk0,
  1170. &clk_pcmcdclk1,
  1171. &clk_pcmcdclk2,
  1172. };
  1173. static struct clk_lookup s5pv210_clk_lookup[] = {
  1174. CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
  1175. CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk),
  1176. CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
  1177. CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
  1178. CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
  1179. CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
  1180. CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
  1181. CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
  1182. CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
  1183. CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
  1184. CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
  1185. CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
  1186. CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
  1187. CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
  1188. CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
  1189. CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
  1190. };
  1191. void __init s5pv210_register_clocks(void)
  1192. {
  1193. int ptr;
  1194. s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
  1195. for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
  1196. s3c_register_clksrc(sysclks[ptr], 1);
  1197. for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
  1198. s3c_register_clksrc(sclk_tv[ptr], 1);
  1199. for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
  1200. s3c_register_clksrc(clksrc_cdev[ptr], 1);
  1201. s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
  1202. s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
  1203. s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
  1204. s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
  1205. clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
  1206. s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
  1207. for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
  1208. s3c_disable_clocks(clk_cdev[ptr], 1);
  1209. s3c24xx_register_clock(&dummy_apb_pclk);
  1210. s3c_pwmclk_init();
  1211. }