common.c 10 KB

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  1. /*
  2. * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
  3. * http://www.samsung.com
  4. *
  5. * Common Codes for S5P64X0 machines
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/types.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/list.h>
  15. #include <linux/timer.h>
  16. #include <linux/init.h>
  17. #include <linux/clk.h>
  18. #include <linux/io.h>
  19. #include <linux/device.h>
  20. #include <linux/serial_core.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/sched.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/gpio.h>
  25. #include <linux/irq.h>
  26. #include <asm/irq.h>
  27. #include <asm/proc-fns.h>
  28. #include <asm/mach/arch.h>
  29. #include <asm/mach/map.h>
  30. #include <asm/mach/irq.h>
  31. #include <mach/map.h>
  32. #include <mach/hardware.h>
  33. #include <mach/regs-clock.h>
  34. #include <mach/regs-gpio.h>
  35. #include <plat/cpu.h>
  36. #include <plat/clock.h>
  37. #include <plat/devs.h>
  38. #include <plat/pm.h>
  39. #include <plat/sdhci.h>
  40. #include <plat/adc-core.h>
  41. #include <plat/fb-core.h>
  42. #include <plat/gpio-cfg.h>
  43. #include <plat/regs-irqtype.h>
  44. #include <plat/regs-serial.h>
  45. #include <plat/watchdog-reset.h>
  46. #include "common.h"
  47. static const char name_s5p6440[] = "S5P6440";
  48. static const char name_s5p6450[] = "S5P6450";
  49. static struct cpu_table cpu_ids[] __initdata = {
  50. {
  51. .idcode = S5P6440_CPU_ID,
  52. .idmask = S5P64XX_CPU_MASK,
  53. .map_io = s5p6440_map_io,
  54. .init_clocks = s5p6440_init_clocks,
  55. .init_uarts = s5p6440_init_uarts,
  56. .init = s5p64x0_init,
  57. .name = name_s5p6440,
  58. }, {
  59. .idcode = S5P6450_CPU_ID,
  60. .idmask = S5P64XX_CPU_MASK,
  61. .map_io = s5p6450_map_io,
  62. .init_clocks = s5p6450_init_clocks,
  63. .init_uarts = s5p6450_init_uarts,
  64. .init = s5p64x0_init,
  65. .name = name_s5p6450,
  66. },
  67. };
  68. /* Initial IO mappings */
  69. static struct map_desc s5p64x0_iodesc[] __initdata = {
  70. {
  71. .virtual = (unsigned long)S5P_VA_CHIPID,
  72. .pfn = __phys_to_pfn(S5P64X0_PA_CHIPID),
  73. .length = SZ_4K,
  74. .type = MT_DEVICE,
  75. }, {
  76. .virtual = (unsigned long)S3C_VA_SYS,
  77. .pfn = __phys_to_pfn(S5P64X0_PA_SYSCON),
  78. .length = SZ_64K,
  79. .type = MT_DEVICE,
  80. }, {
  81. .virtual = (unsigned long)S3C_VA_TIMER,
  82. .pfn = __phys_to_pfn(S5P64X0_PA_TIMER),
  83. .length = SZ_16K,
  84. .type = MT_DEVICE,
  85. }, {
  86. .virtual = (unsigned long)S3C_VA_WATCHDOG,
  87. .pfn = __phys_to_pfn(S5P64X0_PA_WDT),
  88. .length = SZ_4K,
  89. .type = MT_DEVICE,
  90. }, {
  91. .virtual = (unsigned long)S5P_VA_SROMC,
  92. .pfn = __phys_to_pfn(S5P64X0_PA_SROMC),
  93. .length = SZ_4K,
  94. .type = MT_DEVICE,
  95. }, {
  96. .virtual = (unsigned long)S5P_VA_GPIO,
  97. .pfn = __phys_to_pfn(S5P64X0_PA_GPIO),
  98. .length = SZ_4K,
  99. .type = MT_DEVICE,
  100. }, {
  101. .virtual = (unsigned long)VA_VIC0,
  102. .pfn = __phys_to_pfn(S5P64X0_PA_VIC0),
  103. .length = SZ_16K,
  104. .type = MT_DEVICE,
  105. }, {
  106. .virtual = (unsigned long)VA_VIC1,
  107. .pfn = __phys_to_pfn(S5P64X0_PA_VIC1),
  108. .length = SZ_16K,
  109. .type = MT_DEVICE,
  110. },
  111. };
  112. static struct map_desc s5p6440_iodesc[] __initdata = {
  113. {
  114. .virtual = (unsigned long)S3C_VA_UART,
  115. .pfn = __phys_to_pfn(S5P6440_PA_UART(0)),
  116. .length = SZ_4K,
  117. .type = MT_DEVICE,
  118. },
  119. };
  120. static struct map_desc s5p6450_iodesc[] __initdata = {
  121. {
  122. .virtual = (unsigned long)S3C_VA_UART,
  123. .pfn = __phys_to_pfn(S5P6450_PA_UART(0)),
  124. .length = SZ_512K,
  125. .type = MT_DEVICE,
  126. }, {
  127. .virtual = (unsigned long)S3C_VA_UART + SZ_512K,
  128. .pfn = __phys_to_pfn(S5P6450_PA_UART(5)),
  129. .length = SZ_4K,
  130. .type = MT_DEVICE,
  131. },
  132. };
  133. static void s5p64x0_idle(void)
  134. {
  135. unsigned long val;
  136. if (!need_resched()) {
  137. val = __raw_readl(S5P64X0_PWR_CFG);
  138. val &= ~(0x3 << 5);
  139. val |= (0x1 << 5);
  140. __raw_writel(val, S5P64X0_PWR_CFG);
  141. cpu_do_idle();
  142. }
  143. local_irq_enable();
  144. }
  145. /*
  146. * s5p64x0_map_io
  147. *
  148. * register the standard CPU IO areas
  149. */
  150. void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
  151. {
  152. /* initialize the io descriptors we need for initialization */
  153. iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
  154. if (mach_desc)
  155. iotable_init(mach_desc, size);
  156. /* detect cpu id and rev. */
  157. s5p_init_cpu(S5P64X0_SYS_ID);
  158. s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
  159. }
  160. void __init s5p6440_map_io(void)
  161. {
  162. /* initialize any device information early */
  163. s3c_adc_setname("s3c64xx-adc");
  164. s3c_fb_setname("s5p64x0-fb");
  165. s5p64x0_default_sdhci0();
  166. s5p64x0_default_sdhci1();
  167. s5p6440_default_sdhci2();
  168. iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
  169. init_consistent_dma_size(SZ_8M);
  170. }
  171. void __init s5p6450_map_io(void)
  172. {
  173. /* initialize any device information early */
  174. s3c_adc_setname("s3c64xx-adc");
  175. s3c_fb_setname("s5p64x0-fb");
  176. s5p64x0_default_sdhci0();
  177. s5p64x0_default_sdhci1();
  178. s5p6450_default_sdhci2();
  179. iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
  180. init_consistent_dma_size(SZ_8M);
  181. }
  182. /*
  183. * s5p64x0_init_clocks
  184. *
  185. * register and setup the CPU clocks
  186. */
  187. void __init s5p6440_init_clocks(int xtal)
  188. {
  189. printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
  190. s3c24xx_register_baseclocks(xtal);
  191. s5p_register_clocks(xtal);
  192. s5p6440_register_clocks();
  193. s5p6440_setup_clocks();
  194. }
  195. void __init s5p6450_init_clocks(int xtal)
  196. {
  197. printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
  198. s3c24xx_register_baseclocks(xtal);
  199. s5p_register_clocks(xtal);
  200. s5p6450_register_clocks();
  201. s5p6450_setup_clocks();
  202. }
  203. /*
  204. * s5p64x0_init_irq
  205. *
  206. * register the CPU interrupts
  207. */
  208. void __init s5p6440_init_irq(void)
  209. {
  210. /* S5P6440 supports 2 VIC */
  211. u32 vic[2];
  212. /*
  213. * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
  214. * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
  215. */
  216. vic[0] = 0xff800ae7;
  217. vic[1] = 0xffbf23e5;
  218. s5p_init_irq(vic, ARRAY_SIZE(vic));
  219. }
  220. void __init s5p6450_init_irq(void)
  221. {
  222. /* S5P6450 supports only 2 VIC */
  223. u32 vic[2];
  224. /*
  225. * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
  226. * VIC1 is missing IRQ VIC1[12, 14, 23]
  227. */
  228. vic[0] = 0xff9f1fff;
  229. vic[1] = 0xff7fafff;
  230. s5p_init_irq(vic, ARRAY_SIZE(vic));
  231. }
  232. struct bus_type s5p64x0_subsys = {
  233. .name = "s5p64x0-core",
  234. .dev_name = "s5p64x0-core",
  235. };
  236. static struct device s5p64x0_dev = {
  237. .bus = &s5p64x0_subsys,
  238. };
  239. static int __init s5p64x0_core_init(void)
  240. {
  241. return subsys_system_register(&s5p64x0_subsys, NULL);
  242. }
  243. core_initcall(s5p64x0_core_init);
  244. int __init s5p64x0_init(void)
  245. {
  246. printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
  247. /* set idle function */
  248. pm_idle = s5p64x0_idle;
  249. return device_register(&s5p64x0_dev);
  250. }
  251. /* uart registration process */
  252. void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  253. {
  254. int uart;
  255. for (uart = 0; uart < no; uart++) {
  256. s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
  257. s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
  258. }
  259. s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
  260. }
  261. void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  262. {
  263. s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
  264. }
  265. #define eint_offset(irq) ((irq) - IRQ_EINT(0))
  266. static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
  267. {
  268. int offs = eint_offset(data->irq);
  269. int shift;
  270. u32 ctrl, mask;
  271. u32 newvalue = 0;
  272. if (offs > 15)
  273. return -EINVAL;
  274. switch (type) {
  275. case IRQ_TYPE_NONE:
  276. printk(KERN_WARNING "No edge setting!\n");
  277. break;
  278. case IRQ_TYPE_EDGE_RISING:
  279. newvalue = S3C2410_EXTINT_RISEEDGE;
  280. break;
  281. case IRQ_TYPE_EDGE_FALLING:
  282. newvalue = S3C2410_EXTINT_FALLEDGE;
  283. break;
  284. case IRQ_TYPE_EDGE_BOTH:
  285. newvalue = S3C2410_EXTINT_BOTHEDGE;
  286. break;
  287. case IRQ_TYPE_LEVEL_LOW:
  288. newvalue = S3C2410_EXTINT_LOWLEV;
  289. break;
  290. case IRQ_TYPE_LEVEL_HIGH:
  291. newvalue = S3C2410_EXTINT_HILEV;
  292. break;
  293. default:
  294. printk(KERN_ERR "No such irq type %d", type);
  295. return -EINVAL;
  296. }
  297. shift = (offs / 2) * 4;
  298. mask = 0x7 << shift;
  299. ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
  300. ctrl |= newvalue << shift;
  301. __raw_writel(ctrl, S5P64X0_EINT0CON0);
  302. /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
  303. if (soc_is_s5p6450())
  304. s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
  305. else
  306. s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
  307. return 0;
  308. }
  309. /*
  310. * s5p64x0_irq_demux_eint
  311. *
  312. * This function demuxes the IRQ from the group0 external interrupts,
  313. * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
  314. * the specific handlers s5p64x0_irq_demux_eintX_Y.
  315. */
  316. static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
  317. {
  318. u32 status = __raw_readl(S5P64X0_EINT0PEND);
  319. u32 mask = __raw_readl(S5P64X0_EINT0MASK);
  320. unsigned int irq;
  321. status &= ~mask;
  322. status >>= start;
  323. status &= (1 << (end - start + 1)) - 1;
  324. for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
  325. if (status & 1)
  326. generic_handle_irq(irq);
  327. status >>= 1;
  328. }
  329. }
  330. static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
  331. {
  332. s5p64x0_irq_demux_eint(0, 3);
  333. }
  334. static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
  335. {
  336. s5p64x0_irq_demux_eint(4, 11);
  337. }
  338. static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
  339. struct irq_desc *desc)
  340. {
  341. s5p64x0_irq_demux_eint(12, 15);
  342. }
  343. static int s5p64x0_alloc_gc(void)
  344. {
  345. struct irq_chip_generic *gc;
  346. struct irq_chip_type *ct;
  347. gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
  348. S5P_VA_GPIO, handle_level_irq);
  349. if (!gc) {
  350. printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
  351. "external interrupts failed\n", __func__);
  352. return -EINVAL;
  353. }
  354. ct = gc->chip_types;
  355. ct->chip.irq_ack = irq_gc_ack_set_bit;
  356. ct->chip.irq_mask = irq_gc_mask_set_bit;
  357. ct->chip.irq_unmask = irq_gc_mask_clr_bit;
  358. ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
  359. ct->chip.irq_set_wake = s3c_irqext_wake;
  360. ct->regs.ack = EINT0PEND_OFFSET;
  361. ct->regs.mask = EINT0MASK_OFFSET;
  362. irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
  363. IRQ_NOREQUEST | IRQ_NOPROBE, 0);
  364. return 0;
  365. }
  366. static int __init s5p64x0_init_irq_eint(void)
  367. {
  368. int ret = s5p64x0_alloc_gc();
  369. irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
  370. irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
  371. irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
  372. return ret;
  373. }
  374. arch_initcall(s5p64x0_init_irq_eint);
  375. void s5p64x0_restart(char mode, const char *cmd)
  376. {
  377. if (mode != 's')
  378. arch_wdt_reset();
  379. soft_restart(0);
  380. }