devices.c 22 KB

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  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/init.h>
  4. #include <linux/platform_device.h>
  5. #include <linux/dma-mapping.h>
  6. #include <linux/spi/pxa2xx_spi.h>
  7. #include <linux/i2c/pxa-i2c.h>
  8. #include <asm/pmu.h>
  9. #include <mach/udc.h>
  10. #include <mach/pxa3xx-u2d.h>
  11. #include <mach/pxafb.h>
  12. #include <mach/mmc.h>
  13. #include <mach/irda.h>
  14. #include <mach/ohci.h>
  15. #include <plat/pxa27x_keypad.h>
  16. #include <mach/camera.h>
  17. #include <mach/audio.h>
  18. #include <mach/hardware.h>
  19. #include <plat/pxa3xx_nand.h>
  20. #include "devices.h"
  21. #include "generic.h"
  22. void __init pxa_register_device(struct platform_device *dev, void *data)
  23. {
  24. int ret;
  25. dev->dev.platform_data = data;
  26. ret = platform_device_register(dev);
  27. if (ret)
  28. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  29. }
  30. static struct resource pxa_resource_pmu = {
  31. .start = IRQ_PMU,
  32. .end = IRQ_PMU,
  33. .flags = IORESOURCE_IRQ,
  34. };
  35. struct platform_device pxa_device_pmu = {
  36. .name = "arm-pmu",
  37. .id = ARM_PMU_DEVICE_CPU,
  38. .resource = &pxa_resource_pmu,
  39. .num_resources = 1,
  40. };
  41. static struct resource pxamci_resources[] = {
  42. [0] = {
  43. .start = 0x41100000,
  44. .end = 0x41100fff,
  45. .flags = IORESOURCE_MEM,
  46. },
  47. [1] = {
  48. .start = IRQ_MMC,
  49. .end = IRQ_MMC,
  50. .flags = IORESOURCE_IRQ,
  51. },
  52. [2] = {
  53. .start = 21,
  54. .end = 21,
  55. .flags = IORESOURCE_DMA,
  56. },
  57. [3] = {
  58. .start = 22,
  59. .end = 22,
  60. .flags = IORESOURCE_DMA,
  61. },
  62. };
  63. static u64 pxamci_dmamask = 0xffffffffUL;
  64. struct platform_device pxa_device_mci = {
  65. .name = "pxa2xx-mci",
  66. .id = 0,
  67. .dev = {
  68. .dma_mask = &pxamci_dmamask,
  69. .coherent_dma_mask = 0xffffffff,
  70. },
  71. .num_resources = ARRAY_SIZE(pxamci_resources),
  72. .resource = pxamci_resources,
  73. };
  74. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  75. {
  76. pxa_register_device(&pxa_device_mci, info);
  77. }
  78. static struct pxa2xx_udc_mach_info pxa_udc_info = {
  79. .gpio_pullup = -1,
  80. };
  81. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  82. {
  83. memcpy(&pxa_udc_info, info, sizeof *info);
  84. }
  85. static struct resource pxa2xx_udc_resources[] = {
  86. [0] = {
  87. .start = 0x40600000,
  88. .end = 0x4060ffff,
  89. .flags = IORESOURCE_MEM,
  90. },
  91. [1] = {
  92. .start = IRQ_USB,
  93. .end = IRQ_USB,
  94. .flags = IORESOURCE_IRQ,
  95. },
  96. };
  97. static u64 udc_dma_mask = ~(u32)0;
  98. struct platform_device pxa25x_device_udc = {
  99. .name = "pxa25x-udc",
  100. .id = -1,
  101. .resource = pxa2xx_udc_resources,
  102. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  103. .dev = {
  104. .platform_data = &pxa_udc_info,
  105. .dma_mask = &udc_dma_mask,
  106. }
  107. };
  108. struct platform_device pxa27x_device_udc = {
  109. .name = "pxa27x-udc",
  110. .id = -1,
  111. .resource = pxa2xx_udc_resources,
  112. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  113. .dev = {
  114. .platform_data = &pxa_udc_info,
  115. .dma_mask = &udc_dma_mask,
  116. }
  117. };
  118. #ifdef CONFIG_PXA3xx
  119. static struct resource pxa3xx_u2d_resources[] = {
  120. [0] = {
  121. .start = 0x54100000,
  122. .end = 0x54100fff,
  123. .flags = IORESOURCE_MEM,
  124. },
  125. [1] = {
  126. .start = IRQ_USB2,
  127. .end = IRQ_USB2,
  128. .flags = IORESOURCE_IRQ,
  129. },
  130. };
  131. struct platform_device pxa3xx_device_u2d = {
  132. .name = "pxa3xx-u2d",
  133. .id = -1,
  134. .resource = pxa3xx_u2d_resources,
  135. .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
  136. };
  137. void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
  138. {
  139. pxa_register_device(&pxa3xx_device_u2d, info);
  140. }
  141. #endif /* CONFIG_PXA3xx */
  142. static struct resource pxafb_resources[] = {
  143. [0] = {
  144. .start = 0x44000000,
  145. .end = 0x4400ffff,
  146. .flags = IORESOURCE_MEM,
  147. },
  148. [1] = {
  149. .start = IRQ_LCD,
  150. .end = IRQ_LCD,
  151. .flags = IORESOURCE_IRQ,
  152. },
  153. };
  154. static u64 fb_dma_mask = ~(u64)0;
  155. struct platform_device pxa_device_fb = {
  156. .name = "pxa2xx-fb",
  157. .id = -1,
  158. .dev = {
  159. .dma_mask = &fb_dma_mask,
  160. .coherent_dma_mask = 0xffffffff,
  161. },
  162. .num_resources = ARRAY_SIZE(pxafb_resources),
  163. .resource = pxafb_resources,
  164. };
  165. void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
  166. {
  167. pxa_device_fb.dev.parent = parent;
  168. pxa_register_device(&pxa_device_fb, info);
  169. }
  170. static struct resource pxa_resource_ffuart[] = {
  171. {
  172. .start = 0x40100000,
  173. .end = 0x40100023,
  174. .flags = IORESOURCE_MEM,
  175. }, {
  176. .start = IRQ_FFUART,
  177. .end = IRQ_FFUART,
  178. .flags = IORESOURCE_IRQ,
  179. }
  180. };
  181. struct platform_device pxa_device_ffuart = {
  182. .name = "pxa2xx-uart",
  183. .id = 0,
  184. .resource = pxa_resource_ffuart,
  185. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  186. };
  187. void __init pxa_set_ffuart_info(void *info)
  188. {
  189. pxa_register_device(&pxa_device_ffuart, info);
  190. }
  191. static struct resource pxa_resource_btuart[] = {
  192. {
  193. .start = 0x40200000,
  194. .end = 0x40200023,
  195. .flags = IORESOURCE_MEM,
  196. }, {
  197. .start = IRQ_BTUART,
  198. .end = IRQ_BTUART,
  199. .flags = IORESOURCE_IRQ,
  200. }
  201. };
  202. struct platform_device pxa_device_btuart = {
  203. .name = "pxa2xx-uart",
  204. .id = 1,
  205. .resource = pxa_resource_btuart,
  206. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  207. };
  208. void __init pxa_set_btuart_info(void *info)
  209. {
  210. pxa_register_device(&pxa_device_btuart, info);
  211. }
  212. static struct resource pxa_resource_stuart[] = {
  213. {
  214. .start = 0x40700000,
  215. .end = 0x40700023,
  216. .flags = IORESOURCE_MEM,
  217. }, {
  218. .start = IRQ_STUART,
  219. .end = IRQ_STUART,
  220. .flags = IORESOURCE_IRQ,
  221. }
  222. };
  223. struct platform_device pxa_device_stuart = {
  224. .name = "pxa2xx-uart",
  225. .id = 2,
  226. .resource = pxa_resource_stuart,
  227. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  228. };
  229. void __init pxa_set_stuart_info(void *info)
  230. {
  231. pxa_register_device(&pxa_device_stuart, info);
  232. }
  233. static struct resource pxa_resource_hwuart[] = {
  234. {
  235. .start = 0x41600000,
  236. .end = 0x4160002F,
  237. .flags = IORESOURCE_MEM,
  238. }, {
  239. .start = IRQ_HWUART,
  240. .end = IRQ_HWUART,
  241. .flags = IORESOURCE_IRQ,
  242. }
  243. };
  244. struct platform_device pxa_device_hwuart = {
  245. .name = "pxa2xx-uart",
  246. .id = 3,
  247. .resource = pxa_resource_hwuart,
  248. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  249. };
  250. void __init pxa_set_hwuart_info(void *info)
  251. {
  252. if (cpu_is_pxa255())
  253. pxa_register_device(&pxa_device_hwuart, info);
  254. else
  255. pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
  256. }
  257. static struct resource pxai2c_resources[] = {
  258. {
  259. .start = 0x40301680,
  260. .end = 0x403016a3,
  261. .flags = IORESOURCE_MEM,
  262. }, {
  263. .start = IRQ_I2C,
  264. .end = IRQ_I2C,
  265. .flags = IORESOURCE_IRQ,
  266. },
  267. };
  268. struct platform_device pxa_device_i2c = {
  269. .name = "pxa2xx-i2c",
  270. .id = 0,
  271. .resource = pxai2c_resources,
  272. .num_resources = ARRAY_SIZE(pxai2c_resources),
  273. };
  274. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  275. {
  276. pxa_register_device(&pxa_device_i2c, info);
  277. }
  278. #ifdef CONFIG_PXA27x
  279. static struct resource pxa27x_resources_i2c_power[] = {
  280. {
  281. .start = 0x40f00180,
  282. .end = 0x40f001a3,
  283. .flags = IORESOURCE_MEM,
  284. }, {
  285. .start = IRQ_PWRI2C,
  286. .end = IRQ_PWRI2C,
  287. .flags = IORESOURCE_IRQ,
  288. },
  289. };
  290. struct platform_device pxa27x_device_i2c_power = {
  291. .name = "pxa2xx-i2c",
  292. .id = 1,
  293. .resource = pxa27x_resources_i2c_power,
  294. .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
  295. };
  296. #endif
  297. static struct resource pxai2s_resources[] = {
  298. {
  299. .start = 0x40400000,
  300. .end = 0x40400083,
  301. .flags = IORESOURCE_MEM,
  302. }, {
  303. .start = IRQ_I2S,
  304. .end = IRQ_I2S,
  305. .flags = IORESOURCE_IRQ,
  306. },
  307. };
  308. struct platform_device pxa_device_i2s = {
  309. .name = "pxa2xx-i2s",
  310. .id = -1,
  311. .resource = pxai2s_resources,
  312. .num_resources = ARRAY_SIZE(pxai2s_resources),
  313. };
  314. struct platform_device pxa_device_asoc_ssp1 = {
  315. .name = "pxa-ssp-dai",
  316. .id = 0,
  317. };
  318. struct platform_device pxa_device_asoc_ssp2= {
  319. .name = "pxa-ssp-dai",
  320. .id = 1,
  321. };
  322. struct platform_device pxa_device_asoc_ssp3 = {
  323. .name = "pxa-ssp-dai",
  324. .id = 2,
  325. };
  326. struct platform_device pxa_device_asoc_ssp4 = {
  327. .name = "pxa-ssp-dai",
  328. .id = 3,
  329. };
  330. struct platform_device pxa_device_asoc_platform = {
  331. .name = "pxa-pcm-audio",
  332. .id = -1,
  333. };
  334. static u64 pxaficp_dmamask = ~(u32)0;
  335. struct platform_device pxa_device_ficp = {
  336. .name = "pxa2xx-ir",
  337. .id = -1,
  338. .dev = {
  339. .dma_mask = &pxaficp_dmamask,
  340. .coherent_dma_mask = 0xffffffff,
  341. },
  342. };
  343. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  344. {
  345. pxa_register_device(&pxa_device_ficp, info);
  346. }
  347. static struct resource pxa_rtc_resources[] = {
  348. [0] = {
  349. .start = 0x40900000,
  350. .end = 0x40900000 + 0x3b,
  351. .flags = IORESOURCE_MEM,
  352. },
  353. [1] = {
  354. .start = IRQ_RTC1Hz,
  355. .end = IRQ_RTC1Hz,
  356. .flags = IORESOURCE_IRQ,
  357. },
  358. [2] = {
  359. .start = IRQ_RTCAlrm,
  360. .end = IRQ_RTCAlrm,
  361. .flags = IORESOURCE_IRQ,
  362. },
  363. };
  364. static struct resource sa1100_rtc_resources[] = {
  365. [0] = {
  366. .start = 0x40900000,
  367. .end = 0x409000ff,
  368. .flags = IORESOURCE_MEM,
  369. },
  370. [1] = {
  371. .start = IRQ_RTC1Hz,
  372. .end = IRQ_RTC1Hz,
  373. .flags = IORESOURCE_IRQ,
  374. },
  375. [2] = {
  376. .start = IRQ_RTCAlrm,
  377. .end = IRQ_RTCAlrm,
  378. .flags = IORESOURCE_IRQ,
  379. },
  380. };
  381. struct platform_device sa1100_device_rtc = {
  382. .name = "sa1100-rtc",
  383. .id = -1,
  384. .num_resources = ARRAY_SIZE(sa1100_rtc_resources),
  385. .resource = sa1100_rtc_resources,
  386. };
  387. struct platform_device pxa_device_rtc = {
  388. .name = "pxa-rtc",
  389. .id = -1,
  390. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  391. .resource = pxa_rtc_resources,
  392. };
  393. static struct resource pxa_ac97_resources[] = {
  394. [0] = {
  395. .start = 0x40500000,
  396. .end = 0x40500000 + 0xfff,
  397. .flags = IORESOURCE_MEM,
  398. },
  399. [1] = {
  400. .start = IRQ_AC97,
  401. .end = IRQ_AC97,
  402. .flags = IORESOURCE_IRQ,
  403. },
  404. };
  405. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  406. struct platform_device pxa_device_ac97 = {
  407. .name = "pxa2xx-ac97",
  408. .id = -1,
  409. .dev = {
  410. .dma_mask = &pxa_ac97_dmamask,
  411. .coherent_dma_mask = 0xffffffff,
  412. },
  413. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  414. .resource = pxa_ac97_resources,
  415. };
  416. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  417. {
  418. pxa_register_device(&pxa_device_ac97, ops);
  419. }
  420. #ifdef CONFIG_PXA25x
  421. static struct resource pxa25x_resource_pwm0[] = {
  422. [0] = {
  423. .start = 0x40b00000,
  424. .end = 0x40b0000f,
  425. .flags = IORESOURCE_MEM,
  426. },
  427. };
  428. struct platform_device pxa25x_device_pwm0 = {
  429. .name = "pxa25x-pwm",
  430. .id = 0,
  431. .resource = pxa25x_resource_pwm0,
  432. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  433. };
  434. static struct resource pxa25x_resource_pwm1[] = {
  435. [0] = {
  436. .start = 0x40c00000,
  437. .end = 0x40c0000f,
  438. .flags = IORESOURCE_MEM,
  439. },
  440. };
  441. struct platform_device pxa25x_device_pwm1 = {
  442. .name = "pxa25x-pwm",
  443. .id = 1,
  444. .resource = pxa25x_resource_pwm1,
  445. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  446. };
  447. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  448. static struct resource pxa25x_resource_ssp[] = {
  449. [0] = {
  450. .start = 0x41000000,
  451. .end = 0x4100001f,
  452. .flags = IORESOURCE_MEM,
  453. },
  454. [1] = {
  455. .start = IRQ_SSP,
  456. .end = IRQ_SSP,
  457. .flags = IORESOURCE_IRQ,
  458. },
  459. [2] = {
  460. /* DRCMR for RX */
  461. .start = 13,
  462. .end = 13,
  463. .flags = IORESOURCE_DMA,
  464. },
  465. [3] = {
  466. /* DRCMR for TX */
  467. .start = 14,
  468. .end = 14,
  469. .flags = IORESOURCE_DMA,
  470. },
  471. };
  472. struct platform_device pxa25x_device_ssp = {
  473. .name = "pxa25x-ssp",
  474. .id = 0,
  475. .dev = {
  476. .dma_mask = &pxa25x_ssp_dma_mask,
  477. .coherent_dma_mask = DMA_BIT_MASK(32),
  478. },
  479. .resource = pxa25x_resource_ssp,
  480. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  481. };
  482. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  483. static struct resource pxa25x_resource_nssp[] = {
  484. [0] = {
  485. .start = 0x41400000,
  486. .end = 0x4140002f,
  487. .flags = IORESOURCE_MEM,
  488. },
  489. [1] = {
  490. .start = IRQ_NSSP,
  491. .end = IRQ_NSSP,
  492. .flags = IORESOURCE_IRQ,
  493. },
  494. [2] = {
  495. /* DRCMR for RX */
  496. .start = 15,
  497. .end = 15,
  498. .flags = IORESOURCE_DMA,
  499. },
  500. [3] = {
  501. /* DRCMR for TX */
  502. .start = 16,
  503. .end = 16,
  504. .flags = IORESOURCE_DMA,
  505. },
  506. };
  507. struct platform_device pxa25x_device_nssp = {
  508. .name = "pxa25x-nssp",
  509. .id = 1,
  510. .dev = {
  511. .dma_mask = &pxa25x_nssp_dma_mask,
  512. .coherent_dma_mask = DMA_BIT_MASK(32),
  513. },
  514. .resource = pxa25x_resource_nssp,
  515. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  516. };
  517. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  518. static struct resource pxa25x_resource_assp[] = {
  519. [0] = {
  520. .start = 0x41500000,
  521. .end = 0x4150002f,
  522. .flags = IORESOURCE_MEM,
  523. },
  524. [1] = {
  525. .start = IRQ_ASSP,
  526. .end = IRQ_ASSP,
  527. .flags = IORESOURCE_IRQ,
  528. },
  529. [2] = {
  530. /* DRCMR for RX */
  531. .start = 23,
  532. .end = 23,
  533. .flags = IORESOURCE_DMA,
  534. },
  535. [3] = {
  536. /* DRCMR for TX */
  537. .start = 24,
  538. .end = 24,
  539. .flags = IORESOURCE_DMA,
  540. },
  541. };
  542. struct platform_device pxa25x_device_assp = {
  543. /* ASSP is basically equivalent to NSSP */
  544. .name = "pxa25x-nssp",
  545. .id = 2,
  546. .dev = {
  547. .dma_mask = &pxa25x_assp_dma_mask,
  548. .coherent_dma_mask = DMA_BIT_MASK(32),
  549. },
  550. .resource = pxa25x_resource_assp,
  551. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  552. };
  553. #endif /* CONFIG_PXA25x */
  554. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  555. static struct resource pxa27x_resource_camera[] = {
  556. [0] = {
  557. .start = 0x50000000,
  558. .end = 0x50000fff,
  559. .flags = IORESOURCE_MEM,
  560. },
  561. [1] = {
  562. .start = IRQ_CAMERA,
  563. .end = IRQ_CAMERA,
  564. .flags = IORESOURCE_IRQ,
  565. },
  566. };
  567. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  568. static struct platform_device pxa27x_device_camera = {
  569. .name = "pxa27x-camera",
  570. .id = 0, /* This is used to put cameras on this interface */
  571. .dev = {
  572. .dma_mask = &pxa27x_dma_mask_camera,
  573. .coherent_dma_mask = 0xffffffff,
  574. },
  575. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  576. .resource = pxa27x_resource_camera,
  577. };
  578. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  579. {
  580. pxa_register_device(&pxa27x_device_camera, info);
  581. }
  582. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  583. static struct resource pxa27x_resource_ohci[] = {
  584. [0] = {
  585. .start = 0x4C000000,
  586. .end = 0x4C00ff6f,
  587. .flags = IORESOURCE_MEM,
  588. },
  589. [1] = {
  590. .start = IRQ_USBH1,
  591. .end = IRQ_USBH1,
  592. .flags = IORESOURCE_IRQ,
  593. },
  594. };
  595. struct platform_device pxa27x_device_ohci = {
  596. .name = "pxa27x-ohci",
  597. .id = -1,
  598. .dev = {
  599. .dma_mask = &pxa27x_ohci_dma_mask,
  600. .coherent_dma_mask = DMA_BIT_MASK(32),
  601. },
  602. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  603. .resource = pxa27x_resource_ohci,
  604. };
  605. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  606. {
  607. pxa_register_device(&pxa27x_device_ohci, info);
  608. }
  609. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  610. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
  611. static struct resource pxa27x_resource_keypad[] = {
  612. [0] = {
  613. .start = 0x41500000,
  614. .end = 0x4150004c,
  615. .flags = IORESOURCE_MEM,
  616. },
  617. [1] = {
  618. .start = IRQ_KEYPAD,
  619. .end = IRQ_KEYPAD,
  620. .flags = IORESOURCE_IRQ,
  621. },
  622. };
  623. struct platform_device pxa27x_device_keypad = {
  624. .name = "pxa27x-keypad",
  625. .id = -1,
  626. .resource = pxa27x_resource_keypad,
  627. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  628. };
  629. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  630. {
  631. pxa_register_device(&pxa27x_device_keypad, info);
  632. }
  633. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  634. static struct resource pxa27x_resource_ssp1[] = {
  635. [0] = {
  636. .start = 0x41000000,
  637. .end = 0x4100003f,
  638. .flags = IORESOURCE_MEM,
  639. },
  640. [1] = {
  641. .start = IRQ_SSP,
  642. .end = IRQ_SSP,
  643. .flags = IORESOURCE_IRQ,
  644. },
  645. [2] = {
  646. /* DRCMR for RX */
  647. .start = 13,
  648. .end = 13,
  649. .flags = IORESOURCE_DMA,
  650. },
  651. [3] = {
  652. /* DRCMR for TX */
  653. .start = 14,
  654. .end = 14,
  655. .flags = IORESOURCE_DMA,
  656. },
  657. };
  658. struct platform_device pxa27x_device_ssp1 = {
  659. .name = "pxa27x-ssp",
  660. .id = 0,
  661. .dev = {
  662. .dma_mask = &pxa27x_ssp1_dma_mask,
  663. .coherent_dma_mask = DMA_BIT_MASK(32),
  664. },
  665. .resource = pxa27x_resource_ssp1,
  666. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  667. };
  668. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  669. static struct resource pxa27x_resource_ssp2[] = {
  670. [0] = {
  671. .start = 0x41700000,
  672. .end = 0x4170003f,
  673. .flags = IORESOURCE_MEM,
  674. },
  675. [1] = {
  676. .start = IRQ_SSP2,
  677. .end = IRQ_SSP2,
  678. .flags = IORESOURCE_IRQ,
  679. },
  680. [2] = {
  681. /* DRCMR for RX */
  682. .start = 15,
  683. .end = 15,
  684. .flags = IORESOURCE_DMA,
  685. },
  686. [3] = {
  687. /* DRCMR for TX */
  688. .start = 16,
  689. .end = 16,
  690. .flags = IORESOURCE_DMA,
  691. },
  692. };
  693. struct platform_device pxa27x_device_ssp2 = {
  694. .name = "pxa27x-ssp",
  695. .id = 1,
  696. .dev = {
  697. .dma_mask = &pxa27x_ssp2_dma_mask,
  698. .coherent_dma_mask = DMA_BIT_MASK(32),
  699. },
  700. .resource = pxa27x_resource_ssp2,
  701. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  702. };
  703. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  704. static struct resource pxa27x_resource_ssp3[] = {
  705. [0] = {
  706. .start = 0x41900000,
  707. .end = 0x4190003f,
  708. .flags = IORESOURCE_MEM,
  709. },
  710. [1] = {
  711. .start = IRQ_SSP3,
  712. .end = IRQ_SSP3,
  713. .flags = IORESOURCE_IRQ,
  714. },
  715. [2] = {
  716. /* DRCMR for RX */
  717. .start = 66,
  718. .end = 66,
  719. .flags = IORESOURCE_DMA,
  720. },
  721. [3] = {
  722. /* DRCMR for TX */
  723. .start = 67,
  724. .end = 67,
  725. .flags = IORESOURCE_DMA,
  726. },
  727. };
  728. struct platform_device pxa27x_device_ssp3 = {
  729. .name = "pxa27x-ssp",
  730. .id = 2,
  731. .dev = {
  732. .dma_mask = &pxa27x_ssp3_dma_mask,
  733. .coherent_dma_mask = DMA_BIT_MASK(32),
  734. },
  735. .resource = pxa27x_resource_ssp3,
  736. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  737. };
  738. static struct resource pxa27x_resource_pwm0[] = {
  739. [0] = {
  740. .start = 0x40b00000,
  741. .end = 0x40b0001f,
  742. .flags = IORESOURCE_MEM,
  743. },
  744. };
  745. struct platform_device pxa27x_device_pwm0 = {
  746. .name = "pxa27x-pwm",
  747. .id = 0,
  748. .resource = pxa27x_resource_pwm0,
  749. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  750. };
  751. static struct resource pxa27x_resource_pwm1[] = {
  752. [0] = {
  753. .start = 0x40c00000,
  754. .end = 0x40c0001f,
  755. .flags = IORESOURCE_MEM,
  756. },
  757. };
  758. struct platform_device pxa27x_device_pwm1 = {
  759. .name = "pxa27x-pwm",
  760. .id = 1,
  761. .resource = pxa27x_resource_pwm1,
  762. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  763. };
  764. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx || CONFIG_PXA95x*/
  765. #ifdef CONFIG_PXA3xx
  766. static struct resource pxa3xx_resources_mci2[] = {
  767. [0] = {
  768. .start = 0x42000000,
  769. .end = 0x42000fff,
  770. .flags = IORESOURCE_MEM,
  771. },
  772. [1] = {
  773. .start = IRQ_MMC2,
  774. .end = IRQ_MMC2,
  775. .flags = IORESOURCE_IRQ,
  776. },
  777. [2] = {
  778. .start = 93,
  779. .end = 93,
  780. .flags = IORESOURCE_DMA,
  781. },
  782. [3] = {
  783. .start = 94,
  784. .end = 94,
  785. .flags = IORESOURCE_DMA,
  786. },
  787. };
  788. struct platform_device pxa3xx_device_mci2 = {
  789. .name = "pxa2xx-mci",
  790. .id = 1,
  791. .dev = {
  792. .dma_mask = &pxamci_dmamask,
  793. .coherent_dma_mask = 0xffffffff,
  794. },
  795. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  796. .resource = pxa3xx_resources_mci2,
  797. };
  798. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  799. {
  800. pxa_register_device(&pxa3xx_device_mci2, info);
  801. }
  802. static struct resource pxa3xx_resources_mci3[] = {
  803. [0] = {
  804. .start = 0x42500000,
  805. .end = 0x42500fff,
  806. .flags = IORESOURCE_MEM,
  807. },
  808. [1] = {
  809. .start = IRQ_MMC3,
  810. .end = IRQ_MMC3,
  811. .flags = IORESOURCE_IRQ,
  812. },
  813. [2] = {
  814. .start = 100,
  815. .end = 100,
  816. .flags = IORESOURCE_DMA,
  817. },
  818. [3] = {
  819. .start = 101,
  820. .end = 101,
  821. .flags = IORESOURCE_DMA,
  822. },
  823. };
  824. struct platform_device pxa3xx_device_mci3 = {
  825. .name = "pxa2xx-mci",
  826. .id = 2,
  827. .dev = {
  828. .dma_mask = &pxamci_dmamask,
  829. .coherent_dma_mask = 0xffffffff,
  830. },
  831. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  832. .resource = pxa3xx_resources_mci3,
  833. };
  834. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  835. {
  836. pxa_register_device(&pxa3xx_device_mci3, info);
  837. }
  838. static struct resource pxa3xx_resources_gcu[] = {
  839. {
  840. .start = 0x54000000,
  841. .end = 0x54000fff,
  842. .flags = IORESOURCE_MEM,
  843. },
  844. {
  845. .start = IRQ_GCU,
  846. .end = IRQ_GCU,
  847. .flags = IORESOURCE_IRQ,
  848. },
  849. };
  850. static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
  851. struct platform_device pxa3xx_device_gcu = {
  852. .name = "pxa3xx-gcu",
  853. .id = -1,
  854. .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
  855. .resource = pxa3xx_resources_gcu,
  856. .dev = {
  857. .dma_mask = &pxa3xx_gcu_dmamask,
  858. .coherent_dma_mask = 0xffffffff,
  859. },
  860. };
  861. #endif /* CONFIG_PXA3xx */
  862. #if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
  863. static struct resource pxa3xx_resources_i2c_power[] = {
  864. {
  865. .start = 0x40f500c0,
  866. .end = 0x40f500d3,
  867. .flags = IORESOURCE_MEM,
  868. }, {
  869. .start = IRQ_PWRI2C,
  870. .end = IRQ_PWRI2C,
  871. .flags = IORESOURCE_IRQ,
  872. },
  873. };
  874. struct platform_device pxa3xx_device_i2c_power = {
  875. .name = "pxa3xx-pwri2c",
  876. .id = 1,
  877. .resource = pxa3xx_resources_i2c_power,
  878. .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
  879. };
  880. static struct resource pxa3xx_resources_nand[] = {
  881. [0] = {
  882. .start = 0x43100000,
  883. .end = 0x43100053,
  884. .flags = IORESOURCE_MEM,
  885. },
  886. [1] = {
  887. .start = IRQ_NAND,
  888. .end = IRQ_NAND,
  889. .flags = IORESOURCE_IRQ,
  890. },
  891. [2] = {
  892. /* DRCMR for Data DMA */
  893. .start = 97,
  894. .end = 97,
  895. .flags = IORESOURCE_DMA,
  896. },
  897. [3] = {
  898. /* DRCMR for Command DMA */
  899. .start = 99,
  900. .end = 99,
  901. .flags = IORESOURCE_DMA,
  902. },
  903. };
  904. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  905. struct platform_device pxa3xx_device_nand = {
  906. .name = "pxa3xx-nand",
  907. .id = -1,
  908. .dev = {
  909. .dma_mask = &pxa3xx_nand_dma_mask,
  910. .coherent_dma_mask = DMA_BIT_MASK(32),
  911. },
  912. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  913. .resource = pxa3xx_resources_nand,
  914. };
  915. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  916. {
  917. pxa_register_device(&pxa3xx_device_nand, info);
  918. }
  919. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  920. static struct resource pxa3xx_resource_ssp4[] = {
  921. [0] = {
  922. .start = 0x41a00000,
  923. .end = 0x41a0003f,
  924. .flags = IORESOURCE_MEM,
  925. },
  926. [1] = {
  927. .start = IRQ_SSP4,
  928. .end = IRQ_SSP4,
  929. .flags = IORESOURCE_IRQ,
  930. },
  931. [2] = {
  932. /* DRCMR for RX */
  933. .start = 2,
  934. .end = 2,
  935. .flags = IORESOURCE_DMA,
  936. },
  937. [3] = {
  938. /* DRCMR for TX */
  939. .start = 3,
  940. .end = 3,
  941. .flags = IORESOURCE_DMA,
  942. },
  943. };
  944. struct platform_device pxa3xx_device_ssp4 = {
  945. /* PXA3xx SSP is basically equivalent to PXA27x */
  946. .name = "pxa27x-ssp",
  947. .id = 3,
  948. .dev = {
  949. .dma_mask = &pxa3xx_ssp4_dma_mask,
  950. .coherent_dma_mask = DMA_BIT_MASK(32),
  951. },
  952. .resource = pxa3xx_resource_ssp4,
  953. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  954. };
  955. #endif /* CONFIG_PXA3xx || CONFIG_PXA95x */
  956. struct resource pxa_resource_gpio[] = {
  957. {
  958. .start = 0x40e00000,
  959. .end = 0x40e0ffff,
  960. .flags = IORESOURCE_MEM,
  961. }, {
  962. .start = IRQ_GPIO0,
  963. .end = IRQ_GPIO0,
  964. .name = "gpio0",
  965. .flags = IORESOURCE_IRQ,
  966. }, {
  967. .start = IRQ_GPIO1,
  968. .end = IRQ_GPIO1,
  969. .name = "gpio1",
  970. .flags = IORESOURCE_IRQ,
  971. }, {
  972. .start = IRQ_GPIO_2_x,
  973. .end = IRQ_GPIO_2_x,
  974. .name = "gpio_mux",
  975. .flags = IORESOURCE_IRQ,
  976. },
  977. };
  978. struct platform_device pxa_device_gpio = {
  979. .name = "pxa-gpio",
  980. .id = -1,
  981. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  982. .resource = pxa_resource_gpio,
  983. };
  984. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  985. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  986. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
  987. {
  988. struct platform_device *pd;
  989. pd = platform_device_alloc("pxa2xx-spi", id);
  990. if (pd == NULL) {
  991. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  992. id);
  993. return;
  994. }
  995. pd->dev.platform_data = info;
  996. platform_device_add(pd);
  997. }