src.c 1.9 KB

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  1. /*
  2. * Copyright 2011 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12. #include <linux/init.h>
  13. #include <linux/io.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <linux/smp.h>
  17. #define SRC_SCR 0x000
  18. #define SRC_GPR1 0x020
  19. #define BP_SRC_SCR_WARM_RESET_ENABLE 0
  20. #define BP_SRC_SCR_CORE1_RST 14
  21. #define BP_SRC_SCR_CORE1_ENABLE 22
  22. static void __iomem *src_base;
  23. #ifndef CONFIG_SMP
  24. #define cpu_logical_map(cpu) 0
  25. #endif
  26. void imx_enable_cpu(int cpu, bool enable)
  27. {
  28. u32 mask, val;
  29. cpu = cpu_logical_map(cpu);
  30. mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
  31. val = readl_relaxed(src_base + SRC_SCR);
  32. val = enable ? val | mask : val & ~mask;
  33. writel_relaxed(val, src_base + SRC_SCR);
  34. }
  35. void imx_set_cpu_jump(int cpu, void *jump_addr)
  36. {
  37. cpu = cpu_logical_map(cpu);
  38. writel_relaxed(virt_to_phys(jump_addr),
  39. src_base + SRC_GPR1 + cpu * 8);
  40. }
  41. void imx_src_prepare_restart(void)
  42. {
  43. u32 val;
  44. /* clear enable bits of secondary cores */
  45. val = readl_relaxed(src_base + SRC_SCR);
  46. val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
  47. writel_relaxed(val, src_base + SRC_SCR);
  48. /* clear persistent entry register of primary core */
  49. writel_relaxed(0, src_base + SRC_GPR1);
  50. }
  51. void __init imx_src_init(void)
  52. {
  53. struct device_node *np;
  54. u32 val;
  55. np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src");
  56. src_base = of_iomap(np, 0);
  57. WARN_ON(!src_base);
  58. /*
  59. * force warm reset sources to generate cold reset
  60. * for a more reliable restart
  61. */
  62. val = readl_relaxed(src_base + SRC_SCR);
  63. val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
  64. writel_relaxed(val, src_base + SRC_SCR);
  65. }