intel_panel.c 21 KB

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  1. /*
  2. * Copyright © 2006-2010 Intel Corporation
  3. * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22. * DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors:
  25. * Eric Anholt <eric@anholt.net>
  26. * Dave Airlie <airlied@linux.ie>
  27. * Jesse Barnes <jesse.barnes@intel.com>
  28. * Chris Wilson <chris@chris-wilson.co.uk>
  29. */
  30. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31. #include <linux/moduleparam.h>
  32. #include "intel_drv.h"
  33. #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
  34. void
  35. intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
  36. struct drm_display_mode *adjusted_mode)
  37. {
  38. drm_mode_copy(adjusted_mode, fixed_mode);
  39. drm_mode_set_crtcinfo(adjusted_mode, 0);
  40. }
  41. /* adjusted_mode has been preset to be the panel's fixed mode */
  42. void
  43. intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
  44. struct intel_crtc_config *pipe_config,
  45. int fitting_mode)
  46. {
  47. struct drm_display_mode *adjusted_mode;
  48. int x, y, width, height;
  49. adjusted_mode = &pipe_config->adjusted_mode;
  50. x = y = width = height = 0;
  51. /* Native modes don't need fitting */
  52. if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
  53. adjusted_mode->vdisplay == pipe_config->pipe_src_h)
  54. goto done;
  55. switch (fitting_mode) {
  56. case DRM_MODE_SCALE_CENTER:
  57. width = pipe_config->pipe_src_w;
  58. height = pipe_config->pipe_src_h;
  59. x = (adjusted_mode->hdisplay - width + 1)/2;
  60. y = (adjusted_mode->vdisplay - height + 1)/2;
  61. break;
  62. case DRM_MODE_SCALE_ASPECT:
  63. /* Scale but preserve the aspect ratio */
  64. {
  65. u32 scaled_width = adjusted_mode->hdisplay
  66. * pipe_config->pipe_src_h;
  67. u32 scaled_height = pipe_config->pipe_src_w
  68. * adjusted_mode->vdisplay;
  69. if (scaled_width > scaled_height) { /* pillar */
  70. width = scaled_height / pipe_config->pipe_src_h;
  71. if (width & 1)
  72. width++;
  73. x = (adjusted_mode->hdisplay - width + 1) / 2;
  74. y = 0;
  75. height = adjusted_mode->vdisplay;
  76. } else if (scaled_width < scaled_height) { /* letter */
  77. height = scaled_width / pipe_config->pipe_src_w;
  78. if (height & 1)
  79. height++;
  80. y = (adjusted_mode->vdisplay - height + 1) / 2;
  81. x = 0;
  82. width = adjusted_mode->hdisplay;
  83. } else {
  84. x = y = 0;
  85. width = adjusted_mode->hdisplay;
  86. height = adjusted_mode->vdisplay;
  87. }
  88. }
  89. break;
  90. case DRM_MODE_SCALE_FULLSCREEN:
  91. x = y = 0;
  92. width = adjusted_mode->hdisplay;
  93. height = adjusted_mode->vdisplay;
  94. break;
  95. default:
  96. WARN(1, "bad panel fit mode: %d\n", fitting_mode);
  97. return;
  98. }
  99. done:
  100. pipe_config->pch_pfit.pos = (x << 16) | y;
  101. pipe_config->pch_pfit.size = (width << 16) | height;
  102. }
  103. static void
  104. centre_horizontally(struct drm_display_mode *mode,
  105. int width)
  106. {
  107. u32 border, sync_pos, blank_width, sync_width;
  108. /* keep the hsync and hblank widths constant */
  109. sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
  110. blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
  111. sync_pos = (blank_width - sync_width + 1) / 2;
  112. border = (mode->hdisplay - width + 1) / 2;
  113. border += border & 1; /* make the border even */
  114. mode->crtc_hdisplay = width;
  115. mode->crtc_hblank_start = width + border;
  116. mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
  117. mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
  118. mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
  119. }
  120. static void
  121. centre_vertically(struct drm_display_mode *mode,
  122. int height)
  123. {
  124. u32 border, sync_pos, blank_width, sync_width;
  125. /* keep the vsync and vblank widths constant */
  126. sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
  127. blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
  128. sync_pos = (blank_width - sync_width + 1) / 2;
  129. border = (mode->vdisplay - height + 1) / 2;
  130. mode->crtc_vdisplay = height;
  131. mode->crtc_vblank_start = height + border;
  132. mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
  133. mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
  134. mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
  135. }
  136. static inline u32 panel_fitter_scaling(u32 source, u32 target)
  137. {
  138. /*
  139. * Floating point operation is not supported. So the FACTOR
  140. * is defined, which can avoid the floating point computation
  141. * when calculating the panel ratio.
  142. */
  143. #define ACCURACY 12
  144. #define FACTOR (1 << ACCURACY)
  145. u32 ratio = source * FACTOR / target;
  146. return (FACTOR * ratio + FACTOR/2) / FACTOR;
  147. }
  148. static void i965_scale_aspect(struct intel_crtc_config *pipe_config,
  149. u32 *pfit_control)
  150. {
  151. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  152. u32 scaled_width = adjusted_mode->hdisplay *
  153. pipe_config->pipe_src_h;
  154. u32 scaled_height = pipe_config->pipe_src_w *
  155. adjusted_mode->vdisplay;
  156. /* 965+ is easy, it does everything in hw */
  157. if (scaled_width > scaled_height)
  158. *pfit_control |= PFIT_ENABLE |
  159. PFIT_SCALING_PILLAR;
  160. else if (scaled_width < scaled_height)
  161. *pfit_control |= PFIT_ENABLE |
  162. PFIT_SCALING_LETTER;
  163. else if (adjusted_mode->hdisplay != pipe_config->pipe_src_w)
  164. *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
  165. }
  166. static void i9xx_scale_aspect(struct intel_crtc_config *pipe_config,
  167. u32 *pfit_control, u32 *pfit_pgm_ratios,
  168. u32 *border)
  169. {
  170. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  171. u32 scaled_width = adjusted_mode->hdisplay *
  172. pipe_config->pipe_src_h;
  173. u32 scaled_height = pipe_config->pipe_src_w *
  174. adjusted_mode->vdisplay;
  175. u32 bits;
  176. /*
  177. * For earlier chips we have to calculate the scaling
  178. * ratio by hand and program it into the
  179. * PFIT_PGM_RATIO register
  180. */
  181. if (scaled_width > scaled_height) { /* pillar */
  182. centre_horizontally(adjusted_mode,
  183. scaled_height /
  184. pipe_config->pipe_src_h);
  185. *border = LVDS_BORDER_ENABLE;
  186. if (pipe_config->pipe_src_h != adjusted_mode->vdisplay) {
  187. bits = panel_fitter_scaling(pipe_config->pipe_src_h,
  188. adjusted_mode->vdisplay);
  189. *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
  190. bits << PFIT_VERT_SCALE_SHIFT);
  191. *pfit_control |= (PFIT_ENABLE |
  192. VERT_INTERP_BILINEAR |
  193. HORIZ_INTERP_BILINEAR);
  194. }
  195. } else if (scaled_width < scaled_height) { /* letter */
  196. centre_vertically(adjusted_mode,
  197. scaled_width /
  198. pipe_config->pipe_src_w);
  199. *border = LVDS_BORDER_ENABLE;
  200. if (pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
  201. bits = panel_fitter_scaling(pipe_config->pipe_src_w,
  202. adjusted_mode->hdisplay);
  203. *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
  204. bits << PFIT_VERT_SCALE_SHIFT);
  205. *pfit_control |= (PFIT_ENABLE |
  206. VERT_INTERP_BILINEAR |
  207. HORIZ_INTERP_BILINEAR);
  208. }
  209. } else {
  210. /* Aspects match, Let hw scale both directions */
  211. *pfit_control |= (PFIT_ENABLE |
  212. VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
  213. VERT_INTERP_BILINEAR |
  214. HORIZ_INTERP_BILINEAR);
  215. }
  216. }
  217. void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
  218. struct intel_crtc_config *pipe_config,
  219. int fitting_mode)
  220. {
  221. struct drm_device *dev = intel_crtc->base.dev;
  222. u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
  223. struct drm_display_mode *adjusted_mode;
  224. adjusted_mode = &pipe_config->adjusted_mode;
  225. /* Native modes don't need fitting */
  226. if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
  227. adjusted_mode->vdisplay == pipe_config->pipe_src_h)
  228. goto out;
  229. switch (fitting_mode) {
  230. case DRM_MODE_SCALE_CENTER:
  231. /*
  232. * For centered modes, we have to calculate border widths &
  233. * heights and modify the values programmed into the CRTC.
  234. */
  235. centre_horizontally(adjusted_mode, pipe_config->pipe_src_w);
  236. centre_vertically(adjusted_mode, pipe_config->pipe_src_h);
  237. border = LVDS_BORDER_ENABLE;
  238. break;
  239. case DRM_MODE_SCALE_ASPECT:
  240. /* Scale but preserve the aspect ratio */
  241. if (INTEL_INFO(dev)->gen >= 4)
  242. i965_scale_aspect(pipe_config, &pfit_control);
  243. else
  244. i9xx_scale_aspect(pipe_config, &pfit_control,
  245. &pfit_pgm_ratios, &border);
  246. break;
  247. case DRM_MODE_SCALE_FULLSCREEN:
  248. /*
  249. * Full scaling, even if it changes the aspect ratio.
  250. * Fortunately this is all done for us in hw.
  251. */
  252. if (pipe_config->pipe_src_h != adjusted_mode->vdisplay ||
  253. pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
  254. pfit_control |= PFIT_ENABLE;
  255. if (INTEL_INFO(dev)->gen >= 4)
  256. pfit_control |= PFIT_SCALING_AUTO;
  257. else
  258. pfit_control |= (VERT_AUTO_SCALE |
  259. VERT_INTERP_BILINEAR |
  260. HORIZ_AUTO_SCALE |
  261. HORIZ_INTERP_BILINEAR);
  262. }
  263. break;
  264. default:
  265. WARN(1, "bad panel fit mode: %d\n", fitting_mode);
  266. return;
  267. }
  268. /* 965+ wants fuzzy fitting */
  269. /* FIXME: handle multiple panels by failing gracefully */
  270. if (INTEL_INFO(dev)->gen >= 4)
  271. pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
  272. PFIT_FILTER_FUZZY);
  273. out:
  274. if ((pfit_control & PFIT_ENABLE) == 0) {
  275. pfit_control = 0;
  276. pfit_pgm_ratios = 0;
  277. }
  278. /* Make sure pre-965 set dither correctly for 18bpp panels. */
  279. if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
  280. pfit_control |= PANEL_8TO6_DITHER_ENABLE;
  281. pipe_config->gmch_pfit.control = pfit_control;
  282. pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
  283. pipe_config->gmch_pfit.lvds_border_bits = border;
  284. }
  285. static int is_backlight_combination_mode(struct drm_device *dev)
  286. {
  287. struct drm_i915_private *dev_priv = dev->dev_private;
  288. if (INTEL_INFO(dev)->gen >= 4)
  289. return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
  290. if (IS_GEN2(dev))
  291. return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
  292. return 0;
  293. }
  294. /* XXX: query mode clock or hardware clock and program max PWM appropriately
  295. * when it's 0.
  296. */
  297. static u32 i915_read_blc_pwm_ctl(struct drm_device *dev)
  298. {
  299. struct drm_i915_private *dev_priv = dev->dev_private;
  300. u32 val;
  301. WARN_ON_SMP(!spin_is_locked(&dev_priv->backlight.lock));
  302. /* Restore the CTL value if it lost, e.g. GPU reset */
  303. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  304. val = I915_READ(BLC_PWM_PCH_CTL2);
  305. if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
  306. dev_priv->regfile.saveBLC_PWM_CTL2 = val;
  307. } else if (val == 0) {
  308. val = dev_priv->regfile.saveBLC_PWM_CTL2;
  309. I915_WRITE(BLC_PWM_PCH_CTL2, val);
  310. }
  311. } else {
  312. val = I915_READ(BLC_PWM_CTL);
  313. if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
  314. dev_priv->regfile.saveBLC_PWM_CTL = val;
  315. if (INTEL_INFO(dev)->gen >= 4)
  316. dev_priv->regfile.saveBLC_PWM_CTL2 =
  317. I915_READ(BLC_PWM_CTL2);
  318. } else if (val == 0) {
  319. val = dev_priv->regfile.saveBLC_PWM_CTL;
  320. I915_WRITE(BLC_PWM_CTL, val);
  321. if (INTEL_INFO(dev)->gen >= 4)
  322. I915_WRITE(BLC_PWM_CTL2,
  323. dev_priv->regfile.saveBLC_PWM_CTL2);
  324. }
  325. }
  326. return val;
  327. }
  328. static u32 intel_panel_get_max_backlight(struct drm_device *dev)
  329. {
  330. u32 max;
  331. max = i915_read_blc_pwm_ctl(dev);
  332. if (HAS_PCH_SPLIT(dev)) {
  333. max >>= 16;
  334. } else {
  335. if (INTEL_INFO(dev)->gen < 4)
  336. max >>= 17;
  337. else
  338. max >>= 16;
  339. if (is_backlight_combination_mode(dev))
  340. max *= 0xff;
  341. }
  342. DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
  343. return max;
  344. }
  345. static int i915_panel_invert_brightness;
  346. MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness "
  347. "(-1 force normal, 0 machine defaults, 1 force inversion), please "
  348. "report PCI device ID, subsystem vendor and subsystem device ID "
  349. "to dri-devel@lists.freedesktop.org, if your machine needs it. "
  350. "It will then be included in an upcoming module version.");
  351. module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600);
  352. static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val)
  353. {
  354. struct drm_i915_private *dev_priv = dev->dev_private;
  355. if (i915_panel_invert_brightness < 0)
  356. return val;
  357. if (i915_panel_invert_brightness > 0 ||
  358. dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
  359. u32 max = intel_panel_get_max_backlight(dev);
  360. if (max)
  361. return max - val;
  362. }
  363. return val;
  364. }
  365. static u32 intel_panel_get_backlight(struct drm_device *dev)
  366. {
  367. struct drm_i915_private *dev_priv = dev->dev_private;
  368. u32 val;
  369. unsigned long flags;
  370. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  371. if (HAS_PCH_SPLIT(dev)) {
  372. val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
  373. } else {
  374. val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
  375. if (INTEL_INFO(dev)->gen < 4)
  376. val >>= 1;
  377. if (is_backlight_combination_mode(dev)) {
  378. u8 lbpc;
  379. pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
  380. val *= lbpc;
  381. }
  382. }
  383. val = intel_panel_compute_brightness(dev, val);
  384. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  385. DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
  386. return val;
  387. }
  388. static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
  389. {
  390. struct drm_i915_private *dev_priv = dev->dev_private;
  391. u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
  392. I915_WRITE(BLC_PWM_CPU_CTL, val | level);
  393. }
  394. static void intel_panel_actually_set_backlight(struct drm_device *dev,
  395. u32 level)
  396. {
  397. struct drm_i915_private *dev_priv = dev->dev_private;
  398. u32 tmp;
  399. DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
  400. level = intel_panel_compute_brightness(dev, level);
  401. if (HAS_PCH_SPLIT(dev))
  402. return intel_pch_panel_set_backlight(dev, level);
  403. if (is_backlight_combination_mode(dev)) {
  404. u32 max = intel_panel_get_max_backlight(dev);
  405. u8 lbpc;
  406. /* we're screwed, but keep behaviour backwards compatible */
  407. if (!max)
  408. max = 1;
  409. lbpc = level * 0xfe / max + 1;
  410. level /= lbpc;
  411. pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
  412. }
  413. tmp = I915_READ(BLC_PWM_CTL);
  414. if (INTEL_INFO(dev)->gen < 4)
  415. level <<= 1;
  416. tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
  417. I915_WRITE(BLC_PWM_CTL, tmp | level);
  418. }
  419. /* set backlight brightness to level in range [0..max] */
  420. void intel_panel_set_backlight(struct drm_device *dev, u32 level, u32 max)
  421. {
  422. struct drm_i915_private *dev_priv = dev->dev_private;
  423. u32 freq;
  424. unsigned long flags;
  425. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  426. freq = intel_panel_get_max_backlight(dev);
  427. if (!freq) {
  428. /* we are screwed, bail out */
  429. goto out;
  430. }
  431. /* scale to hardware, but be careful to not overflow */
  432. if (freq < max)
  433. level = level * freq / max;
  434. else
  435. level = freq / max * level;
  436. dev_priv->backlight.level = level;
  437. if (dev_priv->backlight.device)
  438. dev_priv->backlight.device->props.brightness = level;
  439. if (dev_priv->backlight.enabled)
  440. intel_panel_actually_set_backlight(dev, level);
  441. out:
  442. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  443. }
  444. void intel_panel_disable_backlight(struct drm_device *dev)
  445. {
  446. struct drm_i915_private *dev_priv = dev->dev_private;
  447. unsigned long flags;
  448. /*
  449. * Do not disable backlight on the vgaswitcheroo path. When switching
  450. * away from i915, the other client may depend on i915 to handle the
  451. * backlight. This will leave the backlight on unnecessarily when
  452. * another client is not activated.
  453. */
  454. if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) {
  455. DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n");
  456. return;
  457. }
  458. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  459. dev_priv->backlight.enabled = false;
  460. intel_panel_actually_set_backlight(dev, 0);
  461. if (INTEL_INFO(dev)->gen >= 4) {
  462. uint32_t reg, tmp;
  463. reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
  464. I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE);
  465. if (HAS_PCH_SPLIT(dev)) {
  466. tmp = I915_READ(BLC_PWM_PCH_CTL1);
  467. tmp &= ~BLM_PCH_PWM_ENABLE;
  468. I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
  469. }
  470. }
  471. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  472. }
  473. void intel_panel_enable_backlight(struct drm_device *dev,
  474. enum pipe pipe)
  475. {
  476. struct drm_i915_private *dev_priv = dev->dev_private;
  477. enum transcoder cpu_transcoder =
  478. intel_pipe_to_cpu_transcoder(dev_priv, pipe);
  479. unsigned long flags;
  480. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  481. if (dev_priv->backlight.level == 0) {
  482. dev_priv->backlight.level = intel_panel_get_max_backlight(dev);
  483. if (dev_priv->backlight.device)
  484. dev_priv->backlight.device->props.brightness =
  485. dev_priv->backlight.level;
  486. }
  487. if (INTEL_INFO(dev)->gen >= 4) {
  488. uint32_t reg, tmp;
  489. reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
  490. tmp = I915_READ(reg);
  491. /* Note that this can also get called through dpms changes. And
  492. * we don't track the backlight dpms state, hence check whether
  493. * we have to do anything first. */
  494. if (tmp & BLM_PWM_ENABLE)
  495. goto set_level;
  496. if (INTEL_INFO(dev)->num_pipes == 3)
  497. tmp &= ~BLM_PIPE_SELECT_IVB;
  498. else
  499. tmp &= ~BLM_PIPE_SELECT;
  500. if (cpu_transcoder == TRANSCODER_EDP)
  501. tmp |= BLM_TRANSCODER_EDP;
  502. else
  503. tmp |= BLM_PIPE(cpu_transcoder);
  504. tmp &= ~BLM_PWM_ENABLE;
  505. I915_WRITE(reg, tmp);
  506. POSTING_READ(reg);
  507. I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
  508. if (HAS_PCH_SPLIT(dev) &&
  509. !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) {
  510. tmp = I915_READ(BLC_PWM_PCH_CTL1);
  511. tmp |= BLM_PCH_PWM_ENABLE;
  512. tmp &= ~BLM_PCH_OVERRIDE_ENABLE;
  513. I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
  514. }
  515. }
  516. set_level:
  517. /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
  518. * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
  519. * registers are set.
  520. */
  521. dev_priv->backlight.enabled = true;
  522. intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
  523. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  524. }
  525. static void intel_panel_init_backlight(struct drm_device *dev)
  526. {
  527. struct drm_i915_private *dev_priv = dev->dev_private;
  528. dev_priv->backlight.level = intel_panel_get_backlight(dev);
  529. dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
  530. }
  531. enum drm_connector_status
  532. intel_panel_detect(struct drm_device *dev)
  533. {
  534. struct drm_i915_private *dev_priv = dev->dev_private;
  535. /* Assume that the BIOS does not lie through the OpRegion... */
  536. if (!i915_panel_ignore_lid && dev_priv->opregion.lid_state) {
  537. return ioread32(dev_priv->opregion.lid_state) & 0x1 ?
  538. connector_status_connected :
  539. connector_status_disconnected;
  540. }
  541. switch (i915_panel_ignore_lid) {
  542. case -2:
  543. return connector_status_connected;
  544. case -1:
  545. return connector_status_disconnected;
  546. default:
  547. return connector_status_unknown;
  548. }
  549. }
  550. #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
  551. static int intel_panel_update_status(struct backlight_device *bd)
  552. {
  553. struct drm_device *dev = bl_get_data(bd);
  554. intel_panel_set_backlight(dev, bd->props.brightness,
  555. bd->props.max_brightness);
  556. return 0;
  557. }
  558. static int intel_panel_get_brightness(struct backlight_device *bd)
  559. {
  560. struct drm_device *dev = bl_get_data(bd);
  561. return intel_panel_get_backlight(dev);
  562. }
  563. static const struct backlight_ops intel_panel_bl_ops = {
  564. .update_status = intel_panel_update_status,
  565. .get_brightness = intel_panel_get_brightness,
  566. };
  567. int intel_panel_setup_backlight(struct drm_connector *connector)
  568. {
  569. struct drm_device *dev = connector->dev;
  570. struct drm_i915_private *dev_priv = dev->dev_private;
  571. struct backlight_properties props;
  572. unsigned long flags;
  573. intel_panel_init_backlight(dev);
  574. if (WARN_ON(dev_priv->backlight.device))
  575. return -ENODEV;
  576. memset(&props, 0, sizeof(props));
  577. props.type = BACKLIGHT_RAW;
  578. props.brightness = dev_priv->backlight.level;
  579. spin_lock_irqsave(&dev_priv->backlight.lock, flags);
  580. props.max_brightness = intel_panel_get_max_backlight(dev);
  581. spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
  582. if (props.max_brightness == 0) {
  583. DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
  584. return -ENODEV;
  585. }
  586. dev_priv->backlight.device =
  587. backlight_device_register("intel_backlight",
  588. &connector->kdev, dev,
  589. &intel_panel_bl_ops, &props);
  590. if (IS_ERR(dev_priv->backlight.device)) {
  591. DRM_ERROR("Failed to register backlight: %ld\n",
  592. PTR_ERR(dev_priv->backlight.device));
  593. dev_priv->backlight.device = NULL;
  594. return -ENODEV;
  595. }
  596. return 0;
  597. }
  598. void intel_panel_destroy_backlight(struct drm_device *dev)
  599. {
  600. struct drm_i915_private *dev_priv = dev->dev_private;
  601. if (dev_priv->backlight.device) {
  602. backlight_device_unregister(dev_priv->backlight.device);
  603. dev_priv->backlight.device = NULL;
  604. }
  605. }
  606. #else
  607. int intel_panel_setup_backlight(struct drm_connector *connector)
  608. {
  609. intel_panel_init_backlight(connector->dev);
  610. return 0;
  611. }
  612. void intel_panel_destroy_backlight(struct drm_device *dev)
  613. {
  614. return;
  615. }
  616. #endif
  617. int intel_panel_init(struct intel_panel *panel,
  618. struct drm_display_mode *fixed_mode)
  619. {
  620. panel->fixed_mode = fixed_mode;
  621. return 0;
  622. }
  623. void intel_panel_fini(struct intel_panel *panel)
  624. {
  625. struct intel_connector *intel_connector =
  626. container_of(panel, struct intel_connector, panel);
  627. if (panel->fixed_mode)
  628. drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode);
  629. }