au1000_eth.c 33 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310
  1. /*
  2. *
  3. * Alchemy Au1x00 ethernet driver
  4. *
  5. * Copyright 2001-2003, 2006 MontaVista Software Inc.
  6. * Copyright 2002 TimeSys Corp.
  7. * Added ethtool/mii-tool support,
  8. * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
  9. * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
  10. * or riemer@riemer-nt.de: fixed the link beat detection with
  11. * ioctls (SIOCGMIIPHY)
  12. * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
  13. * converted to use linux-2.6.x's PHY framework
  14. *
  15. * Author: MontaVista Software, Inc.
  16. * ppopov@mvista.com or source@mvista.com
  17. *
  18. * ########################################################################
  19. *
  20. * This program is free software; you can distribute it and/or modify it
  21. * under the terms of the GNU General Public License (Version 2) as
  22. * published by the Free Software Foundation.
  23. *
  24. * This program is distributed in the hope it will be useful, but WITHOUT
  25. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  26. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  27. * for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License along
  30. * with this program; if not, write to the Free Software Foundation, Inc.,
  31. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  32. *
  33. * ########################################################################
  34. *
  35. *
  36. */
  37. #include <linux/capability.h>
  38. #include <linux/dma-mapping.h>
  39. #include <linux/module.h>
  40. #include <linux/kernel.h>
  41. #include <linux/string.h>
  42. #include <linux/timer.h>
  43. #include <linux/errno.h>
  44. #include <linux/in.h>
  45. #include <linux/ioport.h>
  46. #include <linux/bitops.h>
  47. #include <linux/slab.h>
  48. #include <linux/interrupt.h>
  49. #include <linux/init.h>
  50. #include <linux/netdevice.h>
  51. #include <linux/etherdevice.h>
  52. #include <linux/ethtool.h>
  53. #include <linux/mii.h>
  54. #include <linux/skbuff.h>
  55. #include <linux/delay.h>
  56. #include <linux/crc32.h>
  57. #include <linux/phy.h>
  58. #include <linux/platform_device.h>
  59. #include <asm/cpu.h>
  60. #include <asm/mipsregs.h>
  61. #include <asm/irq.h>
  62. #include <asm/io.h>
  63. #include <asm/processor.h>
  64. #include <au1000.h>
  65. #include <au1xxx_eth.h>
  66. #include <prom.h>
  67. #include "au1000_eth.h"
  68. #ifdef AU1000_ETH_DEBUG
  69. static int au1000_debug = 5;
  70. #else
  71. static int au1000_debug = 3;
  72. #endif
  73. #define DRV_NAME "au1000_eth"
  74. #define DRV_VERSION "1.6"
  75. #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
  76. #define DRV_DESC "Au1xxx on-chip Ethernet driver"
  77. MODULE_AUTHOR(DRV_AUTHOR);
  78. MODULE_DESCRIPTION(DRV_DESC);
  79. MODULE_LICENSE("GPL");
  80. MODULE_VERSION(DRV_VERSION);
  81. /*
  82. * Theory of operation
  83. *
  84. * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
  85. * There are four receive and four transmit descriptors. These
  86. * descriptors are not in memory; rather, they are just a set of
  87. * hardware registers.
  88. *
  89. * Since the Au1000 has a coherent data cache, the receive and
  90. * transmit buffers are allocated from the KSEG0 segment. The
  91. * hardware registers, however, are still mapped at KSEG1 to
  92. * make sure there's no out-of-order writes, and that all writes
  93. * complete immediately.
  94. */
  95. /* These addresses are only used if yamon doesn't tell us what
  96. * the mac address is, and the mac address is not passed on the
  97. * command line.
  98. */
  99. static unsigned char au1000_mac_addr[6] __devinitdata = {
  100. 0x00, 0x50, 0xc2, 0x0c, 0x30, 0x00
  101. };
  102. struct au1000_private *au_macs[NUM_ETH_INTERFACES];
  103. /*
  104. * board-specific configurations
  105. *
  106. * PHY detection algorithm
  107. *
  108. * If phy_static_config is undefined, the PHY setup is
  109. * autodetected:
  110. *
  111. * mii_probe() first searches the current MAC's MII bus for a PHY,
  112. * selecting the first (or last, if phy_search_highest_addr is
  113. * defined) PHY address not already claimed by another netdev.
  114. *
  115. * If nothing was found that way when searching for the 2nd ethernet
  116. * controller's PHY and phy1_search_mac0 is defined, then
  117. * the first MII bus is searched as well for an unclaimed PHY; this is
  118. * needed in case of a dual-PHY accessible only through the MAC0's MII
  119. * bus.
  120. *
  121. * Finally, if no PHY is found, then the corresponding ethernet
  122. * controller is not registered to the network subsystem.
  123. */
  124. /* autodetection defaults: phy1_search_mac0 */
  125. /* static PHY setup
  126. *
  127. * most boards PHY setup should be detectable properly with the
  128. * autodetection algorithm in mii_probe(), but in some cases (e.g. if
  129. * you have a switch attached, or want to use the PHY's interrupt
  130. * notification capabilities) you can provide a static PHY
  131. * configuration here
  132. *
  133. * IRQs may only be set, if a PHY address was configured
  134. * If a PHY address is given, also a bus id is required to be set
  135. *
  136. * ps: make sure the used irqs are configured properly in the board
  137. * specific irq-map
  138. */
  139. static void au1000_enable_mac(struct net_device *dev, int force_reset)
  140. {
  141. unsigned long flags;
  142. struct au1000_private *aup = netdev_priv(dev);
  143. spin_lock_irqsave(&aup->lock, flags);
  144. if(force_reset || (!aup->mac_enabled)) {
  145. *aup->enable = MAC_EN_CLOCK_ENABLE;
  146. au_sync_delay(2);
  147. *aup->enable = (MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
  148. | MAC_EN_CLOCK_ENABLE);
  149. au_sync_delay(2);
  150. aup->mac_enabled = 1;
  151. }
  152. spin_unlock_irqrestore(&aup->lock, flags);
  153. }
  154. /*
  155. * MII operations
  156. */
  157. static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
  158. {
  159. struct au1000_private *aup = netdev_priv(dev);
  160. volatile u32 *const mii_control_reg = &aup->mac->mii_control;
  161. volatile u32 *const mii_data_reg = &aup->mac->mii_data;
  162. u32 timedout = 20;
  163. u32 mii_control;
  164. while (*mii_control_reg & MAC_MII_BUSY) {
  165. mdelay(1);
  166. if (--timedout == 0) {
  167. printk(KERN_ERR "%s: read_MII busy timeout!!\n",
  168. dev->name);
  169. return -1;
  170. }
  171. }
  172. mii_control = MAC_SET_MII_SELECT_REG(reg) |
  173. MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
  174. *mii_control_reg = mii_control;
  175. timedout = 20;
  176. while (*mii_control_reg & MAC_MII_BUSY) {
  177. mdelay(1);
  178. if (--timedout == 0) {
  179. printk(KERN_ERR "%s: mdio_read busy timeout!!\n",
  180. dev->name);
  181. return -1;
  182. }
  183. }
  184. return (int)*mii_data_reg;
  185. }
  186. static void au1000_mdio_write(struct net_device *dev, int phy_addr,
  187. int reg, u16 value)
  188. {
  189. struct au1000_private *aup = netdev_priv(dev);
  190. volatile u32 *const mii_control_reg = &aup->mac->mii_control;
  191. volatile u32 *const mii_data_reg = &aup->mac->mii_data;
  192. u32 timedout = 20;
  193. u32 mii_control;
  194. while (*mii_control_reg & MAC_MII_BUSY) {
  195. mdelay(1);
  196. if (--timedout == 0) {
  197. printk(KERN_ERR "%s: mdio_write busy timeout!!\n",
  198. dev->name);
  199. return;
  200. }
  201. }
  202. mii_control = MAC_SET_MII_SELECT_REG(reg) |
  203. MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
  204. *mii_data_reg = value;
  205. *mii_control_reg = mii_control;
  206. }
  207. static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
  208. {
  209. /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
  210. * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus) */
  211. struct net_device *const dev = bus->priv;
  212. au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
  213. * mii_bus is enabled */
  214. return au1000_mdio_read(dev, phy_addr, regnum);
  215. }
  216. static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
  217. u16 value)
  218. {
  219. struct net_device *const dev = bus->priv;
  220. au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
  221. * mii_bus is enabled */
  222. au1000_mdio_write(dev, phy_addr, regnum, value);
  223. return 0;
  224. }
  225. static int au1000_mdiobus_reset(struct mii_bus *bus)
  226. {
  227. struct net_device *const dev = bus->priv;
  228. au1000_enable_mac(dev, 0); /* make sure the MAC associated with this
  229. * mii_bus is enabled */
  230. return 0;
  231. }
  232. static void au1000_hard_stop(struct net_device *dev)
  233. {
  234. struct au1000_private *aup = netdev_priv(dev);
  235. if (au1000_debug > 4)
  236. printk(KERN_INFO "%s: hard stop\n", dev->name);
  237. aup->mac->control &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
  238. au_sync_delay(10);
  239. }
  240. static void au1000_enable_rx_tx(struct net_device *dev)
  241. {
  242. struct au1000_private *aup = netdev_priv(dev);
  243. if (au1000_debug > 4)
  244. printk(KERN_INFO "%s: enable_rx_tx\n", dev->name);
  245. aup->mac->control |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
  246. au_sync_delay(10);
  247. }
  248. static void
  249. au1000_adjust_link(struct net_device *dev)
  250. {
  251. struct au1000_private *aup = netdev_priv(dev);
  252. struct phy_device *phydev = aup->phy_dev;
  253. unsigned long flags;
  254. int status_change = 0;
  255. BUG_ON(!aup->phy_dev);
  256. spin_lock_irqsave(&aup->lock, flags);
  257. if (phydev->link && (aup->old_speed != phydev->speed)) {
  258. /* speed changed */
  259. switch (phydev->speed) {
  260. case SPEED_10:
  261. case SPEED_100:
  262. break;
  263. default:
  264. printk(KERN_WARNING
  265. "%s: Speed (%d) is not 10/100 ???\n",
  266. dev->name, phydev->speed);
  267. break;
  268. }
  269. aup->old_speed = phydev->speed;
  270. status_change = 1;
  271. }
  272. if (phydev->link && (aup->old_duplex != phydev->duplex)) {
  273. /* duplex mode changed */
  274. /* switching duplex mode requires to disable rx and tx! */
  275. au1000_hard_stop(dev);
  276. if (DUPLEX_FULL == phydev->duplex)
  277. aup->mac->control = ((aup->mac->control
  278. | MAC_FULL_DUPLEX)
  279. & ~MAC_DISABLE_RX_OWN);
  280. else
  281. aup->mac->control = ((aup->mac->control
  282. & ~MAC_FULL_DUPLEX)
  283. | MAC_DISABLE_RX_OWN);
  284. au_sync_delay(1);
  285. au1000_enable_rx_tx(dev);
  286. aup->old_duplex = phydev->duplex;
  287. status_change = 1;
  288. }
  289. if (phydev->link != aup->old_link) {
  290. /* link state changed */
  291. if (!phydev->link) {
  292. /* link went down */
  293. aup->old_speed = 0;
  294. aup->old_duplex = -1;
  295. }
  296. aup->old_link = phydev->link;
  297. status_change = 1;
  298. }
  299. spin_unlock_irqrestore(&aup->lock, flags);
  300. if (status_change) {
  301. if (phydev->link)
  302. printk(KERN_INFO "%s: link up (%d/%s)\n",
  303. dev->name, phydev->speed,
  304. DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
  305. else
  306. printk(KERN_INFO "%s: link down\n", dev->name);
  307. }
  308. }
  309. static int au1000_mii_probe (struct net_device *dev)
  310. {
  311. struct au1000_private *const aup = netdev_priv(dev);
  312. struct phy_device *phydev = NULL;
  313. if (aup->phy_static_config) {
  314. BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
  315. if (aup->phy_addr)
  316. phydev = aup->mii_bus->phy_map[aup->phy_addr];
  317. else
  318. printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n",
  319. dev->name);
  320. return 0;
  321. } else {
  322. int phy_addr;
  323. /* find the first (lowest address) PHY on the current MAC's MII bus */
  324. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
  325. if (aup->mii_bus->phy_map[phy_addr]) {
  326. phydev = aup->mii_bus->phy_map[phy_addr];
  327. if (!aup->phy_search_highest_addr)
  328. break; /* break out with first one found */
  329. }
  330. if (aup->phy1_search_mac0) {
  331. /* try harder to find a PHY */
  332. if (!phydev && (aup->mac_id == 1)) {
  333. /* no PHY found, maybe we have a dual PHY? */
  334. printk (KERN_INFO DRV_NAME ": no PHY found on MAC1, "
  335. "let's see if it's attached to MAC0...\n");
  336. /* find the first (lowest address) non-attached PHY on
  337. * the MAC0 MII bus */
  338. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
  339. struct phy_device *const tmp_phydev =
  340. aup->mii_bus->phy_map[phy_addr];
  341. if (aup->mac_id == 1)
  342. break;
  343. if (!tmp_phydev)
  344. continue; /* no PHY here... */
  345. if (tmp_phydev->attached_dev)
  346. continue; /* already claimed by MAC0 */
  347. phydev = tmp_phydev;
  348. break; /* found it */
  349. }
  350. }
  351. }
  352. }
  353. if (!phydev) {
  354. printk (KERN_ERR DRV_NAME ":%s: no PHY found\n", dev->name);
  355. return -1;
  356. }
  357. /* now we are supposed to have a proper phydev, to attach to... */
  358. BUG_ON(phydev->attached_dev);
  359. phydev = phy_connect(dev, dev_name(&phydev->dev), &au1000_adjust_link,
  360. 0, PHY_INTERFACE_MODE_MII);
  361. if (IS_ERR(phydev)) {
  362. printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
  363. return PTR_ERR(phydev);
  364. }
  365. /* mask with MAC supported features */
  366. phydev->supported &= (SUPPORTED_10baseT_Half
  367. | SUPPORTED_10baseT_Full
  368. | SUPPORTED_100baseT_Half
  369. | SUPPORTED_100baseT_Full
  370. | SUPPORTED_Autoneg
  371. /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
  372. | SUPPORTED_MII
  373. | SUPPORTED_TP);
  374. phydev->advertising = phydev->supported;
  375. aup->old_link = 0;
  376. aup->old_speed = 0;
  377. aup->old_duplex = -1;
  378. aup->phy_dev = phydev;
  379. printk(KERN_INFO "%s: attached PHY driver [%s] "
  380. "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name,
  381. phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
  382. return 0;
  383. }
  384. /*
  385. * Buffer allocation/deallocation routines. The buffer descriptor returned
  386. * has the virtual and dma address of a buffer suitable for
  387. * both, receive and transmit operations.
  388. */
  389. static db_dest_t *au1000_GetFreeDB(struct au1000_private *aup)
  390. {
  391. db_dest_t *pDB;
  392. pDB = aup->pDBfree;
  393. if (pDB) {
  394. aup->pDBfree = pDB->pnext;
  395. }
  396. return pDB;
  397. }
  398. void au1000_ReleaseDB(struct au1000_private *aup, db_dest_t *pDB)
  399. {
  400. db_dest_t *pDBfree = aup->pDBfree;
  401. if (pDBfree)
  402. pDBfree->pnext = pDB;
  403. aup->pDBfree = pDB;
  404. }
  405. static void au1000_reset_mac_unlocked(struct net_device *dev)
  406. {
  407. struct au1000_private *const aup = netdev_priv(dev);
  408. int i;
  409. au1000_hard_stop(dev);
  410. *aup->enable = MAC_EN_CLOCK_ENABLE;
  411. au_sync_delay(2);
  412. *aup->enable = 0;
  413. au_sync_delay(2);
  414. aup->tx_full = 0;
  415. for (i = 0; i < NUM_RX_DMA; i++) {
  416. /* reset control bits */
  417. aup->rx_dma_ring[i]->buff_stat &= ~0xf;
  418. }
  419. for (i = 0; i < NUM_TX_DMA; i++) {
  420. /* reset control bits */
  421. aup->tx_dma_ring[i]->buff_stat &= ~0xf;
  422. }
  423. aup->mac_enabled = 0;
  424. }
  425. static void au1000_reset_mac(struct net_device *dev)
  426. {
  427. struct au1000_private *const aup = netdev_priv(dev);
  428. unsigned long flags;
  429. if (au1000_debug > 4)
  430. printk(KERN_INFO "%s: reset mac, aup %x\n",
  431. dev->name, (unsigned)aup);
  432. spin_lock_irqsave(&aup->lock, flags);
  433. au1000_reset_mac_unlocked (dev);
  434. spin_unlock_irqrestore(&aup->lock, flags);
  435. }
  436. /*
  437. * Setup the receive and transmit "rings". These pointers are the addresses
  438. * of the rx and tx MAC DMA registers so they are fixed by the hardware --
  439. * these are not descriptors sitting in memory.
  440. */
  441. static void
  442. au1000_setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
  443. {
  444. int i;
  445. for (i = 0; i < NUM_RX_DMA; i++) {
  446. aup->rx_dma_ring[i] =
  447. (volatile rx_dma_t *) (rx_base + sizeof(rx_dma_t)*i);
  448. }
  449. for (i = 0; i < NUM_TX_DMA; i++) {
  450. aup->tx_dma_ring[i] =
  451. (volatile tx_dma_t *) (tx_base + sizeof(tx_dma_t)*i);
  452. }
  453. }
  454. /*
  455. * ethtool operations
  456. */
  457. static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  458. {
  459. struct au1000_private *aup = netdev_priv(dev);
  460. if (aup->phy_dev)
  461. return phy_ethtool_gset(aup->phy_dev, cmd);
  462. return -EINVAL;
  463. }
  464. static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  465. {
  466. struct au1000_private *aup = netdev_priv(dev);
  467. if (!capable(CAP_NET_ADMIN))
  468. return -EPERM;
  469. if (aup->phy_dev)
  470. return phy_ethtool_sset(aup->phy_dev, cmd);
  471. return -EINVAL;
  472. }
  473. static void
  474. au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  475. {
  476. struct au1000_private *aup = netdev_priv(dev);
  477. strcpy(info->driver, DRV_NAME);
  478. strcpy(info->version, DRV_VERSION);
  479. info->fw_version[0] = '\0';
  480. sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
  481. info->regdump_len = 0;
  482. }
  483. static const struct ethtool_ops au1000_ethtool_ops = {
  484. .get_settings = au1000_get_settings,
  485. .set_settings = au1000_set_settings,
  486. .get_drvinfo = au1000_get_drvinfo,
  487. .get_link = ethtool_op_get_link,
  488. };
  489. /*
  490. * Initialize the interface.
  491. *
  492. * When the device powers up, the clocks are disabled and the
  493. * mac is in reset state. When the interface is closed, we
  494. * do the same -- reset the device and disable the clocks to
  495. * conserve power. Thus, whenever au1000_init() is called,
  496. * the device should already be in reset state.
  497. */
  498. static int au1000_init(struct net_device *dev)
  499. {
  500. struct au1000_private *aup = netdev_priv(dev);
  501. unsigned long flags;
  502. int i;
  503. u32 control;
  504. if (au1000_debug > 4)
  505. printk("%s: au1000_init\n", dev->name);
  506. /* bring the device out of reset */
  507. au1000_enable_mac(dev, 1);
  508. spin_lock_irqsave(&aup->lock, flags);
  509. aup->mac->control = 0;
  510. aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
  511. aup->tx_tail = aup->tx_head;
  512. aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
  513. aup->mac->mac_addr_high = dev->dev_addr[5]<<8 | dev->dev_addr[4];
  514. aup->mac->mac_addr_low = dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
  515. dev->dev_addr[1]<<8 | dev->dev_addr[0];
  516. for (i = 0; i < NUM_RX_DMA; i++) {
  517. aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
  518. }
  519. au_sync();
  520. control = MAC_RX_ENABLE | MAC_TX_ENABLE;
  521. #ifndef CONFIG_CPU_LITTLE_ENDIAN
  522. control |= MAC_BIG_ENDIAN;
  523. #endif
  524. if (aup->phy_dev) {
  525. if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
  526. control |= MAC_FULL_DUPLEX;
  527. else
  528. control |= MAC_DISABLE_RX_OWN;
  529. } else { /* PHY-less op, assume full-duplex */
  530. control |= MAC_FULL_DUPLEX;
  531. }
  532. aup->mac->control = control;
  533. aup->mac->vlan1_tag = 0x8100; /* activate vlan support */
  534. au_sync();
  535. spin_unlock_irqrestore(&aup->lock, flags);
  536. return 0;
  537. }
  538. static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
  539. {
  540. struct net_device_stats *ps = &dev->stats;
  541. ps->rx_packets++;
  542. if (status & RX_MCAST_FRAME)
  543. ps->multicast++;
  544. if (status & RX_ERROR) {
  545. ps->rx_errors++;
  546. if (status & RX_MISSED_FRAME)
  547. ps->rx_missed_errors++;
  548. if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
  549. ps->rx_length_errors++;
  550. if (status & RX_CRC_ERROR)
  551. ps->rx_crc_errors++;
  552. if (status & RX_COLL)
  553. ps->collisions++;
  554. } else
  555. ps->rx_bytes += status & RX_FRAME_LEN_MASK;
  556. }
  557. /*
  558. * Au1000 receive routine.
  559. */
  560. static int au1000_rx(struct net_device *dev)
  561. {
  562. struct au1000_private *aup = netdev_priv(dev);
  563. struct sk_buff *skb;
  564. volatile rx_dma_t *prxd;
  565. u32 buff_stat, status;
  566. db_dest_t *pDB;
  567. u32 frmlen;
  568. if (au1000_debug > 5)
  569. printk("%s: au1000_rx head %d\n", dev->name, aup->rx_head);
  570. prxd = aup->rx_dma_ring[aup->rx_head];
  571. buff_stat = prxd->buff_stat;
  572. while (buff_stat & RX_T_DONE) {
  573. status = prxd->status;
  574. pDB = aup->rx_db_inuse[aup->rx_head];
  575. au1000_update_rx_stats(dev, status);
  576. if (!(status & RX_ERROR)) {
  577. /* good frame */
  578. frmlen = (status & RX_FRAME_LEN_MASK);
  579. frmlen -= 4; /* Remove FCS */
  580. skb = dev_alloc_skb(frmlen + 2);
  581. if (skb == NULL) {
  582. printk(KERN_ERR
  583. "%s: Memory squeeze, dropping packet.\n",
  584. dev->name);
  585. dev->stats.rx_dropped++;
  586. continue;
  587. }
  588. skb_reserve(skb, 2); /* 16 byte IP header align */
  589. skb_copy_to_linear_data(skb,
  590. (unsigned char *)pDB->vaddr, frmlen);
  591. skb_put(skb, frmlen);
  592. skb->protocol = eth_type_trans(skb, dev);
  593. netif_rx(skb); /* pass the packet to upper layers */
  594. } else {
  595. if (au1000_debug > 4) {
  596. if (status & RX_MISSED_FRAME)
  597. printk("rx miss\n");
  598. if (status & RX_WDOG_TIMER)
  599. printk("rx wdog\n");
  600. if (status & RX_RUNT)
  601. printk("rx runt\n");
  602. if (status & RX_OVERLEN)
  603. printk("rx overlen\n");
  604. if (status & RX_COLL)
  605. printk("rx coll\n");
  606. if (status & RX_MII_ERROR)
  607. printk("rx mii error\n");
  608. if (status & RX_CRC_ERROR)
  609. printk("rx crc error\n");
  610. if (status & RX_LEN_ERROR)
  611. printk("rx len error\n");
  612. if (status & RX_U_CNTRL_FRAME)
  613. printk("rx u control frame\n");
  614. }
  615. }
  616. prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
  617. aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
  618. au_sync();
  619. /* next descriptor */
  620. prxd = aup->rx_dma_ring[aup->rx_head];
  621. buff_stat = prxd->buff_stat;
  622. }
  623. return 0;
  624. }
  625. static void au1000_update_tx_stats(struct net_device *dev, u32 status)
  626. {
  627. struct au1000_private *aup = netdev_priv(dev);
  628. struct net_device_stats *ps = &dev->stats;
  629. if (status & TX_FRAME_ABORTED) {
  630. if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
  631. if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
  632. /* any other tx errors are only valid
  633. * in half duplex mode */
  634. ps->tx_errors++;
  635. ps->tx_aborted_errors++;
  636. }
  637. } else {
  638. ps->tx_errors++;
  639. ps->tx_aborted_errors++;
  640. if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
  641. ps->tx_carrier_errors++;
  642. }
  643. }
  644. }
  645. /*
  646. * Called from the interrupt service routine to acknowledge
  647. * the TX DONE bits. This is a must if the irq is setup as
  648. * edge triggered.
  649. */
  650. static void au1000_tx_ack(struct net_device *dev)
  651. {
  652. struct au1000_private *aup = netdev_priv(dev);
  653. volatile tx_dma_t *ptxd;
  654. ptxd = aup->tx_dma_ring[aup->tx_tail];
  655. while (ptxd->buff_stat & TX_T_DONE) {
  656. au1000_update_tx_stats(dev, ptxd->status);
  657. ptxd->buff_stat &= ~TX_T_DONE;
  658. ptxd->len = 0;
  659. au_sync();
  660. aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
  661. ptxd = aup->tx_dma_ring[aup->tx_tail];
  662. if (aup->tx_full) {
  663. aup->tx_full = 0;
  664. netif_wake_queue(dev);
  665. }
  666. }
  667. }
  668. /*
  669. * Au1000 interrupt service routine.
  670. */
  671. static irqreturn_t au1000_interrupt(int irq, void *dev_id)
  672. {
  673. struct net_device *dev = dev_id;
  674. /* Handle RX interrupts first to minimize chance of overrun */
  675. au1000_rx(dev);
  676. au1000_tx_ack(dev);
  677. return IRQ_RETVAL(1);
  678. }
  679. static int au1000_open(struct net_device *dev)
  680. {
  681. int retval;
  682. struct au1000_private *aup = netdev_priv(dev);
  683. if (au1000_debug > 4)
  684. printk("%s: open: dev=%p\n", dev->name, dev);
  685. retval = request_irq(dev->irq, au1000_interrupt, 0,
  686. dev->name, dev);
  687. if (retval) {
  688. printk(KERN_ERR "%s: unable to get IRQ %d\n",
  689. dev->name, dev->irq);
  690. return retval;
  691. }
  692. retval = au1000_init(dev);
  693. if (retval) {
  694. printk(KERN_ERR "%s: error in au1000_init\n", dev->name);
  695. free_irq(dev->irq, dev);
  696. return retval;
  697. }
  698. if (aup->phy_dev) {
  699. /* cause the PHY state machine to schedule a link state check */
  700. aup->phy_dev->state = PHY_CHANGELINK;
  701. phy_start(aup->phy_dev);
  702. }
  703. netif_start_queue(dev);
  704. if (au1000_debug > 4)
  705. printk("%s: open: Initialization done.\n", dev->name);
  706. return 0;
  707. }
  708. static int au1000_close(struct net_device *dev)
  709. {
  710. unsigned long flags;
  711. struct au1000_private *const aup = netdev_priv(dev);
  712. if (au1000_debug > 4)
  713. printk("%s: close: dev=%p\n", dev->name, dev);
  714. if (aup->phy_dev)
  715. phy_stop(aup->phy_dev);
  716. spin_lock_irqsave(&aup->lock, flags);
  717. au1000_reset_mac_unlocked (dev);
  718. /* stop the device */
  719. netif_stop_queue(dev);
  720. /* disable the interrupt */
  721. free_irq(dev->irq, dev);
  722. spin_unlock_irqrestore(&aup->lock, flags);
  723. return 0;
  724. }
  725. /*
  726. * Au1000 transmit routine.
  727. */
  728. static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
  729. {
  730. struct au1000_private *aup = netdev_priv(dev);
  731. struct net_device_stats *ps = &dev->stats;
  732. volatile tx_dma_t *ptxd;
  733. u32 buff_stat;
  734. db_dest_t *pDB;
  735. int i;
  736. if (au1000_debug > 5)
  737. printk("%s: tx: aup %x len=%d, data=%p, head %d\n",
  738. dev->name, (unsigned)aup, skb->len,
  739. skb->data, aup->tx_head);
  740. ptxd = aup->tx_dma_ring[aup->tx_head];
  741. buff_stat = ptxd->buff_stat;
  742. if (buff_stat & TX_DMA_ENABLE) {
  743. /* We've wrapped around and the transmitter is still busy */
  744. netif_stop_queue(dev);
  745. aup->tx_full = 1;
  746. return NETDEV_TX_BUSY;
  747. } else if (buff_stat & TX_T_DONE) {
  748. au1000_update_tx_stats(dev, ptxd->status);
  749. ptxd->len = 0;
  750. }
  751. if (aup->tx_full) {
  752. aup->tx_full = 0;
  753. netif_wake_queue(dev);
  754. }
  755. pDB = aup->tx_db_inuse[aup->tx_head];
  756. skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
  757. if (skb->len < ETH_ZLEN) {
  758. for (i = skb->len; i < ETH_ZLEN; i++) {
  759. ((char *)pDB->vaddr)[i] = 0;
  760. }
  761. ptxd->len = ETH_ZLEN;
  762. } else
  763. ptxd->len = skb->len;
  764. ps->tx_packets++;
  765. ps->tx_bytes += ptxd->len;
  766. ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
  767. au_sync();
  768. dev_kfree_skb(skb);
  769. aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
  770. dev->trans_start = jiffies;
  771. return NETDEV_TX_OK;
  772. }
  773. /*
  774. * The Tx ring has been full longer than the watchdog timeout
  775. * value. The transmitter must be hung?
  776. */
  777. static void au1000_tx_timeout(struct net_device *dev)
  778. {
  779. printk(KERN_ERR "%s: au1000_tx_timeout: dev=%p\n", dev->name, dev);
  780. au1000_reset_mac(dev);
  781. au1000_init(dev);
  782. dev->trans_start = jiffies;
  783. netif_wake_queue(dev);
  784. }
  785. static void au1000_multicast_list(struct net_device *dev)
  786. {
  787. struct au1000_private *aup = netdev_priv(dev);
  788. if (au1000_debug > 4)
  789. printk("%s: au1000_multicast_list: flags=%x\n", dev->name, dev->flags);
  790. if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
  791. aup->mac->control |= MAC_PROMISCUOUS;
  792. } else if ((dev->flags & IFF_ALLMULTI) ||
  793. netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
  794. aup->mac->control |= MAC_PASS_ALL_MULTI;
  795. aup->mac->control &= ~MAC_PROMISCUOUS;
  796. printk(KERN_INFO "%s: Pass all multicast\n", dev->name);
  797. } else {
  798. struct netdev_hw_addr *ha;
  799. u32 mc_filter[2]; /* Multicast hash filter */
  800. mc_filter[1] = mc_filter[0] = 0;
  801. netdev_for_each_mc_addr(ha, dev)
  802. set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
  803. (long *)mc_filter);
  804. aup->mac->multi_hash_high = mc_filter[1];
  805. aup->mac->multi_hash_low = mc_filter[0];
  806. aup->mac->control &= ~MAC_PROMISCUOUS;
  807. aup->mac->control |= MAC_HASH_MODE;
  808. }
  809. }
  810. static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  811. {
  812. struct au1000_private *aup = netdev_priv(dev);
  813. if (!netif_running(dev))
  814. return -EINVAL;
  815. if (!aup->phy_dev)
  816. return -EINVAL; /* PHY not controllable */
  817. return phy_mii_ioctl(aup->phy_dev, if_mii(rq), cmd);
  818. }
  819. static const struct net_device_ops au1000_netdev_ops = {
  820. .ndo_open = au1000_open,
  821. .ndo_stop = au1000_close,
  822. .ndo_start_xmit = au1000_tx,
  823. .ndo_set_multicast_list = au1000_multicast_list,
  824. .ndo_do_ioctl = au1000_ioctl,
  825. .ndo_tx_timeout = au1000_tx_timeout,
  826. .ndo_set_mac_address = eth_mac_addr,
  827. .ndo_validate_addr = eth_validate_addr,
  828. .ndo_change_mtu = eth_change_mtu,
  829. };
  830. static int __devinit au1000_probe(struct platform_device *pdev)
  831. {
  832. static unsigned version_printed;
  833. struct au1000_private *aup = NULL;
  834. struct au1000_eth_platform_data *pd;
  835. struct net_device *dev = NULL;
  836. db_dest_t *pDB, *pDBfree;
  837. int irq, i, err = 0;
  838. struct resource *base, *macen;
  839. char ethaddr[6];
  840. base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  841. if (!base) {
  842. printk(KERN_ERR DRV_NAME ": failed to retrieve base register\n");
  843. err = -ENODEV;
  844. goto out;
  845. }
  846. macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  847. if (!macen) {
  848. printk(KERN_ERR DRV_NAME ": failed to retrieve MAC Enable register\n");
  849. err = -ENODEV;
  850. goto out;
  851. }
  852. irq = platform_get_irq(pdev, 0);
  853. if (irq < 0) {
  854. printk(KERN_ERR DRV_NAME ": failed to retrieve IRQ\n");
  855. err = -ENODEV;
  856. goto out;
  857. }
  858. if (!request_mem_region(base->start, resource_size(base), pdev->name)) {
  859. printk(KERN_ERR DRV_NAME ": failed to request memory region for base registers\n");
  860. err = -ENXIO;
  861. goto out;
  862. }
  863. if (!request_mem_region(macen->start, resource_size(macen), pdev->name)) {
  864. printk(KERN_ERR DRV_NAME ": failed to request memory region for MAC enable register\n");
  865. err = -ENXIO;
  866. goto err_request;
  867. }
  868. dev = alloc_etherdev(sizeof(struct au1000_private));
  869. if (!dev) {
  870. printk(KERN_ERR "%s: alloc_etherdev failed\n", DRV_NAME);
  871. err = -ENOMEM;
  872. goto err_alloc;
  873. }
  874. SET_NETDEV_DEV(dev, &pdev->dev);
  875. platform_set_drvdata(pdev, dev);
  876. aup = netdev_priv(dev);
  877. spin_lock_init(&aup->lock);
  878. /* Allocate the data buffers */
  879. /* Snooping works fine with eth on all au1xxx */
  880. aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
  881. (NUM_TX_BUFFS + NUM_RX_BUFFS),
  882. &aup->dma_addr, 0);
  883. if (!aup->vaddr) {
  884. printk(KERN_ERR DRV_NAME ": failed to allocate data buffers\n");
  885. err = -ENOMEM;
  886. goto err_vaddr;
  887. }
  888. /* aup->mac is the base address of the MAC's registers */
  889. aup->mac = (volatile mac_reg_t *)ioremap_nocache(base->start, resource_size(base));
  890. if (!aup->mac) {
  891. printk(KERN_ERR DRV_NAME ": failed to ioremap MAC registers\n");
  892. err = -ENXIO;
  893. goto err_remap1;
  894. }
  895. /* Setup some variables for quick register address access */
  896. aup->enable = (volatile u32 *)ioremap_nocache(macen->start, resource_size(macen));
  897. if (!aup->enable) {
  898. printk(KERN_ERR DRV_NAME ": failed to ioremap MAC enable register\n");
  899. err = -ENXIO;
  900. goto err_remap2;
  901. }
  902. aup->mac_id = pdev->id;
  903. if (pdev->id == 0) {
  904. if (prom_get_ethernet_addr(ethaddr) == 0)
  905. memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr));
  906. else {
  907. printk(KERN_INFO "%s: No MAC address found\n",
  908. dev->name);
  909. /* Use the hard coded MAC addresses */
  910. }
  911. au1000_setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
  912. } else if (pdev->id == 1)
  913. au1000_setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
  914. /*
  915. * Assign to the Ethernet ports two consecutive MAC addresses
  916. * to match those that are printed on their stickers
  917. */
  918. memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr));
  919. dev->dev_addr[5] += pdev->id;
  920. *aup->enable = 0;
  921. aup->mac_enabled = 0;
  922. pd = pdev->dev.platform_data;
  923. if (!pd) {
  924. printk(KERN_INFO DRV_NAME ": no platform_data passed, PHY search on MAC0\n");
  925. aup->phy1_search_mac0 = 1;
  926. } else {
  927. aup->phy_static_config = pd->phy_static_config;
  928. aup->phy_search_highest_addr = pd->phy_search_highest_addr;
  929. aup->phy1_search_mac0 = pd->phy1_search_mac0;
  930. aup->phy_addr = pd->phy_addr;
  931. aup->phy_busid = pd->phy_busid;
  932. aup->phy_irq = pd->phy_irq;
  933. }
  934. if (aup->phy_busid && aup->phy_busid > 0) {
  935. printk(KERN_ERR DRV_NAME ": MAC0-associated PHY attached 2nd MACs MII"
  936. "bus not supported yet\n");
  937. err = -ENODEV;
  938. goto err_mdiobus_alloc;
  939. }
  940. aup->mii_bus = mdiobus_alloc();
  941. if (aup->mii_bus == NULL) {
  942. printk(KERN_ERR DRV_NAME ": failed to allocate mdiobus structure\n");
  943. err = -ENOMEM;
  944. goto err_mdiobus_alloc;
  945. }
  946. aup->mii_bus->priv = dev;
  947. aup->mii_bus->read = au1000_mdiobus_read;
  948. aup->mii_bus->write = au1000_mdiobus_write;
  949. aup->mii_bus->reset = au1000_mdiobus_reset;
  950. aup->mii_bus->name = "au1000_eth_mii";
  951. snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id);
  952. aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
  953. if (aup->mii_bus->irq == NULL)
  954. goto err_out;
  955. for (i = 0; i < PHY_MAX_ADDR; ++i)
  956. aup->mii_bus->irq[i] = PHY_POLL;
  957. /* if known, set corresponding PHY IRQs */
  958. if (aup->phy_static_config)
  959. if (aup->phy_irq && aup->phy_busid == aup->mac_id)
  960. aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
  961. err = mdiobus_register(aup->mii_bus);
  962. if (err) {
  963. printk(KERN_ERR DRV_NAME " failed to register MDIO bus\n");
  964. goto err_mdiobus_reg;
  965. }
  966. if (au1000_mii_probe(dev) != 0)
  967. goto err_out;
  968. pDBfree = NULL;
  969. /* setup the data buffer descriptors and attach a buffer to each one */
  970. pDB = aup->db;
  971. for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
  972. pDB->pnext = pDBfree;
  973. pDBfree = pDB;
  974. pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
  975. pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
  976. pDB++;
  977. }
  978. aup->pDBfree = pDBfree;
  979. for (i = 0; i < NUM_RX_DMA; i++) {
  980. pDB = au1000_GetFreeDB(aup);
  981. if (!pDB) {
  982. goto err_out;
  983. }
  984. aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
  985. aup->rx_db_inuse[i] = pDB;
  986. }
  987. for (i = 0; i < NUM_TX_DMA; i++) {
  988. pDB = au1000_GetFreeDB(aup);
  989. if (!pDB) {
  990. goto err_out;
  991. }
  992. aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
  993. aup->tx_dma_ring[i]->len = 0;
  994. aup->tx_db_inuse[i] = pDB;
  995. }
  996. dev->base_addr = base->start;
  997. dev->irq = irq;
  998. dev->netdev_ops = &au1000_netdev_ops;
  999. SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
  1000. dev->watchdog_timeo = ETH_TX_TIMEOUT;
  1001. /*
  1002. * The boot code uses the ethernet controller, so reset it to start
  1003. * fresh. au1000_init() expects that the device is in reset state.
  1004. */
  1005. au1000_reset_mac(dev);
  1006. err = register_netdev(dev);
  1007. if (err) {
  1008. printk(KERN_ERR DRV_NAME "%s: Cannot register net device, aborting.\n",
  1009. dev->name);
  1010. goto err_out;
  1011. }
  1012. printk("%s: Au1xx0 Ethernet found at 0x%lx, irq %d\n",
  1013. dev->name, (unsigned long)base->start, irq);
  1014. if (version_printed++ == 0)
  1015. printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
  1016. return 0;
  1017. err_out:
  1018. if (aup->mii_bus != NULL)
  1019. mdiobus_unregister(aup->mii_bus);
  1020. /* here we should have a valid dev plus aup-> register addresses
  1021. * so we can reset the mac properly.*/
  1022. au1000_reset_mac(dev);
  1023. for (i = 0; i < NUM_RX_DMA; i++) {
  1024. if (aup->rx_db_inuse[i])
  1025. au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
  1026. }
  1027. for (i = 0; i < NUM_TX_DMA; i++) {
  1028. if (aup->tx_db_inuse[i])
  1029. au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
  1030. }
  1031. err_mdiobus_reg:
  1032. mdiobus_free(aup->mii_bus);
  1033. err_mdiobus_alloc:
  1034. iounmap(aup->enable);
  1035. err_remap2:
  1036. iounmap(aup->mac);
  1037. err_remap1:
  1038. dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
  1039. (void *)aup->vaddr, aup->dma_addr);
  1040. err_vaddr:
  1041. free_netdev(dev);
  1042. err_alloc:
  1043. release_mem_region(macen->start, resource_size(macen));
  1044. err_request:
  1045. release_mem_region(base->start, resource_size(base));
  1046. out:
  1047. return err;
  1048. }
  1049. static int __devexit au1000_remove(struct platform_device *pdev)
  1050. {
  1051. struct net_device *dev = platform_get_drvdata(pdev);
  1052. struct au1000_private *aup = netdev_priv(dev);
  1053. int i;
  1054. struct resource *base, *macen;
  1055. platform_set_drvdata(pdev, NULL);
  1056. unregister_netdev(dev);
  1057. mdiobus_unregister(aup->mii_bus);
  1058. mdiobus_free(aup->mii_bus);
  1059. for (i = 0; i < NUM_RX_DMA; i++)
  1060. if (aup->rx_db_inuse[i])
  1061. au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
  1062. for (i = 0; i < NUM_TX_DMA; i++)
  1063. if (aup->tx_db_inuse[i])
  1064. au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
  1065. dma_free_noncoherent(NULL, MAX_BUF_SIZE *
  1066. (NUM_TX_BUFFS + NUM_RX_BUFFS),
  1067. (void *)aup->vaddr, aup->dma_addr);
  1068. iounmap(aup->mac);
  1069. iounmap(aup->enable);
  1070. base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1071. release_mem_region(base->start, resource_size(base));
  1072. macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1073. release_mem_region(macen->start, resource_size(macen));
  1074. free_netdev(dev);
  1075. return 0;
  1076. }
  1077. static struct platform_driver au1000_eth_driver = {
  1078. .probe = au1000_probe,
  1079. .remove = __devexit_p(au1000_remove),
  1080. .driver = {
  1081. .name = "au1000-eth",
  1082. .owner = THIS_MODULE,
  1083. },
  1084. };
  1085. MODULE_ALIAS("platform:au1000-eth");
  1086. static int __init au1000_init_module(void)
  1087. {
  1088. return platform_driver_register(&au1000_eth_driver);
  1089. }
  1090. static void __exit au1000_exit_module(void)
  1091. {
  1092. platform_driver_unregister(&au1000_eth_driver);
  1093. }
  1094. module_init(au1000_init_module);
  1095. module_exit(au1000_exit_module);