mthca_srq.c 18 KB

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  1. /*
  2. * Copyright (c) 2005 Cisco Systems. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. * $Id: mthca_srq.c 3047 2005-08-10 03:59:35Z roland $
  33. */
  34. #include <linux/slab.h>
  35. #include <linux/string.h>
  36. #include "mthca_dev.h"
  37. #include "mthca_cmd.h"
  38. #include "mthca_memfree.h"
  39. #include "mthca_wqe.h"
  40. enum {
  41. MTHCA_MAX_DIRECT_SRQ_SIZE = 4 * PAGE_SIZE
  42. };
  43. struct mthca_tavor_srq_context {
  44. __be64 wqe_base_ds; /* low 6 bits is descriptor size */
  45. __be32 state_pd;
  46. __be32 lkey;
  47. __be32 uar;
  48. __be16 limit_watermark;
  49. __be16 wqe_cnt;
  50. u32 reserved[2];
  51. };
  52. struct mthca_arbel_srq_context {
  53. __be32 state_logsize_srqn;
  54. __be32 lkey;
  55. __be32 db_index;
  56. __be32 logstride_usrpage;
  57. __be64 wqe_base;
  58. __be32 eq_pd;
  59. __be16 limit_watermark;
  60. __be16 wqe_cnt;
  61. u16 reserved1;
  62. __be16 wqe_counter;
  63. u32 reserved2[3];
  64. };
  65. static void *get_wqe(struct mthca_srq *srq, int n)
  66. {
  67. if (srq->is_direct)
  68. return srq->queue.direct.buf + (n << srq->wqe_shift);
  69. else
  70. return srq->queue.page_list[(n << srq->wqe_shift) >> PAGE_SHIFT].buf +
  71. ((n << srq->wqe_shift) & (PAGE_SIZE - 1));
  72. }
  73. /*
  74. * Return a pointer to the location within a WQE that we're using as a
  75. * link when the WQE is in the free list. We use the imm field
  76. * because in the Tavor case, posting a WQE may overwrite the next
  77. * segment of the previous WQE, but a receive WQE will never touch the
  78. * imm field. This avoids corrupting our free list if the previous
  79. * WQE has already completed and been put on the free list when we
  80. * post the next WQE.
  81. */
  82. static inline int *wqe_to_link(void *wqe)
  83. {
  84. return (int *) (wqe + offsetof(struct mthca_next_seg, imm));
  85. }
  86. static void mthca_tavor_init_srq_context(struct mthca_dev *dev,
  87. struct mthca_pd *pd,
  88. struct mthca_srq *srq,
  89. struct mthca_tavor_srq_context *context)
  90. {
  91. memset(context, 0, sizeof *context);
  92. context->wqe_base_ds = cpu_to_be64(1 << (srq->wqe_shift - 4));
  93. context->state_pd = cpu_to_be32(pd->pd_num);
  94. context->lkey = cpu_to_be32(srq->mr.ibmr.lkey);
  95. if (pd->ibpd.uobject)
  96. context->uar =
  97. cpu_to_be32(to_mucontext(pd->ibpd.uobject->context)->uar.index);
  98. else
  99. context->uar = cpu_to_be32(dev->driver_uar.index);
  100. }
  101. static void mthca_arbel_init_srq_context(struct mthca_dev *dev,
  102. struct mthca_pd *pd,
  103. struct mthca_srq *srq,
  104. struct mthca_arbel_srq_context *context)
  105. {
  106. int logsize;
  107. memset(context, 0, sizeof *context);
  108. logsize = long_log2(srq->max) + srq->wqe_shift;
  109. context->state_logsize_srqn = cpu_to_be32(logsize << 24 | srq->srqn);
  110. context->lkey = cpu_to_be32(srq->mr.ibmr.lkey);
  111. context->db_index = cpu_to_be32(srq->db_index);
  112. context->logstride_usrpage = cpu_to_be32((srq->wqe_shift - 4) << 29);
  113. if (pd->ibpd.uobject)
  114. context->logstride_usrpage |=
  115. cpu_to_be32(to_mucontext(pd->ibpd.uobject->context)->uar.index);
  116. else
  117. context->logstride_usrpage |= cpu_to_be32(dev->driver_uar.index);
  118. context->eq_pd = cpu_to_be32(MTHCA_EQ_ASYNC << 24 | pd->pd_num);
  119. }
  120. static void mthca_free_srq_buf(struct mthca_dev *dev, struct mthca_srq *srq)
  121. {
  122. mthca_buf_free(dev, srq->max << srq->wqe_shift, &srq->queue,
  123. srq->is_direct, &srq->mr);
  124. kfree(srq->wrid);
  125. }
  126. static int mthca_alloc_srq_buf(struct mthca_dev *dev, struct mthca_pd *pd,
  127. struct mthca_srq *srq)
  128. {
  129. struct mthca_data_seg *scatter;
  130. void *wqe;
  131. int err;
  132. int i;
  133. if (pd->ibpd.uobject)
  134. return 0;
  135. srq->wrid = kmalloc(srq->max * sizeof (u64), GFP_KERNEL);
  136. if (!srq->wrid)
  137. return -ENOMEM;
  138. err = mthca_buf_alloc(dev, srq->max << srq->wqe_shift,
  139. MTHCA_MAX_DIRECT_SRQ_SIZE,
  140. &srq->queue, &srq->is_direct, pd, 1, &srq->mr);
  141. if (err) {
  142. kfree(srq->wrid);
  143. return err;
  144. }
  145. /*
  146. * Now initialize the SRQ buffer so that all of the WQEs are
  147. * linked into the list of free WQEs. In addition, set the
  148. * scatter list L_Keys to the sentry value of 0x100.
  149. */
  150. for (i = 0; i < srq->max; ++i) {
  151. wqe = get_wqe(srq, i);
  152. *wqe_to_link(wqe) = i < srq->max - 1 ? i + 1 : -1;
  153. for (scatter = wqe + sizeof (struct mthca_next_seg);
  154. (void *) scatter < wqe + (1 << srq->wqe_shift);
  155. ++scatter)
  156. scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
  157. }
  158. srq->last = get_wqe(srq, srq->max - 1);
  159. return 0;
  160. }
  161. int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd,
  162. struct ib_srq_attr *attr, struct mthca_srq *srq)
  163. {
  164. struct mthca_mailbox *mailbox;
  165. u8 status;
  166. int ds;
  167. int err;
  168. /* Sanity check SRQ size before proceeding */
  169. if (attr->max_wr > dev->limits.max_srq_wqes ||
  170. attr->max_sge > dev->limits.max_srq_sge)
  171. return -EINVAL;
  172. srq->max = attr->max_wr;
  173. srq->max_gs = attr->max_sge;
  174. srq->counter = 0;
  175. if (mthca_is_memfree(dev))
  176. srq->max = roundup_pow_of_two(srq->max + 1);
  177. else
  178. srq->max = srq->max + 1;
  179. ds = max(64UL,
  180. roundup_pow_of_two(sizeof (struct mthca_next_seg) +
  181. srq->max_gs * sizeof (struct mthca_data_seg)));
  182. if (!mthca_is_memfree(dev) && (ds > dev->limits.max_desc_sz))
  183. return -EINVAL;
  184. srq->wqe_shift = long_log2(ds);
  185. srq->srqn = mthca_alloc(&dev->srq_table.alloc);
  186. if (srq->srqn == -1)
  187. return -ENOMEM;
  188. if (mthca_is_memfree(dev)) {
  189. err = mthca_table_get(dev, dev->srq_table.table, srq->srqn);
  190. if (err)
  191. goto err_out;
  192. if (!pd->ibpd.uobject) {
  193. srq->db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SRQ,
  194. srq->srqn, &srq->db);
  195. if (srq->db_index < 0) {
  196. err = -ENOMEM;
  197. goto err_out_icm;
  198. }
  199. }
  200. }
  201. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  202. if (IS_ERR(mailbox)) {
  203. err = PTR_ERR(mailbox);
  204. goto err_out_db;
  205. }
  206. err = mthca_alloc_srq_buf(dev, pd, srq);
  207. if (err)
  208. goto err_out_mailbox;
  209. spin_lock_init(&srq->lock);
  210. srq->refcount = 1;
  211. init_waitqueue_head(&srq->wait);
  212. mutex_init(&srq->mutex);
  213. if (mthca_is_memfree(dev))
  214. mthca_arbel_init_srq_context(dev, pd, srq, mailbox->buf);
  215. else
  216. mthca_tavor_init_srq_context(dev, pd, srq, mailbox->buf);
  217. err = mthca_SW2HW_SRQ(dev, mailbox, srq->srqn, &status);
  218. if (err) {
  219. mthca_warn(dev, "SW2HW_SRQ failed (%d)\n", err);
  220. goto err_out_free_buf;
  221. }
  222. if (status) {
  223. mthca_warn(dev, "SW2HW_SRQ returned status 0x%02x\n",
  224. status);
  225. err = -EINVAL;
  226. goto err_out_free_buf;
  227. }
  228. spin_lock_irq(&dev->srq_table.lock);
  229. if (mthca_array_set(&dev->srq_table.srq,
  230. srq->srqn & (dev->limits.num_srqs - 1),
  231. srq)) {
  232. spin_unlock_irq(&dev->srq_table.lock);
  233. goto err_out_free_srq;
  234. }
  235. spin_unlock_irq(&dev->srq_table.lock);
  236. mthca_free_mailbox(dev, mailbox);
  237. srq->first_free = 0;
  238. srq->last_free = srq->max - 1;
  239. attr->max_wr = srq->max - 1;
  240. attr->max_sge = srq->max_gs;
  241. return 0;
  242. err_out_free_srq:
  243. err = mthca_HW2SW_SRQ(dev, mailbox, srq->srqn, &status);
  244. if (err)
  245. mthca_warn(dev, "HW2SW_SRQ failed (%d)\n", err);
  246. else if (status)
  247. mthca_warn(dev, "HW2SW_SRQ returned status 0x%02x\n", status);
  248. err_out_free_buf:
  249. if (!pd->ibpd.uobject)
  250. mthca_free_srq_buf(dev, srq);
  251. err_out_mailbox:
  252. mthca_free_mailbox(dev, mailbox);
  253. err_out_db:
  254. if (!pd->ibpd.uobject && mthca_is_memfree(dev))
  255. mthca_free_db(dev, MTHCA_DB_TYPE_SRQ, srq->db_index);
  256. err_out_icm:
  257. mthca_table_put(dev, dev->srq_table.table, srq->srqn);
  258. err_out:
  259. mthca_free(&dev->srq_table.alloc, srq->srqn);
  260. return err;
  261. }
  262. static inline int get_srq_refcount(struct mthca_dev *dev, struct mthca_srq *srq)
  263. {
  264. int c;
  265. spin_lock_irq(&dev->srq_table.lock);
  266. c = srq->refcount;
  267. spin_unlock_irq(&dev->srq_table.lock);
  268. return c;
  269. }
  270. void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq)
  271. {
  272. struct mthca_mailbox *mailbox;
  273. int err;
  274. u8 status;
  275. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  276. if (IS_ERR(mailbox)) {
  277. mthca_warn(dev, "No memory for mailbox to free SRQ.\n");
  278. return;
  279. }
  280. err = mthca_HW2SW_SRQ(dev, mailbox, srq->srqn, &status);
  281. if (err)
  282. mthca_warn(dev, "HW2SW_SRQ failed (%d)\n", err);
  283. else if (status)
  284. mthca_warn(dev, "HW2SW_SRQ returned status 0x%02x\n", status);
  285. spin_lock_irq(&dev->srq_table.lock);
  286. mthca_array_clear(&dev->srq_table.srq,
  287. srq->srqn & (dev->limits.num_srqs - 1));
  288. --srq->refcount;
  289. spin_unlock_irq(&dev->srq_table.lock);
  290. wait_event(srq->wait, !get_srq_refcount(dev, srq));
  291. if (!srq->ibsrq.uobject) {
  292. mthca_free_srq_buf(dev, srq);
  293. if (mthca_is_memfree(dev))
  294. mthca_free_db(dev, MTHCA_DB_TYPE_SRQ, srq->db_index);
  295. }
  296. mthca_table_put(dev, dev->srq_table.table, srq->srqn);
  297. mthca_free(&dev->srq_table.alloc, srq->srqn);
  298. mthca_free_mailbox(dev, mailbox);
  299. }
  300. int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
  301. enum ib_srq_attr_mask attr_mask, struct ib_udata *udata)
  302. {
  303. struct mthca_dev *dev = to_mdev(ibsrq->device);
  304. struct mthca_srq *srq = to_msrq(ibsrq);
  305. int ret;
  306. u8 status;
  307. /* We don't support resizing SRQs (yet?) */
  308. if (attr_mask & IB_SRQ_MAX_WR)
  309. return -EINVAL;
  310. if (attr_mask & IB_SRQ_LIMIT) {
  311. u32 max_wr = mthca_is_memfree(dev) ? srq->max - 1 : srq->max;
  312. if (attr->srq_limit > max_wr)
  313. return -EINVAL;
  314. mutex_lock(&srq->mutex);
  315. ret = mthca_ARM_SRQ(dev, srq->srqn, attr->srq_limit, &status);
  316. mutex_unlock(&srq->mutex);
  317. if (ret)
  318. return ret;
  319. if (status)
  320. return -EINVAL;
  321. }
  322. return 0;
  323. }
  324. int mthca_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr)
  325. {
  326. struct mthca_dev *dev = to_mdev(ibsrq->device);
  327. struct mthca_srq *srq = to_msrq(ibsrq);
  328. struct mthca_mailbox *mailbox;
  329. struct mthca_arbel_srq_context *arbel_ctx;
  330. struct mthca_tavor_srq_context *tavor_ctx;
  331. u8 status;
  332. int err;
  333. mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
  334. if (IS_ERR(mailbox))
  335. return PTR_ERR(mailbox);
  336. err = mthca_QUERY_SRQ(dev, srq->srqn, mailbox, &status);
  337. if (err)
  338. goto out;
  339. if (mthca_is_memfree(dev)) {
  340. arbel_ctx = mailbox->buf;
  341. srq_attr->srq_limit = be16_to_cpu(arbel_ctx->limit_watermark);
  342. } else {
  343. tavor_ctx = mailbox->buf;
  344. srq_attr->srq_limit = be16_to_cpu(tavor_ctx->limit_watermark);
  345. }
  346. srq_attr->max_wr = srq->max - 1;
  347. srq_attr->max_sge = srq->max_gs;
  348. out:
  349. mthca_free_mailbox(dev, mailbox);
  350. return err;
  351. }
  352. void mthca_srq_event(struct mthca_dev *dev, u32 srqn,
  353. enum ib_event_type event_type)
  354. {
  355. struct mthca_srq *srq;
  356. struct ib_event event;
  357. spin_lock(&dev->srq_table.lock);
  358. srq = mthca_array_get(&dev->srq_table.srq, srqn & (dev->limits.num_srqs - 1));
  359. if (srq)
  360. ++srq->refcount;
  361. spin_unlock(&dev->srq_table.lock);
  362. if (!srq) {
  363. mthca_warn(dev, "Async event for bogus SRQ %08x\n", srqn);
  364. return;
  365. }
  366. if (!srq->ibsrq.event_handler)
  367. goto out;
  368. event.device = &dev->ib_dev;
  369. event.event = event_type;
  370. event.element.srq = &srq->ibsrq;
  371. srq->ibsrq.event_handler(&event, srq->ibsrq.srq_context);
  372. out:
  373. spin_lock(&dev->srq_table.lock);
  374. if (!--srq->refcount)
  375. wake_up(&srq->wait);
  376. spin_unlock(&dev->srq_table.lock);
  377. }
  378. /*
  379. * This function must be called with IRQs disabled.
  380. */
  381. void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr)
  382. {
  383. int ind;
  384. ind = wqe_addr >> srq->wqe_shift;
  385. spin_lock(&srq->lock);
  386. if (likely(srq->first_free >= 0))
  387. *wqe_to_link(get_wqe(srq, srq->last_free)) = ind;
  388. else
  389. srq->first_free = ind;
  390. *wqe_to_link(get_wqe(srq, ind)) = -1;
  391. srq->last_free = ind;
  392. spin_unlock(&srq->lock);
  393. }
  394. int mthca_tavor_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
  395. struct ib_recv_wr **bad_wr)
  396. {
  397. struct mthca_dev *dev = to_mdev(ibsrq->device);
  398. struct mthca_srq *srq = to_msrq(ibsrq);
  399. __be32 doorbell[2];
  400. unsigned long flags;
  401. int err = 0;
  402. int first_ind;
  403. int ind;
  404. int next_ind;
  405. int nreq;
  406. int i;
  407. void *wqe;
  408. void *prev_wqe;
  409. spin_lock_irqsave(&srq->lock, flags);
  410. first_ind = srq->first_free;
  411. for (nreq = 0; wr; wr = wr->next) {
  412. ind = srq->first_free;
  413. if (ind < 0) {
  414. mthca_err(dev, "SRQ %06x full\n", srq->srqn);
  415. err = -ENOMEM;
  416. *bad_wr = wr;
  417. break;
  418. }
  419. wqe = get_wqe(srq, ind);
  420. next_ind = *wqe_to_link(wqe);
  421. if (next_ind < 0) {
  422. mthca_err(dev, "SRQ %06x full\n", srq->srqn);
  423. err = -ENOMEM;
  424. *bad_wr = wr;
  425. break;
  426. }
  427. prev_wqe = srq->last;
  428. srq->last = wqe;
  429. ((struct mthca_next_seg *) wqe)->nda_op = 0;
  430. ((struct mthca_next_seg *) wqe)->ee_nds = 0;
  431. /* flags field will always remain 0 */
  432. wqe += sizeof (struct mthca_next_seg);
  433. if (unlikely(wr->num_sge > srq->max_gs)) {
  434. err = -EINVAL;
  435. *bad_wr = wr;
  436. srq->last = prev_wqe;
  437. break;
  438. }
  439. for (i = 0; i < wr->num_sge; ++i) {
  440. ((struct mthca_data_seg *) wqe)->byte_count =
  441. cpu_to_be32(wr->sg_list[i].length);
  442. ((struct mthca_data_seg *) wqe)->lkey =
  443. cpu_to_be32(wr->sg_list[i].lkey);
  444. ((struct mthca_data_seg *) wqe)->addr =
  445. cpu_to_be64(wr->sg_list[i].addr);
  446. wqe += sizeof (struct mthca_data_seg);
  447. }
  448. if (i < srq->max_gs) {
  449. ((struct mthca_data_seg *) wqe)->byte_count = 0;
  450. ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
  451. ((struct mthca_data_seg *) wqe)->addr = 0;
  452. }
  453. ((struct mthca_next_seg *) prev_wqe)->nda_op =
  454. cpu_to_be32((ind << srq->wqe_shift) | 1);
  455. wmb();
  456. ((struct mthca_next_seg *) prev_wqe)->ee_nds =
  457. cpu_to_be32(MTHCA_NEXT_DBD);
  458. srq->wrid[ind] = wr->wr_id;
  459. srq->first_free = next_ind;
  460. ++nreq;
  461. if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
  462. nreq = 0;
  463. doorbell[0] = cpu_to_be32(first_ind << srq->wqe_shift);
  464. doorbell[1] = cpu_to_be32(srq->srqn << 8);
  465. /*
  466. * Make sure that descriptors are written
  467. * before doorbell is rung.
  468. */
  469. wmb();
  470. mthca_write64(doorbell,
  471. dev->kar + MTHCA_RECEIVE_DOORBELL,
  472. MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
  473. first_ind = srq->first_free;
  474. }
  475. }
  476. if (likely(nreq)) {
  477. doorbell[0] = cpu_to_be32(first_ind << srq->wqe_shift);
  478. doorbell[1] = cpu_to_be32((srq->srqn << 8) | nreq);
  479. /*
  480. * Make sure that descriptors are written before
  481. * doorbell is rung.
  482. */
  483. wmb();
  484. mthca_write64(doorbell,
  485. dev->kar + MTHCA_RECEIVE_DOORBELL,
  486. MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
  487. }
  488. spin_unlock_irqrestore(&srq->lock, flags);
  489. return err;
  490. }
  491. int mthca_arbel_post_srq_recv(struct ib_srq *ibsrq, struct ib_recv_wr *wr,
  492. struct ib_recv_wr **bad_wr)
  493. {
  494. struct mthca_dev *dev = to_mdev(ibsrq->device);
  495. struct mthca_srq *srq = to_msrq(ibsrq);
  496. unsigned long flags;
  497. int err = 0;
  498. int ind;
  499. int next_ind;
  500. int nreq;
  501. int i;
  502. void *wqe;
  503. spin_lock_irqsave(&srq->lock, flags);
  504. for (nreq = 0; wr; ++nreq, wr = wr->next) {
  505. ind = srq->first_free;
  506. if (ind < 0) {
  507. mthca_err(dev, "SRQ %06x full\n", srq->srqn);
  508. err = -ENOMEM;
  509. *bad_wr = wr;
  510. break;
  511. }
  512. wqe = get_wqe(srq, ind);
  513. next_ind = *wqe_to_link(wqe);
  514. if (next_ind < 0) {
  515. mthca_err(dev, "SRQ %06x full\n", srq->srqn);
  516. err = -ENOMEM;
  517. *bad_wr = wr;
  518. break;
  519. }
  520. ((struct mthca_next_seg *) wqe)->nda_op =
  521. cpu_to_be32((next_ind << srq->wqe_shift) | 1);
  522. ((struct mthca_next_seg *) wqe)->ee_nds = 0;
  523. /* flags field will always remain 0 */
  524. wqe += sizeof (struct mthca_next_seg);
  525. if (unlikely(wr->num_sge > srq->max_gs)) {
  526. err = -EINVAL;
  527. *bad_wr = wr;
  528. break;
  529. }
  530. for (i = 0; i < wr->num_sge; ++i) {
  531. ((struct mthca_data_seg *) wqe)->byte_count =
  532. cpu_to_be32(wr->sg_list[i].length);
  533. ((struct mthca_data_seg *) wqe)->lkey =
  534. cpu_to_be32(wr->sg_list[i].lkey);
  535. ((struct mthca_data_seg *) wqe)->addr =
  536. cpu_to_be64(wr->sg_list[i].addr);
  537. wqe += sizeof (struct mthca_data_seg);
  538. }
  539. if (i < srq->max_gs) {
  540. ((struct mthca_data_seg *) wqe)->byte_count = 0;
  541. ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
  542. ((struct mthca_data_seg *) wqe)->addr = 0;
  543. }
  544. srq->wrid[ind] = wr->wr_id;
  545. srq->first_free = next_ind;
  546. }
  547. if (likely(nreq)) {
  548. srq->counter += nreq;
  549. /*
  550. * Make sure that descriptors are written before
  551. * we write doorbell record.
  552. */
  553. wmb();
  554. *srq->db = cpu_to_be32(srq->counter);
  555. }
  556. spin_unlock_irqrestore(&srq->lock, flags);
  557. return err;
  558. }
  559. int mthca_max_srq_sge(struct mthca_dev *dev)
  560. {
  561. if (mthca_is_memfree(dev))
  562. return dev->limits.max_sg;
  563. /*
  564. * SRQ allocations are based on powers of 2 for Tavor,
  565. * (although they only need to be multiples of 16 bytes).
  566. *
  567. * Therefore, we need to base the max number of sg entries on
  568. * the largest power of 2 descriptor size that is <= to the
  569. * actual max WQE descriptor size, rather than return the
  570. * max_sg value given by the firmware (which is based on WQE
  571. * sizes as multiples of 16, not powers of 2).
  572. *
  573. * If SRQ implementation is changed for Tavor to be based on
  574. * multiples of 16, the calculation below can be deleted and
  575. * the FW max_sg value returned.
  576. */
  577. return min_t(int, dev->limits.max_sg,
  578. ((1 << (fls(dev->limits.max_desc_sz) - 1)) -
  579. sizeof (struct mthca_next_seg)) /
  580. sizeof (struct mthca_data_seg));
  581. }
  582. int __devinit mthca_init_srq_table(struct mthca_dev *dev)
  583. {
  584. int err;
  585. if (!(dev->mthca_flags & MTHCA_FLAG_SRQ))
  586. return 0;
  587. spin_lock_init(&dev->srq_table.lock);
  588. err = mthca_alloc_init(&dev->srq_table.alloc,
  589. dev->limits.num_srqs,
  590. dev->limits.num_srqs - 1,
  591. dev->limits.reserved_srqs);
  592. if (err)
  593. return err;
  594. err = mthca_array_init(&dev->srq_table.srq,
  595. dev->limits.num_srqs);
  596. if (err)
  597. mthca_alloc_cleanup(&dev->srq_table.alloc);
  598. return err;
  599. }
  600. void mthca_cleanup_srq_table(struct mthca_dev *dev)
  601. {
  602. if (!(dev->mthca_flags & MTHCA_FLAG_SRQ))
  603. return;
  604. mthca_array_cleanup(&dev->srq_table.srq, dev->limits.num_srqs);
  605. mthca_alloc_cleanup(&dev->srq_table.alloc);
  606. }