device.c 20 KB

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  1. /*
  2. * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/debugfs.h>
  35. #include <rdma/ib_verbs.h>
  36. #include "iw_cxgb4.h"
  37. #define DRV_VERSION "0.1"
  38. MODULE_AUTHOR("Steve Wise");
  39. MODULE_DESCRIPTION("Chelsio T4 RDMA Driver");
  40. MODULE_LICENSE("Dual BSD/GPL");
  41. MODULE_VERSION(DRV_VERSION);
  42. struct uld_ctx {
  43. struct list_head entry;
  44. struct cxgb4_lld_info lldi;
  45. struct c4iw_dev *dev;
  46. };
  47. static LIST_HEAD(uld_ctx_list);
  48. static DEFINE_MUTEX(dev_mutex);
  49. static struct dentry *c4iw_debugfs_root;
  50. struct c4iw_debugfs_data {
  51. struct c4iw_dev *devp;
  52. char *buf;
  53. int bufsize;
  54. int pos;
  55. };
  56. static int count_idrs(int id, void *p, void *data)
  57. {
  58. int *countp = data;
  59. *countp = *countp + 1;
  60. return 0;
  61. }
  62. static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
  63. loff_t *ppos)
  64. {
  65. struct c4iw_debugfs_data *d = file->private_data;
  66. return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
  67. }
  68. static int dump_qp(int id, void *p, void *data)
  69. {
  70. struct c4iw_qp *qp = p;
  71. struct c4iw_debugfs_data *qpd = data;
  72. int space;
  73. int cc;
  74. if (id != qp->wq.sq.qid)
  75. return 0;
  76. space = qpd->bufsize - qpd->pos - 1;
  77. if (space == 0)
  78. return 1;
  79. if (qp->ep)
  80. cc = snprintf(qpd->buf + qpd->pos, space,
  81. "qp sq id %u rq id %u state %u onchip %u "
  82. "ep tid %u state %u %pI4:%u->%pI4:%u\n",
  83. qp->wq.sq.qid, qp->wq.rq.qid, (int)qp->attr.state,
  84. qp->wq.sq.flags & T4_SQ_ONCHIP,
  85. qp->ep->hwtid, (int)qp->ep->com.state,
  86. &qp->ep->com.local_addr.sin_addr.s_addr,
  87. ntohs(qp->ep->com.local_addr.sin_port),
  88. &qp->ep->com.remote_addr.sin_addr.s_addr,
  89. ntohs(qp->ep->com.remote_addr.sin_port));
  90. else
  91. cc = snprintf(qpd->buf + qpd->pos, space,
  92. "qp sq id %u rq id %u state %u onchip %u\n",
  93. qp->wq.sq.qid, qp->wq.rq.qid,
  94. (int)qp->attr.state,
  95. qp->wq.sq.flags & T4_SQ_ONCHIP);
  96. if (cc < space)
  97. qpd->pos += cc;
  98. return 0;
  99. }
  100. static int qp_release(struct inode *inode, struct file *file)
  101. {
  102. struct c4iw_debugfs_data *qpd = file->private_data;
  103. if (!qpd) {
  104. printk(KERN_INFO "%s null qpd?\n", __func__);
  105. return 0;
  106. }
  107. kfree(qpd->buf);
  108. kfree(qpd);
  109. return 0;
  110. }
  111. static int qp_open(struct inode *inode, struct file *file)
  112. {
  113. struct c4iw_debugfs_data *qpd;
  114. int ret = 0;
  115. int count = 1;
  116. qpd = kmalloc(sizeof *qpd, GFP_KERNEL);
  117. if (!qpd) {
  118. ret = -ENOMEM;
  119. goto out;
  120. }
  121. qpd->devp = inode->i_private;
  122. qpd->pos = 0;
  123. spin_lock_irq(&qpd->devp->lock);
  124. idr_for_each(&qpd->devp->qpidr, count_idrs, &count);
  125. spin_unlock_irq(&qpd->devp->lock);
  126. qpd->bufsize = count * 128;
  127. qpd->buf = kmalloc(qpd->bufsize, GFP_KERNEL);
  128. if (!qpd->buf) {
  129. ret = -ENOMEM;
  130. goto err1;
  131. }
  132. spin_lock_irq(&qpd->devp->lock);
  133. idr_for_each(&qpd->devp->qpidr, dump_qp, qpd);
  134. spin_unlock_irq(&qpd->devp->lock);
  135. qpd->buf[qpd->pos++] = 0;
  136. file->private_data = qpd;
  137. goto out;
  138. err1:
  139. kfree(qpd);
  140. out:
  141. return ret;
  142. }
  143. static const struct file_operations qp_debugfs_fops = {
  144. .owner = THIS_MODULE,
  145. .open = qp_open,
  146. .release = qp_release,
  147. .read = debugfs_read,
  148. .llseek = default_llseek,
  149. };
  150. static int dump_stag(int id, void *p, void *data)
  151. {
  152. struct c4iw_debugfs_data *stagd = data;
  153. int space;
  154. int cc;
  155. space = stagd->bufsize - stagd->pos - 1;
  156. if (space == 0)
  157. return 1;
  158. cc = snprintf(stagd->buf + stagd->pos, space, "0x%x\n", id<<8);
  159. if (cc < space)
  160. stagd->pos += cc;
  161. return 0;
  162. }
  163. static int stag_release(struct inode *inode, struct file *file)
  164. {
  165. struct c4iw_debugfs_data *stagd = file->private_data;
  166. if (!stagd) {
  167. printk(KERN_INFO "%s null stagd?\n", __func__);
  168. return 0;
  169. }
  170. kfree(stagd->buf);
  171. kfree(stagd);
  172. return 0;
  173. }
  174. static int stag_open(struct inode *inode, struct file *file)
  175. {
  176. struct c4iw_debugfs_data *stagd;
  177. int ret = 0;
  178. int count = 1;
  179. stagd = kmalloc(sizeof *stagd, GFP_KERNEL);
  180. if (!stagd) {
  181. ret = -ENOMEM;
  182. goto out;
  183. }
  184. stagd->devp = inode->i_private;
  185. stagd->pos = 0;
  186. spin_lock_irq(&stagd->devp->lock);
  187. idr_for_each(&stagd->devp->mmidr, count_idrs, &count);
  188. spin_unlock_irq(&stagd->devp->lock);
  189. stagd->bufsize = count * sizeof("0x12345678\n");
  190. stagd->buf = kmalloc(stagd->bufsize, GFP_KERNEL);
  191. if (!stagd->buf) {
  192. ret = -ENOMEM;
  193. goto err1;
  194. }
  195. spin_lock_irq(&stagd->devp->lock);
  196. idr_for_each(&stagd->devp->mmidr, dump_stag, stagd);
  197. spin_unlock_irq(&stagd->devp->lock);
  198. stagd->buf[stagd->pos++] = 0;
  199. file->private_data = stagd;
  200. goto out;
  201. err1:
  202. kfree(stagd);
  203. out:
  204. return ret;
  205. }
  206. static const struct file_operations stag_debugfs_fops = {
  207. .owner = THIS_MODULE,
  208. .open = stag_open,
  209. .release = stag_release,
  210. .read = debugfs_read,
  211. .llseek = default_llseek,
  212. };
  213. static int stats_show(struct seq_file *seq, void *v)
  214. {
  215. struct c4iw_dev *dev = seq->private;
  216. seq_printf(seq, " Object: %10s %10s %10s\n", "Total", "Current", "Max");
  217. seq_printf(seq, " PDID: %10llu %10llu %10llu\n",
  218. dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur,
  219. dev->rdev.stats.pd.max);
  220. seq_printf(seq, " QID: %10llu %10llu %10llu\n",
  221. dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur,
  222. dev->rdev.stats.qid.max);
  223. seq_printf(seq, " TPTMEM: %10llu %10llu %10llu\n",
  224. dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur,
  225. dev->rdev.stats.stag.max);
  226. seq_printf(seq, " PBLMEM: %10llu %10llu %10llu\n",
  227. dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur,
  228. dev->rdev.stats.pbl.max);
  229. seq_printf(seq, " RQTMEM: %10llu %10llu %10llu\n",
  230. dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur,
  231. dev->rdev.stats.rqt.max);
  232. seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu\n",
  233. dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur,
  234. dev->rdev.stats.ocqp.max);
  235. seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full);
  236. seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty);
  237. seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop);
  238. return 0;
  239. }
  240. static int stats_open(struct inode *inode, struct file *file)
  241. {
  242. return single_open(file, stats_show, inode->i_private);
  243. }
  244. static ssize_t stats_clear(struct file *file, const char __user *buf,
  245. size_t count, loff_t *pos)
  246. {
  247. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  248. mutex_lock(&dev->rdev.stats.lock);
  249. dev->rdev.stats.pd.max = 0;
  250. dev->rdev.stats.qid.max = 0;
  251. dev->rdev.stats.stag.max = 0;
  252. dev->rdev.stats.pbl.max = 0;
  253. dev->rdev.stats.rqt.max = 0;
  254. dev->rdev.stats.ocqp.max = 0;
  255. dev->rdev.stats.db_full = 0;
  256. dev->rdev.stats.db_empty = 0;
  257. dev->rdev.stats.db_drop = 0;
  258. mutex_unlock(&dev->rdev.stats.lock);
  259. return count;
  260. }
  261. static const struct file_operations stats_debugfs_fops = {
  262. .owner = THIS_MODULE,
  263. .open = stats_open,
  264. .release = single_release,
  265. .read = seq_read,
  266. .llseek = seq_lseek,
  267. .write = stats_clear,
  268. };
  269. static int setup_debugfs(struct c4iw_dev *devp)
  270. {
  271. struct dentry *de;
  272. if (!devp->debugfs_root)
  273. return -1;
  274. de = debugfs_create_file("qps", S_IWUSR, devp->debugfs_root,
  275. (void *)devp, &qp_debugfs_fops);
  276. if (de && de->d_inode)
  277. de->d_inode->i_size = 4096;
  278. de = debugfs_create_file("stags", S_IWUSR, devp->debugfs_root,
  279. (void *)devp, &stag_debugfs_fops);
  280. if (de && de->d_inode)
  281. de->d_inode->i_size = 4096;
  282. de = debugfs_create_file("stats", S_IWUSR, devp->debugfs_root,
  283. (void *)devp, &stats_debugfs_fops);
  284. if (de && de->d_inode)
  285. de->d_inode->i_size = 4096;
  286. return 0;
  287. }
  288. void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
  289. struct c4iw_dev_ucontext *uctx)
  290. {
  291. struct list_head *pos, *nxt;
  292. struct c4iw_qid_list *entry;
  293. mutex_lock(&uctx->lock);
  294. list_for_each_safe(pos, nxt, &uctx->qpids) {
  295. entry = list_entry(pos, struct c4iw_qid_list, entry);
  296. list_del_init(&entry->entry);
  297. if (!(entry->qid & rdev->qpmask)) {
  298. c4iw_put_resource(&rdev->resource.qid_fifo, entry->qid,
  299. &rdev->resource.qid_fifo_lock);
  300. mutex_lock(&rdev->stats.lock);
  301. rdev->stats.qid.cur -= rdev->qpmask + 1;
  302. mutex_unlock(&rdev->stats.lock);
  303. }
  304. kfree(entry);
  305. }
  306. list_for_each_safe(pos, nxt, &uctx->qpids) {
  307. entry = list_entry(pos, struct c4iw_qid_list, entry);
  308. list_del_init(&entry->entry);
  309. kfree(entry);
  310. }
  311. mutex_unlock(&uctx->lock);
  312. }
  313. void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
  314. struct c4iw_dev_ucontext *uctx)
  315. {
  316. INIT_LIST_HEAD(&uctx->qpids);
  317. INIT_LIST_HEAD(&uctx->cqids);
  318. mutex_init(&uctx->lock);
  319. }
  320. /* Caller takes care of locking if needed */
  321. static int c4iw_rdev_open(struct c4iw_rdev *rdev)
  322. {
  323. int err;
  324. c4iw_init_dev_ucontext(rdev, &rdev->uctx);
  325. /*
  326. * qpshift is the number of bits to shift the qpid left in order
  327. * to get the correct address of the doorbell for that qp.
  328. */
  329. rdev->qpshift = PAGE_SHIFT - ilog2(rdev->lldi.udb_density);
  330. rdev->qpmask = rdev->lldi.udb_density - 1;
  331. rdev->cqshift = PAGE_SHIFT - ilog2(rdev->lldi.ucq_density);
  332. rdev->cqmask = rdev->lldi.ucq_density - 1;
  333. PDBG("%s dev %s stag start 0x%0x size 0x%0x num stags %d "
  334. "pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x "
  335. "qp qid start %u size %u cq qid start %u size %u\n",
  336. __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
  337. rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
  338. rdev->lldi.vr->pbl.start,
  339. rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
  340. rdev->lldi.vr->rq.size,
  341. rdev->lldi.vr->qp.start,
  342. rdev->lldi.vr->qp.size,
  343. rdev->lldi.vr->cq.start,
  344. rdev->lldi.vr->cq.size);
  345. PDBG("udb len 0x%x udb base %p db_reg %p gts_reg %p qpshift %lu "
  346. "qpmask 0x%x cqshift %lu cqmask 0x%x\n",
  347. (unsigned)pci_resource_len(rdev->lldi.pdev, 2),
  348. (void *)pci_resource_start(rdev->lldi.pdev, 2),
  349. rdev->lldi.db_reg,
  350. rdev->lldi.gts_reg,
  351. rdev->qpshift, rdev->qpmask,
  352. rdev->cqshift, rdev->cqmask);
  353. if (c4iw_num_stags(rdev) == 0) {
  354. err = -EINVAL;
  355. goto err1;
  356. }
  357. rdev->stats.pd.total = T4_MAX_NUM_PD;
  358. rdev->stats.stag.total = rdev->lldi.vr->stag.size;
  359. rdev->stats.pbl.total = rdev->lldi.vr->pbl.size;
  360. rdev->stats.rqt.total = rdev->lldi.vr->rq.size;
  361. rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size;
  362. rdev->stats.qid.total = rdev->lldi.vr->qp.size;
  363. err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD);
  364. if (err) {
  365. printk(KERN_ERR MOD "error %d initializing resources\n", err);
  366. goto err1;
  367. }
  368. err = c4iw_pblpool_create(rdev);
  369. if (err) {
  370. printk(KERN_ERR MOD "error %d initializing pbl pool\n", err);
  371. goto err2;
  372. }
  373. err = c4iw_rqtpool_create(rdev);
  374. if (err) {
  375. printk(KERN_ERR MOD "error %d initializing rqt pool\n", err);
  376. goto err3;
  377. }
  378. err = c4iw_ocqp_pool_create(rdev);
  379. if (err) {
  380. printk(KERN_ERR MOD "error %d initializing ocqp pool\n", err);
  381. goto err4;
  382. }
  383. return 0;
  384. err4:
  385. c4iw_rqtpool_destroy(rdev);
  386. err3:
  387. c4iw_pblpool_destroy(rdev);
  388. err2:
  389. c4iw_destroy_resource(&rdev->resource);
  390. err1:
  391. return err;
  392. }
  393. static void c4iw_rdev_close(struct c4iw_rdev *rdev)
  394. {
  395. c4iw_pblpool_destroy(rdev);
  396. c4iw_rqtpool_destroy(rdev);
  397. c4iw_destroy_resource(&rdev->resource);
  398. }
  399. static void c4iw_dealloc(struct uld_ctx *ctx)
  400. {
  401. c4iw_rdev_close(&ctx->dev->rdev);
  402. idr_destroy(&ctx->dev->cqidr);
  403. idr_destroy(&ctx->dev->qpidr);
  404. idr_destroy(&ctx->dev->mmidr);
  405. iounmap(ctx->dev->rdev.oc_mw_kva);
  406. ib_dealloc_device(&ctx->dev->ibdev);
  407. ctx->dev = NULL;
  408. }
  409. static void c4iw_remove(struct uld_ctx *ctx)
  410. {
  411. PDBG("%s c4iw_dev %p\n", __func__, ctx->dev);
  412. c4iw_unregister_device(ctx->dev);
  413. c4iw_dealloc(ctx);
  414. }
  415. static int rdma_supported(const struct cxgb4_lld_info *infop)
  416. {
  417. return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 &&
  418. infop->vr->rq.size > 0 && infop->vr->qp.size > 0 &&
  419. infop->vr->cq.size > 0 && infop->vr->ocq.size > 0;
  420. }
  421. static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
  422. {
  423. struct c4iw_dev *devp;
  424. int ret;
  425. if (!rdma_supported(infop)) {
  426. printk(KERN_INFO MOD "%s: RDMA not supported on this device.\n",
  427. pci_name(infop->pdev));
  428. return ERR_PTR(-ENOSYS);
  429. }
  430. devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp));
  431. if (!devp) {
  432. printk(KERN_ERR MOD "Cannot allocate ib device\n");
  433. return ERR_PTR(-ENOMEM);
  434. }
  435. devp->rdev.lldi = *infop;
  436. devp->rdev.oc_mw_pa = pci_resource_start(devp->rdev.lldi.pdev, 2) +
  437. (pci_resource_len(devp->rdev.lldi.pdev, 2) -
  438. roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size));
  439. devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
  440. devp->rdev.lldi.vr->ocq.size);
  441. PDBG(KERN_INFO MOD "ocq memory: "
  442. "hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
  443. devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
  444. devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
  445. ret = c4iw_rdev_open(&devp->rdev);
  446. if (ret) {
  447. printk(KERN_ERR MOD "Unable to open CXIO rdev err %d\n", ret);
  448. ib_dealloc_device(&devp->ibdev);
  449. return ERR_PTR(ret);
  450. }
  451. idr_init(&devp->cqidr);
  452. idr_init(&devp->qpidr);
  453. idr_init(&devp->mmidr);
  454. spin_lock_init(&devp->lock);
  455. mutex_init(&devp->rdev.stats.lock);
  456. mutex_init(&devp->db_mutex);
  457. if (c4iw_debugfs_root) {
  458. devp->debugfs_root = debugfs_create_dir(
  459. pci_name(devp->rdev.lldi.pdev),
  460. c4iw_debugfs_root);
  461. setup_debugfs(devp);
  462. }
  463. return devp;
  464. }
  465. static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
  466. {
  467. struct uld_ctx *ctx;
  468. static int vers_printed;
  469. int i;
  470. if (!vers_printed++)
  471. printk(KERN_INFO MOD "Chelsio T4 RDMA Driver - version %s\n",
  472. DRV_VERSION);
  473. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  474. if (!ctx) {
  475. ctx = ERR_PTR(-ENOMEM);
  476. goto out;
  477. }
  478. ctx->lldi = *infop;
  479. PDBG("%s found device %s nchan %u nrxq %u ntxq %u nports %u\n",
  480. __func__, pci_name(ctx->lldi.pdev),
  481. ctx->lldi.nchan, ctx->lldi.nrxq,
  482. ctx->lldi.ntxq, ctx->lldi.nports);
  483. mutex_lock(&dev_mutex);
  484. list_add_tail(&ctx->entry, &uld_ctx_list);
  485. mutex_unlock(&dev_mutex);
  486. for (i = 0; i < ctx->lldi.nrxq; i++)
  487. PDBG("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
  488. out:
  489. return ctx;
  490. }
  491. static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
  492. const struct pkt_gl *gl)
  493. {
  494. struct uld_ctx *ctx = handle;
  495. struct c4iw_dev *dev = ctx->dev;
  496. struct sk_buff *skb;
  497. const struct cpl_act_establish *rpl;
  498. unsigned int opcode;
  499. if (gl == NULL) {
  500. /* omit RSS and rsp_ctrl at end of descriptor */
  501. unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
  502. skb = alloc_skb(256, GFP_ATOMIC);
  503. if (!skb)
  504. goto nomem;
  505. __skb_put(skb, len);
  506. skb_copy_to_linear_data(skb, &rsp[1], len);
  507. } else if (gl == CXGB4_MSG_AN) {
  508. const struct rsp_ctrl *rc = (void *)rsp;
  509. u32 qid = be32_to_cpu(rc->pldbuflen_qid);
  510. c4iw_ev_handler(dev, qid);
  511. return 0;
  512. } else {
  513. skb = cxgb4_pktgl_to_skb(gl, 128, 128);
  514. if (unlikely(!skb))
  515. goto nomem;
  516. }
  517. rpl = cplhdr(skb);
  518. opcode = rpl->ot.opcode;
  519. if (c4iw_handlers[opcode])
  520. c4iw_handlers[opcode](dev, skb);
  521. else
  522. printk(KERN_INFO "%s no handler opcode 0x%x...\n", __func__,
  523. opcode);
  524. return 0;
  525. nomem:
  526. return -1;
  527. }
  528. static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
  529. {
  530. struct uld_ctx *ctx = handle;
  531. PDBG("%s new_state %u\n", __func__, new_state);
  532. switch (new_state) {
  533. case CXGB4_STATE_UP:
  534. printk(KERN_INFO MOD "%s: Up\n", pci_name(ctx->lldi.pdev));
  535. if (!ctx->dev) {
  536. int ret;
  537. ctx->dev = c4iw_alloc(&ctx->lldi);
  538. if (IS_ERR(ctx->dev)) {
  539. printk(KERN_ERR MOD
  540. "%s: initialization failed: %ld\n",
  541. pci_name(ctx->lldi.pdev),
  542. PTR_ERR(ctx->dev));
  543. ctx->dev = NULL;
  544. break;
  545. }
  546. ret = c4iw_register_device(ctx->dev);
  547. if (ret) {
  548. printk(KERN_ERR MOD
  549. "%s: RDMA registration failed: %d\n",
  550. pci_name(ctx->lldi.pdev), ret);
  551. c4iw_dealloc(ctx);
  552. }
  553. }
  554. break;
  555. case CXGB4_STATE_DOWN:
  556. printk(KERN_INFO MOD "%s: Down\n",
  557. pci_name(ctx->lldi.pdev));
  558. if (ctx->dev)
  559. c4iw_remove(ctx);
  560. break;
  561. case CXGB4_STATE_START_RECOVERY:
  562. printk(KERN_INFO MOD "%s: Fatal Error\n",
  563. pci_name(ctx->lldi.pdev));
  564. if (ctx->dev) {
  565. struct ib_event event;
  566. ctx->dev->rdev.flags |= T4_FATAL_ERROR;
  567. memset(&event, 0, sizeof event);
  568. event.event = IB_EVENT_DEVICE_FATAL;
  569. event.device = &ctx->dev->ibdev;
  570. ib_dispatch_event(&event);
  571. c4iw_remove(ctx);
  572. }
  573. break;
  574. case CXGB4_STATE_DETACH:
  575. printk(KERN_INFO MOD "%s: Detach\n",
  576. pci_name(ctx->lldi.pdev));
  577. if (ctx->dev)
  578. c4iw_remove(ctx);
  579. break;
  580. }
  581. return 0;
  582. }
  583. static int disable_qp_db(int id, void *p, void *data)
  584. {
  585. struct c4iw_qp *qp = p;
  586. t4_disable_wq_db(&qp->wq);
  587. return 0;
  588. }
  589. static void stop_queues(struct uld_ctx *ctx)
  590. {
  591. spin_lock_irq(&ctx->dev->lock);
  592. ctx->dev->db_state = FLOW_CONTROL;
  593. idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL);
  594. spin_unlock_irq(&ctx->dev->lock);
  595. }
  596. static int enable_qp_db(int id, void *p, void *data)
  597. {
  598. struct c4iw_qp *qp = p;
  599. t4_enable_wq_db(&qp->wq);
  600. return 0;
  601. }
  602. static void resume_queues(struct uld_ctx *ctx)
  603. {
  604. spin_lock_irq(&ctx->dev->lock);
  605. ctx->dev->db_state = NORMAL;
  606. idr_for_each(&ctx->dev->qpidr, enable_qp_db, NULL);
  607. spin_unlock_irq(&ctx->dev->lock);
  608. }
  609. static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...)
  610. {
  611. struct uld_ctx *ctx = handle;
  612. switch (control) {
  613. case CXGB4_CONTROL_DB_FULL:
  614. stop_queues(ctx);
  615. mutex_lock(&ctx->dev->rdev.stats.lock);
  616. ctx->dev->rdev.stats.db_full++;
  617. mutex_unlock(&ctx->dev->rdev.stats.lock);
  618. break;
  619. case CXGB4_CONTROL_DB_EMPTY:
  620. resume_queues(ctx);
  621. mutex_lock(&ctx->dev->rdev.stats.lock);
  622. ctx->dev->rdev.stats.db_empty++;
  623. mutex_unlock(&ctx->dev->rdev.stats.lock);
  624. break;
  625. case CXGB4_CONTROL_DB_DROP:
  626. printk(KERN_WARNING MOD "%s: Fatal DB DROP\n",
  627. pci_name(ctx->lldi.pdev));
  628. mutex_lock(&ctx->dev->rdev.stats.lock);
  629. ctx->dev->rdev.stats.db_drop++;
  630. mutex_unlock(&ctx->dev->rdev.stats.lock);
  631. break;
  632. default:
  633. printk(KERN_WARNING MOD "%s: unknown control cmd %u\n",
  634. pci_name(ctx->lldi.pdev), control);
  635. break;
  636. }
  637. return 0;
  638. }
  639. static struct cxgb4_uld_info c4iw_uld_info = {
  640. .name = DRV_NAME,
  641. .add = c4iw_uld_add,
  642. .rx_handler = c4iw_uld_rx_handler,
  643. .state_change = c4iw_uld_state_change,
  644. .control = c4iw_uld_control,
  645. };
  646. static int __init c4iw_init_module(void)
  647. {
  648. int err;
  649. err = c4iw_cm_init();
  650. if (err)
  651. return err;
  652. c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
  653. if (!c4iw_debugfs_root)
  654. printk(KERN_WARNING MOD
  655. "could not create debugfs entry, continuing\n");
  656. cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
  657. return 0;
  658. }
  659. static void __exit c4iw_exit_module(void)
  660. {
  661. struct uld_ctx *ctx, *tmp;
  662. mutex_lock(&dev_mutex);
  663. list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
  664. if (ctx->dev)
  665. c4iw_remove(ctx);
  666. kfree(ctx);
  667. }
  668. mutex_unlock(&dev_mutex);
  669. cxgb4_unregister_uld(CXGB4_ULD_RDMA);
  670. c4iw_cm_term();
  671. debugfs_remove_recursive(c4iw_debugfs_root);
  672. }
  673. module_init(c4iw_init_module);
  674. module_exit(c4iw_exit_module);