i6300esb.c 14 KB

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  1. /*
  2. * i6300esb: Watchdog timer driver for Intel 6300ESB chipset
  3. *
  4. * (c) Copyright 2004 Google Inc.
  5. * (c) Copyright 2005 David Härdeman <david@2gen.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. *
  12. * based on i810-tco.c which is in turn based on softdog.c
  13. *
  14. * The timer is implemented in the following I/O controller hubs:
  15. * (See the intel documentation on http://developer.intel.com.)
  16. * 6300ESB chip : document number 300641-004
  17. *
  18. * 2004YYZZ Ross Biro
  19. * Initial version 0.01
  20. * 2004YYZZ Ross Biro
  21. * Version 0.02
  22. * 20050210 David Härdeman <david@2gen.com>
  23. * Ported driver to kernel 2.6
  24. */
  25. /*
  26. * Includes, defines, variables, module parameters, ...
  27. */
  28. #include <linux/module.h>
  29. #include <linux/types.h>
  30. #include <linux/kernel.h>
  31. #include <linux/fs.h>
  32. #include <linux/mm.h>
  33. #include <linux/miscdevice.h>
  34. #include <linux/watchdog.h>
  35. #include <linux/platform_device.h>
  36. #include <linux/init.h>
  37. #include <linux/pci.h>
  38. #include <linux/ioport.h>
  39. #include <linux/uaccess.h>
  40. #include <linux/io.h>
  41. /* Module and version information */
  42. #define ESB_VERSION "0.04"
  43. #define ESB_MODULE_NAME "i6300ESB timer"
  44. #define ESB_DRIVER_NAME ESB_MODULE_NAME ", v" ESB_VERSION
  45. #define PFX ESB_MODULE_NAME ": "
  46. /* PCI configuration registers */
  47. #define ESB_CONFIG_REG 0x60 /* Config register */
  48. #define ESB_LOCK_REG 0x68 /* WDT lock register */
  49. /* Memory mapped registers */
  50. #define ESB_TIMER1_REG (BASEADDR + 0x00)/* Timer1 value after each reset */
  51. #define ESB_TIMER2_REG (BASEADDR + 0x04)/* Timer2 value after each reset */
  52. #define ESB_GINTSR_REG (BASEADDR + 0x08)/* General Interrupt Status Register */
  53. #define ESB_RELOAD_REG (BASEADDR + 0x0c)/* Reload register */
  54. /* Lock register bits */
  55. #define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
  56. #define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
  57. #define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
  58. /* Config register bits */
  59. #define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
  60. #define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
  61. #define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */
  62. /* Reload register bits */
  63. #define ESB_WDT_TIMEOUT (0x01 << 9) /* Watchdog timed out */
  64. #define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
  65. /* Magic constants */
  66. #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
  67. #define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
  68. /* internal variables */
  69. static void __iomem *BASEADDR;
  70. static DEFINE_SPINLOCK(esb_lock); /* Guards the hardware */
  71. static unsigned long timer_alive;
  72. static struct pci_dev *esb_pci;
  73. static unsigned short triggered; /* The status of the watchdog upon boot */
  74. static char esb_expect_close;
  75. static struct platform_device *esb_platform_device;
  76. /* module parameters */
  77. /* 30 sec default heartbeat (1 < heartbeat < 2*1023) */
  78. #define WATCHDOG_HEARTBEAT 30
  79. static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
  80. module_param(heartbeat, int, 0);
  81. MODULE_PARM_DESC(heartbeat,
  82. "Watchdog heartbeat in seconds. (1<heartbeat<2046, default="
  83. __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
  84. static int nowayout = WATCHDOG_NOWAYOUT;
  85. module_param(nowayout, int, 0);
  86. MODULE_PARM_DESC(nowayout,
  87. "Watchdog cannot be stopped once started (default="
  88. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  89. /*
  90. * Some i6300ESB specific functions
  91. */
  92. /*
  93. * Prepare for reloading the timer by unlocking the proper registers.
  94. * This is performed by first writing 0x80 followed by 0x86 to the
  95. * reload register. After this the appropriate registers can be written
  96. * to once before they need to be unlocked again.
  97. */
  98. static inline void esb_unlock_registers(void)
  99. {
  100. writeb(ESB_UNLOCK1, ESB_RELOAD_REG);
  101. writeb(ESB_UNLOCK2, ESB_RELOAD_REG);
  102. }
  103. static int esb_timer_start(void)
  104. {
  105. u8 val;
  106. spin_lock(&esb_lock);
  107. esb_unlock_registers();
  108. writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
  109. /* Enable or Enable + Lock? */
  110. val = ESB_WDT_ENABLE | (nowayout ? ESB_WDT_LOCK : 0x00);
  111. pci_write_config_byte(esb_pci, ESB_LOCK_REG, val);
  112. spin_unlock(&esb_lock);
  113. return 0;
  114. }
  115. static int esb_timer_stop(void)
  116. {
  117. u8 val;
  118. spin_lock(&esb_lock);
  119. /* First, reset timers as suggested by the docs */
  120. esb_unlock_registers();
  121. writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
  122. /* Then disable the WDT */
  123. pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x0);
  124. pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val);
  125. spin_unlock(&esb_lock);
  126. /* Returns 0 if the timer was disabled, non-zero otherwise */
  127. return val & ESB_WDT_ENABLE;
  128. }
  129. static void esb_timer_keepalive(void)
  130. {
  131. spin_lock(&esb_lock);
  132. esb_unlock_registers();
  133. writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
  134. /* FIXME: Do we need to flush anything here? */
  135. spin_unlock(&esb_lock);
  136. }
  137. static int esb_timer_set_heartbeat(int time)
  138. {
  139. u32 val;
  140. if (time < 0x1 || time > (2 * 0x03ff))
  141. return -EINVAL;
  142. spin_lock(&esb_lock);
  143. /* We shift by 9, so if we are passed a value of 1 sec,
  144. * val will be 1 << 9 = 512, then write that to two
  145. * timers => 2 * 512 = 1024 (which is decremented at 1KHz)
  146. */
  147. val = time << 9;
  148. /* Write timer 1 */
  149. esb_unlock_registers();
  150. writel(val, ESB_TIMER1_REG);
  151. /* Write timer 2 */
  152. esb_unlock_registers();
  153. writel(val, ESB_TIMER2_REG);
  154. /* Reload */
  155. esb_unlock_registers();
  156. writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
  157. /* FIXME: Do we need to flush everything out? */
  158. /* Done */
  159. heartbeat = time;
  160. spin_unlock(&esb_lock);
  161. return 0;
  162. }
  163. /*
  164. * /dev/watchdog handling
  165. */
  166. static int esb_open(struct inode *inode, struct file *file)
  167. {
  168. /* /dev/watchdog can only be opened once */
  169. if (test_and_set_bit(0, &timer_alive))
  170. return -EBUSY;
  171. /* Reload and activate timer */
  172. esb_timer_start();
  173. return nonseekable_open(inode, file);
  174. }
  175. static int esb_release(struct inode *inode, struct file *file)
  176. {
  177. /* Shut off the timer. */
  178. if (esb_expect_close == 42)
  179. esb_timer_stop();
  180. else {
  181. printk(KERN_CRIT PFX
  182. "Unexpected close, not stopping watchdog!\n");
  183. esb_timer_keepalive();
  184. }
  185. clear_bit(0, &timer_alive);
  186. esb_expect_close = 0;
  187. return 0;
  188. }
  189. static ssize_t esb_write(struct file *file, const char __user *data,
  190. size_t len, loff_t *ppos)
  191. {
  192. /* See if we got the magic character 'V' and reload the timer */
  193. if (len) {
  194. if (!nowayout) {
  195. size_t i;
  196. /* note: just in case someone wrote the magic character
  197. * five months ago... */
  198. esb_expect_close = 0;
  199. /* scan to see whether or not we got the
  200. * magic character */
  201. for (i = 0; i != len; i++) {
  202. char c;
  203. if (get_user(c, data + i))
  204. return -EFAULT;
  205. if (c == 'V')
  206. esb_expect_close = 42;
  207. }
  208. }
  209. /* someone wrote to us, we should reload the timer */
  210. esb_timer_keepalive();
  211. }
  212. return len;
  213. }
  214. static long esb_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  215. {
  216. int new_options, retval = -EINVAL;
  217. int new_heartbeat;
  218. void __user *argp = (void __user *)arg;
  219. int __user *p = argp;
  220. static struct watchdog_info ident = {
  221. .options = WDIOF_SETTIMEOUT |
  222. WDIOF_KEEPALIVEPING |
  223. WDIOF_MAGICCLOSE,
  224. .firmware_version = 0,
  225. .identity = ESB_MODULE_NAME,
  226. };
  227. switch (cmd) {
  228. case WDIOC_GETSUPPORT:
  229. return copy_to_user(argp, &ident,
  230. sizeof(ident)) ? -EFAULT : 0;
  231. case WDIOC_GETSTATUS:
  232. return put_user(0, p);
  233. case WDIOC_GETBOOTSTATUS:
  234. return put_user(triggered, p);
  235. case WDIOC_SETOPTIONS:
  236. {
  237. if (get_user(new_options, p))
  238. return -EFAULT;
  239. if (new_options & WDIOS_DISABLECARD) {
  240. esb_timer_stop();
  241. retval = 0;
  242. }
  243. if (new_options & WDIOS_ENABLECARD) {
  244. esb_timer_start();
  245. retval = 0;
  246. }
  247. return retval;
  248. }
  249. case WDIOC_KEEPALIVE:
  250. esb_timer_keepalive();
  251. return 0;
  252. case WDIOC_SETTIMEOUT:
  253. {
  254. if (get_user(new_heartbeat, p))
  255. return -EFAULT;
  256. if (esb_timer_set_heartbeat(new_heartbeat))
  257. return -EINVAL;
  258. esb_timer_keepalive();
  259. /* Fall */
  260. }
  261. case WDIOC_GETTIMEOUT:
  262. return put_user(heartbeat, p);
  263. default:
  264. return -ENOTTY;
  265. }
  266. }
  267. /*
  268. * Kernel Interfaces
  269. */
  270. static const struct file_operations esb_fops = {
  271. .owner = THIS_MODULE,
  272. .llseek = no_llseek,
  273. .write = esb_write,
  274. .unlocked_ioctl = esb_ioctl,
  275. .open = esb_open,
  276. .release = esb_release,
  277. };
  278. static struct miscdevice esb_miscdev = {
  279. .minor = WATCHDOG_MINOR,
  280. .name = "watchdog",
  281. .fops = &esb_fops,
  282. };
  283. /*
  284. * Data for PCI driver interface
  285. *
  286. * This data only exists for exporting the supported
  287. * PCI ids via MODULE_DEVICE_TABLE. We do not actually
  288. * register a pci_driver, because someone else might one day
  289. * want to register another driver on the same PCI id.
  290. */
  291. static struct pci_device_id esb_pci_tbl[] = {
  292. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_9), },
  293. { 0, }, /* End of list */
  294. };
  295. MODULE_DEVICE_TABLE(pci, esb_pci_tbl);
  296. /*
  297. * Init & exit routines
  298. */
  299. static unsigned char __devinit esb_getdevice(void)
  300. {
  301. /*
  302. * Find the PCI device
  303. */
  304. esb_pci = pci_get_device(PCI_VENDOR_ID_INTEL,
  305. PCI_DEVICE_ID_INTEL_ESB_9, NULL);
  306. if (!esb_pci)
  307. return 0;
  308. if (pci_enable_device(esb_pci)) {
  309. printk(KERN_ERR PFX "failed to enable device\n");
  310. goto err_devput;
  311. }
  312. if (pci_request_region(esb_pci, 0, ESB_MODULE_NAME)) {
  313. printk(KERN_ERR PFX "failed to request region\n");
  314. goto err_disable;
  315. }
  316. BASEADDR = pci_ioremap_bar(esb_pci, 0);
  317. if (BASEADDR == NULL) {
  318. /* Something's wrong here, BASEADDR has to be set */
  319. printk(KERN_ERR PFX "failed to get BASEADDR\n");
  320. goto err_release;
  321. }
  322. /* Done */
  323. return 1;
  324. err_release:
  325. pci_release_region(esb_pci, 0);
  326. err_disable:
  327. pci_disable_device(esb_pci);
  328. err_devput:
  329. pci_dev_put(esb_pci);
  330. return 0;
  331. }
  332. static void __devinit esb_initdevice(void)
  333. {
  334. u8 val1;
  335. u16 val2;
  336. /*
  337. * Config register:
  338. * Bit 5 : 0 = Enable WDT_OUTPUT
  339. * Bit 2 : 0 = set the timer frequency to the PCI clock
  340. * divided by 2^15 (approx 1KHz).
  341. * Bits 1:0 : 11 = WDT_INT_TYPE Disabled.
  342. * The watchdog has two timers, it can be setup so that the
  343. * expiry of timer1 results in an interrupt and the expiry of
  344. * timer2 results in a reboot. We set it to not generate
  345. * any interrupts as there is not much we can do with it
  346. * right now.
  347. */
  348. pci_write_config_word(esb_pci, ESB_CONFIG_REG, 0x0003);
  349. /* Check that the WDT isn't already locked */
  350. pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val1);
  351. if (val1 & ESB_WDT_LOCK)
  352. printk(KERN_WARNING PFX "nowayout already set\n");
  353. /* Set the timer to watchdog mode and disable it for now */
  354. pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x00);
  355. /* Check if the watchdog was previously triggered */
  356. esb_unlock_registers();
  357. val2 = readw(ESB_RELOAD_REG);
  358. if (val2 & ESB_WDT_TIMEOUT)
  359. triggered = WDIOF_CARDRESET;
  360. /* Reset WDT_TIMEOUT flag and timers */
  361. esb_unlock_registers();
  362. writew((ESB_WDT_TIMEOUT | ESB_WDT_RELOAD), ESB_RELOAD_REG);
  363. /* And set the correct timeout value */
  364. esb_timer_set_heartbeat(heartbeat);
  365. }
  366. static int __devinit esb_probe(struct platform_device *dev)
  367. {
  368. int ret;
  369. /* Check whether or not the hardware watchdog is there */
  370. if (!esb_getdevice() || esb_pci == NULL)
  371. return -ENODEV;
  372. /* Check that the heartbeat value is within it's range;
  373. if not reset to the default */
  374. if (heartbeat < 0x1 || heartbeat > 2 * 0x03ff) {
  375. heartbeat = WATCHDOG_HEARTBEAT;
  376. printk(KERN_INFO PFX
  377. "heartbeat value must be 1<heartbeat<2046, using %d\n",
  378. heartbeat);
  379. }
  380. /* Initialize the watchdog and make sure it does not run */
  381. esb_initdevice();
  382. /* Register the watchdog so that userspace has access to it */
  383. ret = misc_register(&esb_miscdev);
  384. if (ret != 0) {
  385. printk(KERN_ERR PFX
  386. "cannot register miscdev on minor=%d (err=%d)\n",
  387. WATCHDOG_MINOR, ret);
  388. goto err_unmap;
  389. }
  390. printk(KERN_INFO PFX
  391. "initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n",
  392. BASEADDR, heartbeat, nowayout);
  393. return 0;
  394. err_unmap:
  395. iounmap(BASEADDR);
  396. pci_release_region(esb_pci, 0);
  397. pci_disable_device(esb_pci);
  398. pci_dev_put(esb_pci);
  399. return ret;
  400. }
  401. static int __devexit esb_remove(struct platform_device *dev)
  402. {
  403. /* Stop the timer before we leave */
  404. if (!nowayout)
  405. esb_timer_stop();
  406. /* Deregister */
  407. misc_deregister(&esb_miscdev);
  408. iounmap(BASEADDR);
  409. pci_release_region(esb_pci, 0);
  410. pci_disable_device(esb_pci);
  411. pci_dev_put(esb_pci);
  412. return 0;
  413. }
  414. static void esb_shutdown(struct platform_device *dev)
  415. {
  416. esb_timer_stop();
  417. }
  418. static struct platform_driver esb_platform_driver = {
  419. .probe = esb_probe,
  420. .remove = __devexit_p(esb_remove),
  421. .shutdown = esb_shutdown,
  422. .driver = {
  423. .owner = THIS_MODULE,
  424. .name = ESB_MODULE_NAME,
  425. },
  426. };
  427. static int __init watchdog_init(void)
  428. {
  429. int err;
  430. printk(KERN_INFO PFX "Intel 6300ESB WatchDog Timer Driver v%s\n",
  431. ESB_VERSION);
  432. err = platform_driver_register(&esb_platform_driver);
  433. if (err)
  434. return err;
  435. esb_platform_device = platform_device_register_simple(ESB_MODULE_NAME,
  436. -1, NULL, 0);
  437. if (IS_ERR(esb_platform_device)) {
  438. err = PTR_ERR(esb_platform_device);
  439. goto unreg_platform_driver;
  440. }
  441. return 0;
  442. unreg_platform_driver:
  443. platform_driver_unregister(&esb_platform_driver);
  444. return err;
  445. }
  446. static void __exit watchdog_cleanup(void)
  447. {
  448. platform_device_unregister(esb_platform_device);
  449. platform_driver_unregister(&esb_platform_driver);
  450. printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
  451. }
  452. module_init(watchdog_init);
  453. module_exit(watchdog_cleanup);
  454. MODULE_AUTHOR("Ross Biro and David Härdeman");
  455. MODULE_DESCRIPTION("Watchdog driver for Intel 6300ESB chipsets");
  456. MODULE_LICENSE("GPL");
  457. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);