isp1760-hcd.c 55 KB

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  1. /*
  2. * Driver for the NXP ISP1760 chip
  3. *
  4. * However, the code might contain some bugs. What doesn't work for sure is:
  5. * - ISO
  6. * - OTG
  7. e The interrupt line is configured as active low, level.
  8. *
  9. * (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
  10. *
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/slab.h>
  15. #include <linux/list.h>
  16. #include <linux/usb.h>
  17. #include <linux/debugfs.h>
  18. #include <linux/uaccess.h>
  19. #include <linux/io.h>
  20. #include <asm/unaligned.h>
  21. #include "../core/hcd.h"
  22. #include "isp1760-hcd.h"
  23. static struct kmem_cache *qtd_cachep;
  24. static struct kmem_cache *qh_cachep;
  25. struct isp1760_hcd {
  26. u32 hcs_params;
  27. spinlock_t lock;
  28. struct inter_packet_info atl_ints[32];
  29. struct inter_packet_info int_ints[32];
  30. struct memory_chunk memory_pool[BLOCKS];
  31. /* periodic schedule support */
  32. #define DEFAULT_I_TDPS 1024
  33. unsigned periodic_size;
  34. unsigned i_thresh;
  35. unsigned long reset_done;
  36. unsigned long next_statechange;
  37. unsigned int devflags;
  38. };
  39. static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd)
  40. {
  41. return (struct isp1760_hcd *) (hcd->hcd_priv);
  42. }
  43. static inline struct usb_hcd *priv_to_hcd(struct isp1760_hcd *priv)
  44. {
  45. return container_of((void *) priv, struct usb_hcd, hcd_priv);
  46. }
  47. /* Section 2.2 Host Controller Capability Registers */
  48. #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
  49. #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
  50. #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
  51. #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
  52. #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
  53. #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
  54. #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
  55. /* Section 2.3 Host Controller Operational Registers */
  56. #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
  57. #define CMD_RESET (1<<1) /* reset HC not bus */
  58. #define CMD_RUN (1<<0) /* start/stop HC */
  59. #define STS_PCD (1<<2) /* port change detect */
  60. #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
  61. #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
  62. #define PORT_POWER (1<<12) /* true: has power (see PPC) */
  63. #define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
  64. #define PORT_RESET (1<<8) /* reset port */
  65. #define PORT_SUSPEND (1<<7) /* suspend port */
  66. #define PORT_RESUME (1<<6) /* resume it */
  67. #define PORT_PE (1<<2) /* port enable */
  68. #define PORT_CSC (1<<1) /* connect status change */
  69. #define PORT_CONNECT (1<<0) /* device connected */
  70. #define PORT_RWC_BITS (PORT_CSC)
  71. struct isp1760_qtd {
  72. struct isp1760_qtd *hw_next;
  73. u8 packet_type;
  74. u8 toggle;
  75. void *data_buffer;
  76. /* the rest is HCD-private */
  77. struct list_head qtd_list;
  78. struct urb *urb;
  79. size_t length;
  80. /* isp special*/
  81. u32 status;
  82. #define URB_COMPLETE_NOTIFY (1 << 0)
  83. #define URB_ENQUEUED (1 << 1)
  84. #define URB_TYPE_ATL (1 << 2)
  85. #define URB_TYPE_INT (1 << 3)
  86. };
  87. struct isp1760_qh {
  88. /* first part defined by EHCI spec */
  89. struct list_head qtd_list;
  90. struct isp1760_hcd *priv;
  91. /* periodic schedule info */
  92. unsigned short period; /* polling interval */
  93. struct usb_device *dev;
  94. u32 toggle;
  95. u32 ping;
  96. };
  97. #define ehci_port_speed(priv, portsc) (1 << USB_PORT_FEAT_HIGHSPEED)
  98. static unsigned int isp1760_readl(__u32 __iomem *regs)
  99. {
  100. return readl(regs);
  101. }
  102. static void isp1760_writel(const unsigned int val, __u32 __iomem *regs)
  103. {
  104. writel(val, regs);
  105. }
  106. /*
  107. * The next two copy via MMIO data to/from the device. memcpy_{to|from}io()
  108. * doesn't quite work because some people have to enforce 32-bit access
  109. */
  110. static void priv_read_copy(struct isp1760_hcd *priv, u32 *src,
  111. __u32 __iomem *dst, u32 len)
  112. {
  113. u32 val;
  114. u8 *buff8;
  115. if (!src) {
  116. printk(KERN_ERR "ERROR: buffer: %p len: %d\n", src, len);
  117. return;
  118. }
  119. while (len >= 4) {
  120. *src = __raw_readl(dst);
  121. len -= 4;
  122. src++;
  123. dst++;
  124. }
  125. if (!len)
  126. return;
  127. /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully
  128. * allocated.
  129. */
  130. val = isp1760_readl(dst);
  131. buff8 = (u8 *)src;
  132. while (len) {
  133. *buff8 = val;
  134. val >>= 8;
  135. len--;
  136. buff8++;
  137. }
  138. }
  139. static void priv_write_copy(const struct isp1760_hcd *priv, const u32 *src,
  140. __u32 __iomem *dst, u32 len)
  141. {
  142. while (len >= 4) {
  143. __raw_writel(*src, dst);
  144. len -= 4;
  145. src++;
  146. dst++;
  147. }
  148. if (!len)
  149. return;
  150. /* in case we have 3, 2 or 1 by left. The buffer is allocated and the
  151. * extra bytes should not be read by the HW
  152. */
  153. __raw_writel(*src, dst);
  154. }
  155. /* memory management of the 60kb on the chip from 0x1000 to 0xffff */
  156. static void init_memory(struct isp1760_hcd *priv)
  157. {
  158. int i;
  159. u32 payload;
  160. payload = 0x1000;
  161. for (i = 0; i < BLOCK_1_NUM; i++) {
  162. priv->memory_pool[i].start = payload;
  163. priv->memory_pool[i].size = BLOCK_1_SIZE;
  164. priv->memory_pool[i].free = 1;
  165. payload += priv->memory_pool[i].size;
  166. }
  167. for (i = BLOCK_1_NUM; i < BLOCK_1_NUM + BLOCK_2_NUM; i++) {
  168. priv->memory_pool[i].start = payload;
  169. priv->memory_pool[i].size = BLOCK_2_SIZE;
  170. priv->memory_pool[i].free = 1;
  171. payload += priv->memory_pool[i].size;
  172. }
  173. for (i = BLOCK_1_NUM + BLOCK_2_NUM; i < BLOCKS; i++) {
  174. priv->memory_pool[i].start = payload;
  175. priv->memory_pool[i].size = BLOCK_3_SIZE;
  176. priv->memory_pool[i].free = 1;
  177. payload += priv->memory_pool[i].size;
  178. }
  179. BUG_ON(payload - priv->memory_pool[i - 1].size > PAYLOAD_SIZE);
  180. }
  181. static u32 alloc_mem(struct isp1760_hcd *priv, u32 size)
  182. {
  183. int i;
  184. if (!size)
  185. return ISP1760_NULL_POINTER;
  186. for (i = 0; i < BLOCKS; i++) {
  187. if (priv->memory_pool[i].size >= size &&
  188. priv->memory_pool[i].free) {
  189. priv->memory_pool[i].free = 0;
  190. return priv->memory_pool[i].start;
  191. }
  192. }
  193. printk(KERN_ERR "ISP1760 MEM: can not allocate %d bytes of memory\n",
  194. size);
  195. printk(KERN_ERR "Current memory map:\n");
  196. for (i = 0; i < BLOCKS; i++) {
  197. printk(KERN_ERR "Pool %2d size %4d status: %d\n",
  198. i, priv->memory_pool[i].size,
  199. priv->memory_pool[i].free);
  200. }
  201. /* XXX maybe -ENOMEM could be possible */
  202. BUG();
  203. return 0;
  204. }
  205. static void free_mem(struct isp1760_hcd *priv, u32 mem)
  206. {
  207. int i;
  208. if (mem == ISP1760_NULL_POINTER)
  209. return;
  210. for (i = 0; i < BLOCKS; i++) {
  211. if (priv->memory_pool[i].start == mem) {
  212. BUG_ON(priv->memory_pool[i].free);
  213. priv->memory_pool[i].free = 1;
  214. return ;
  215. }
  216. }
  217. printk(KERN_ERR "Trying to free not-here-allocated memory :%08x\n",
  218. mem);
  219. BUG();
  220. }
  221. static void isp1760_init_regs(struct usb_hcd *hcd)
  222. {
  223. isp1760_writel(0, hcd->regs + HC_BUFFER_STATUS_REG);
  224. isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
  225. HC_ATL_PTD_SKIPMAP_REG);
  226. isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
  227. HC_INT_PTD_SKIPMAP_REG);
  228. isp1760_writel(NO_TRANSFER_ACTIVE, hcd->regs +
  229. HC_ISO_PTD_SKIPMAP_REG);
  230. isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
  231. HC_ATL_PTD_DONEMAP_REG);
  232. isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
  233. HC_INT_PTD_DONEMAP_REG);
  234. isp1760_writel(~NO_TRANSFER_ACTIVE, hcd->regs +
  235. HC_ISO_PTD_DONEMAP_REG);
  236. }
  237. static int handshake(struct isp1760_hcd *priv, void __iomem *ptr,
  238. u32 mask, u32 done, int usec)
  239. {
  240. u32 result;
  241. do {
  242. result = isp1760_readl(ptr);
  243. if (result == ~0)
  244. return -ENODEV;
  245. result &= mask;
  246. if (result == done)
  247. return 0;
  248. udelay(1);
  249. usec--;
  250. } while (usec > 0);
  251. return -ETIMEDOUT;
  252. }
  253. /* reset a non-running (STS_HALT == 1) controller */
  254. static int ehci_reset(struct isp1760_hcd *priv)
  255. {
  256. int retval;
  257. struct usb_hcd *hcd = priv_to_hcd(priv);
  258. u32 command = isp1760_readl(hcd->regs + HC_USBCMD);
  259. command |= CMD_RESET;
  260. isp1760_writel(command, hcd->regs + HC_USBCMD);
  261. hcd->state = HC_STATE_HALT;
  262. priv->next_statechange = jiffies;
  263. retval = handshake(priv, hcd->regs + HC_USBCMD,
  264. CMD_RESET, 0, 250 * 1000);
  265. return retval;
  266. }
  267. static void qh_destroy(struct isp1760_qh *qh)
  268. {
  269. BUG_ON(!list_empty(&qh->qtd_list));
  270. kmem_cache_free(qh_cachep, qh);
  271. }
  272. static struct isp1760_qh *isp1760_qh_alloc(struct isp1760_hcd *priv,
  273. gfp_t flags)
  274. {
  275. struct isp1760_qh *qh;
  276. qh = kmem_cache_zalloc(qh_cachep, flags);
  277. if (!qh)
  278. return qh;
  279. INIT_LIST_HEAD(&qh->qtd_list);
  280. qh->priv = priv;
  281. return qh;
  282. }
  283. /* magic numbers that can affect system performance */
  284. #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
  285. #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
  286. #define EHCI_TUNE_RL_TT 0
  287. #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
  288. #define EHCI_TUNE_MULT_TT 1
  289. #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
  290. /* one-time init, only for memory state */
  291. static int priv_init(struct usb_hcd *hcd)
  292. {
  293. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  294. u32 hcc_params;
  295. spin_lock_init(&priv->lock);
  296. /*
  297. * hw default: 1K periodic list heads, one per frame.
  298. * periodic_size can shrink by USBCMD update if hcc_params allows.
  299. */
  300. priv->periodic_size = DEFAULT_I_TDPS;
  301. /* controllers may cache some of the periodic schedule ... */
  302. hcc_params = isp1760_readl(hcd->regs + HC_HCCPARAMS);
  303. /* full frame cache */
  304. if (HCC_ISOC_CACHE(hcc_params))
  305. priv->i_thresh = 8;
  306. else /* N microframes cached */
  307. priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
  308. return 0;
  309. }
  310. static int isp1760_hc_setup(struct usb_hcd *hcd)
  311. {
  312. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  313. int result;
  314. u32 scratch, hwmode;
  315. /* Setup HW Mode Control: This assumes a level active-low interrupt */
  316. hwmode = HW_DATA_BUS_32BIT;
  317. if (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16)
  318. hwmode &= ~HW_DATA_BUS_32BIT;
  319. if (priv->devflags & ISP1760_FLAG_ANALOG_OC)
  320. hwmode |= HW_ANA_DIGI_OC;
  321. if (priv->devflags & ISP1760_FLAG_DACK_POL_HIGH)
  322. hwmode |= HW_DACK_POL_HIGH;
  323. if (priv->devflags & ISP1760_FLAG_DREQ_POL_HIGH)
  324. hwmode |= HW_DREQ_POL_HIGH;
  325. /*
  326. * We have to set this first in case we're in 16-bit mode.
  327. * Write it twice to ensure correct upper bits if switching
  328. * to 16-bit mode.
  329. */
  330. isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
  331. isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
  332. isp1760_writel(0xdeadbabe, hcd->regs + HC_SCRATCH_REG);
  333. /* Change bus pattern */
  334. scratch = isp1760_readl(hcd->regs + HC_CHIP_ID_REG);
  335. scratch = isp1760_readl(hcd->regs + HC_SCRATCH_REG);
  336. if (scratch != 0xdeadbabe) {
  337. printk(KERN_ERR "ISP1760: Scratch test failed.\n");
  338. return -ENODEV;
  339. }
  340. /* pre reset */
  341. isp1760_init_regs(hcd);
  342. /* reset */
  343. isp1760_writel(SW_RESET_RESET_ALL, hcd->regs + HC_RESET_REG);
  344. mdelay(100);
  345. isp1760_writel(SW_RESET_RESET_HC, hcd->regs + HC_RESET_REG);
  346. mdelay(100);
  347. result = ehci_reset(priv);
  348. if (result)
  349. return result;
  350. /* Step 11 passed */
  351. isp1760_info(priv, "bus width: %d, oc: %s\n",
  352. (priv->devflags & ISP1760_FLAG_BUS_WIDTH_16) ?
  353. 16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
  354. "analog" : "digital");
  355. /* ATL reset */
  356. isp1760_writel(hwmode | ALL_ATX_RESET, hcd->regs + HC_HW_MODE_CTRL);
  357. mdelay(10);
  358. isp1760_writel(hwmode, hcd->regs + HC_HW_MODE_CTRL);
  359. isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_REG);
  360. isp1760_writel(INTERRUPT_ENABLE_MASK, hcd->regs + HC_INTERRUPT_ENABLE);
  361. /*
  362. * PORT 1 Control register of the ISP1760 is the OTG control
  363. * register on ISP1761. Since there is no OTG or device controller
  364. * support in this driver, we use port 1 as a "normal" USB host port on
  365. * both chips.
  366. */
  367. isp1760_writel(PORT1_POWER | PORT1_INIT2,
  368. hcd->regs + HC_PORT1_CTRL);
  369. mdelay(10);
  370. priv->hcs_params = isp1760_readl(hcd->regs + HC_HCSPARAMS);
  371. return priv_init(hcd);
  372. }
  373. static void isp1760_init_maps(struct usb_hcd *hcd)
  374. {
  375. /*set last maps, for iso its only 1, else 32 tds bitmap*/
  376. isp1760_writel(0x80000000, hcd->regs + HC_ATL_PTD_LASTPTD_REG);
  377. isp1760_writel(0x80000000, hcd->regs + HC_INT_PTD_LASTPTD_REG);
  378. isp1760_writel(0x00000001, hcd->regs + HC_ISO_PTD_LASTPTD_REG);
  379. }
  380. static void isp1760_enable_interrupts(struct usb_hcd *hcd)
  381. {
  382. isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_AND_REG);
  383. isp1760_writel(0, hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
  384. isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_AND_REG);
  385. isp1760_writel(0, hcd->regs + HC_INT_IRQ_MASK_OR_REG);
  386. isp1760_writel(0, hcd->regs + HC_ISO_IRQ_MASK_AND_REG);
  387. isp1760_writel(0xffffffff, hcd->regs + HC_ISO_IRQ_MASK_OR_REG);
  388. /* step 23 passed */
  389. }
  390. static int isp1760_run(struct usb_hcd *hcd)
  391. {
  392. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  393. int retval;
  394. u32 temp;
  395. u32 command;
  396. u32 chipid;
  397. hcd->uses_new_polling = 1;
  398. hcd->poll_rh = 0;
  399. hcd->state = HC_STATE_RUNNING;
  400. isp1760_enable_interrupts(hcd);
  401. temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
  402. isp1760_writel(temp | HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
  403. command = isp1760_readl(hcd->regs + HC_USBCMD);
  404. command &= ~(CMD_LRESET|CMD_RESET);
  405. command |= CMD_RUN;
  406. isp1760_writel(command, hcd->regs + HC_USBCMD);
  407. retval = handshake(priv, hcd->regs + HC_USBCMD, CMD_RUN, CMD_RUN,
  408. 250 * 1000);
  409. if (retval)
  410. return retval;
  411. /*
  412. * XXX
  413. * Spec says to write FLAG_CF as last config action, priv code grabs
  414. * the semaphore while doing so.
  415. */
  416. down_write(&ehci_cf_port_reset_rwsem);
  417. isp1760_writel(FLAG_CF, hcd->regs + HC_CONFIGFLAG);
  418. retval = handshake(priv, hcd->regs + HC_CONFIGFLAG, FLAG_CF, FLAG_CF,
  419. 250 * 1000);
  420. up_write(&ehci_cf_port_reset_rwsem);
  421. if (retval)
  422. return retval;
  423. chipid = isp1760_readl(hcd->regs + HC_CHIP_ID_REG);
  424. isp1760_info(priv, "USB ISP %04x HW rev. %d started\n", chipid & 0xffff,
  425. chipid >> 16);
  426. /* PTD Register Init Part 2, Step 28 */
  427. /* enable INTs */
  428. isp1760_init_maps(hcd);
  429. /* GRR this is run-once init(), being done every time the HC starts.
  430. * So long as they're part of class devices, we can't do it init()
  431. * since the class device isn't created that early.
  432. */
  433. return 0;
  434. }
  435. static u32 base_to_chip(u32 base)
  436. {
  437. return ((base - 0x400) >> 3);
  438. }
  439. static void transform_into_atl(struct isp1760_hcd *priv, struct isp1760_qh *qh,
  440. struct isp1760_qtd *qtd, struct urb *urb,
  441. u32 payload, struct ptd *ptd)
  442. {
  443. u32 dw0;
  444. u32 dw1;
  445. u32 dw2;
  446. u32 dw3;
  447. u32 maxpacket;
  448. u32 multi;
  449. u32 pid_code;
  450. u32 rl = RL_COUNTER;
  451. u32 nak = NAK_COUNTER;
  452. /* according to 3.6.2, max packet len can not be > 0x400 */
  453. maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
  454. multi = 1 + ((maxpacket >> 11) & 0x3);
  455. maxpacket &= 0x7ff;
  456. /* DW0 */
  457. dw0 = PTD_VALID;
  458. dw0 |= PTD_LENGTH(qtd->length);
  459. dw0 |= PTD_MAXPACKET(maxpacket);
  460. dw0 |= PTD_ENDPOINT(usb_pipeendpoint(urb->pipe));
  461. dw1 = usb_pipeendpoint(urb->pipe) >> 1;
  462. /* DW1 */
  463. dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(urb->pipe));
  464. pid_code = qtd->packet_type;
  465. dw1 |= PTD_PID_TOKEN(pid_code);
  466. if (usb_pipebulk(urb->pipe))
  467. dw1 |= PTD_TRANS_BULK;
  468. else if (usb_pipeint(urb->pipe))
  469. dw1 |= PTD_TRANS_INT;
  470. if (urb->dev->speed != USB_SPEED_HIGH) {
  471. /* split transaction */
  472. dw1 |= PTD_TRANS_SPLIT;
  473. if (urb->dev->speed == USB_SPEED_LOW)
  474. dw1 |= PTD_SE_USB_LOSPEED;
  475. dw1 |= PTD_PORT_NUM(urb->dev->ttport);
  476. dw1 |= PTD_HUB_NUM(urb->dev->tt->hub->devnum);
  477. /* SE bit for Split INT transfers */
  478. if (usb_pipeint(urb->pipe) &&
  479. (urb->dev->speed == USB_SPEED_LOW))
  480. dw1 |= 2 << 16;
  481. dw3 = 0;
  482. rl = 0;
  483. nak = 0;
  484. } else {
  485. dw0 |= PTD_MULTI(multi);
  486. if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe))
  487. dw3 = qh->ping;
  488. else
  489. dw3 = 0;
  490. }
  491. /* DW2 */
  492. dw2 = 0;
  493. dw2 |= PTD_DATA_START_ADDR(base_to_chip(payload));
  494. dw2 |= PTD_RL_CNT(rl);
  495. dw3 |= PTD_NAC_CNT(nak);
  496. /* DW3 */
  497. if (usb_pipecontrol(urb->pipe))
  498. dw3 |= PTD_DATA_TOGGLE(qtd->toggle);
  499. else
  500. dw3 |= qh->toggle;
  501. dw3 |= PTD_ACTIVE;
  502. /* Cerr */
  503. dw3 |= PTD_CERR(ERR_COUNTER);
  504. memset(ptd, 0, sizeof(*ptd));
  505. ptd->dw0 = cpu_to_le32(dw0);
  506. ptd->dw1 = cpu_to_le32(dw1);
  507. ptd->dw2 = cpu_to_le32(dw2);
  508. ptd->dw3 = cpu_to_le32(dw3);
  509. }
  510. static void transform_add_int(struct isp1760_hcd *priv, struct isp1760_qh *qh,
  511. struct isp1760_qtd *qtd, struct urb *urb,
  512. u32 payload, struct ptd *ptd)
  513. {
  514. u32 maxpacket;
  515. u32 multi;
  516. u32 numberofusofs;
  517. u32 i;
  518. u32 usofmask, usof;
  519. u32 period;
  520. maxpacket = usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe));
  521. multi = 1 + ((maxpacket >> 11) & 0x3);
  522. maxpacket &= 0x7ff;
  523. /* length of the data per uframe */
  524. maxpacket = multi * maxpacket;
  525. numberofusofs = urb->transfer_buffer_length / maxpacket;
  526. if (urb->transfer_buffer_length % maxpacket)
  527. numberofusofs += 1;
  528. usofmask = 1;
  529. usof = 0;
  530. for (i = 0; i < numberofusofs; i++) {
  531. usof |= usofmask;
  532. usofmask <<= 1;
  533. }
  534. if (urb->dev->speed != USB_SPEED_HIGH) {
  535. /* split */
  536. ptd->dw5 = cpu_to_le32(0x1c);
  537. if (qh->period >= 32)
  538. period = qh->period / 2;
  539. else
  540. period = qh->period;
  541. } else {
  542. if (qh->period >= 8)
  543. period = qh->period/8;
  544. else
  545. period = qh->period;
  546. if (period >= 32)
  547. period = 16;
  548. if (qh->period >= 8) {
  549. /* millisecond period */
  550. period = (period << 3);
  551. } else {
  552. /* usof based tranmsfers */
  553. /* minimum 4 usofs */
  554. usof = 0x11;
  555. }
  556. }
  557. ptd->dw2 |= cpu_to_le32(period);
  558. ptd->dw4 = cpu_to_le32(usof);
  559. }
  560. static void transform_into_int(struct isp1760_hcd *priv, struct isp1760_qh *qh,
  561. struct isp1760_qtd *qtd, struct urb *urb,
  562. u32 payload, struct ptd *ptd)
  563. {
  564. transform_into_atl(priv, qh, qtd, urb, payload, ptd);
  565. transform_add_int(priv, qh, qtd, urb, payload, ptd);
  566. }
  567. static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len,
  568. u32 token)
  569. {
  570. int count;
  571. qtd->data_buffer = databuffer;
  572. qtd->packet_type = GET_QTD_TOKEN_TYPE(token);
  573. qtd->toggle = GET_DATA_TOGGLE(token);
  574. if (len > HC_ATL_PL_SIZE)
  575. count = HC_ATL_PL_SIZE;
  576. else
  577. count = len;
  578. qtd->length = count;
  579. return count;
  580. }
  581. static int check_error(struct ptd *ptd)
  582. {
  583. int error = 0;
  584. u32 dw3;
  585. dw3 = le32_to_cpu(ptd->dw3);
  586. if (dw3 & DW3_HALT_BIT)
  587. error = -EPIPE;
  588. if (dw3 & DW3_ERROR_BIT) {
  589. printk(KERN_ERR "error bit is set in DW3\n");
  590. error = -EPIPE;
  591. }
  592. if (dw3 & DW3_QTD_ACTIVE) {
  593. printk(KERN_ERR "transfer active bit is set DW3\n");
  594. printk(KERN_ERR "nak counter: %d, rl: %d\n", (dw3 >> 19) & 0xf,
  595. (le32_to_cpu(ptd->dw2) >> 25) & 0xf);
  596. }
  597. return error;
  598. }
  599. static void check_int_err_status(u32 dw4)
  600. {
  601. u32 i;
  602. dw4 >>= 8;
  603. for (i = 0; i < 8; i++) {
  604. switch (dw4 & 0x7) {
  605. case INT_UNDERRUN:
  606. printk(KERN_ERR "ERROR: under run , %d\n", i);
  607. break;
  608. case INT_EXACT:
  609. printk(KERN_ERR "ERROR: transaction error, %d\n", i);
  610. break;
  611. case INT_BABBLE:
  612. printk(KERN_ERR "ERROR: babble error, %d\n", i);
  613. break;
  614. }
  615. dw4 >>= 3;
  616. }
  617. }
  618. static void enqueue_one_qtd(struct isp1760_qtd *qtd, struct isp1760_hcd *priv,
  619. u32 payload)
  620. {
  621. u32 token;
  622. struct usb_hcd *hcd = priv_to_hcd(priv);
  623. token = qtd->packet_type;
  624. if (qtd->length && (qtd->length <= HC_ATL_PL_SIZE)) {
  625. switch (token) {
  626. case IN_PID:
  627. break;
  628. case OUT_PID:
  629. case SETUP_PID:
  630. priv_write_copy(priv, qtd->data_buffer,
  631. hcd->regs + payload,
  632. qtd->length);
  633. }
  634. }
  635. }
  636. static void enqueue_one_atl_qtd(u32 atl_regs, u32 payload,
  637. struct isp1760_hcd *priv, struct isp1760_qh *qh,
  638. struct urb *urb, u32 slot, struct isp1760_qtd *qtd)
  639. {
  640. struct ptd ptd;
  641. struct usb_hcd *hcd = priv_to_hcd(priv);
  642. transform_into_atl(priv, qh, qtd, urb, payload, &ptd);
  643. priv_write_copy(priv, (u32 *)&ptd, hcd->regs + atl_regs, sizeof(ptd));
  644. enqueue_one_qtd(qtd, priv, payload);
  645. priv->atl_ints[slot].urb = urb;
  646. priv->atl_ints[slot].qh = qh;
  647. priv->atl_ints[slot].qtd = qtd;
  648. priv->atl_ints[slot].data_buffer = qtd->data_buffer;
  649. priv->atl_ints[slot].payload = payload;
  650. qtd->status |= URB_ENQUEUED | URB_TYPE_ATL;
  651. qtd->status |= slot << 16;
  652. }
  653. static void enqueue_one_int_qtd(u32 int_regs, u32 payload,
  654. struct isp1760_hcd *priv, struct isp1760_qh *qh,
  655. struct urb *urb, u32 slot, struct isp1760_qtd *qtd)
  656. {
  657. struct ptd ptd;
  658. struct usb_hcd *hcd = priv_to_hcd(priv);
  659. transform_into_int(priv, qh, qtd, urb, payload, &ptd);
  660. priv_write_copy(priv, (u32 *)&ptd, hcd->regs + int_regs, sizeof(ptd));
  661. enqueue_one_qtd(qtd, priv, payload);
  662. priv->int_ints[slot].urb = urb;
  663. priv->int_ints[slot].qh = qh;
  664. priv->int_ints[slot].qtd = qtd;
  665. priv->int_ints[slot].data_buffer = qtd->data_buffer;
  666. priv->int_ints[slot].payload = payload;
  667. qtd->status |= URB_ENQUEUED | URB_TYPE_INT;
  668. qtd->status |= slot << 16;
  669. }
  670. static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
  671. struct isp1760_qtd *qtd)
  672. {
  673. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  674. u32 skip_map, or_map;
  675. u32 queue_entry;
  676. u32 slot;
  677. u32 atl_regs, payload;
  678. u32 buffstatus;
  679. /*
  680. * When this function is called from the interrupt handler to enqueue
  681. * a follow-up packet, the SKIP register gets written and read back
  682. * almost immediately. With ISP1761, this register requires a delay of
  683. * 195ns between a write and subsequent read (see section 15.1.1.3).
  684. */
  685. ndelay(195);
  686. skip_map = isp1760_readl(hcd->regs + HC_ATL_PTD_SKIPMAP_REG);
  687. BUG_ON(!skip_map);
  688. slot = __ffs(skip_map);
  689. queue_entry = 1 << slot;
  690. atl_regs = ATL_REGS_OFFSET + slot * sizeof(struct ptd);
  691. payload = alloc_mem(priv, qtd->length);
  692. enqueue_one_atl_qtd(atl_regs, payload, priv, qh, qtd->urb, slot, qtd);
  693. or_map = isp1760_readl(hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
  694. or_map |= queue_entry;
  695. isp1760_writel(or_map, hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
  696. skip_map &= ~queue_entry;
  697. isp1760_writel(skip_map, hcd->regs + HC_ATL_PTD_SKIPMAP_REG);
  698. buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG);
  699. buffstatus |= ATL_BUFFER;
  700. isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG);
  701. }
  702. static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
  703. struct isp1760_qtd *qtd)
  704. {
  705. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  706. u32 skip_map, or_map;
  707. u32 queue_entry;
  708. u32 slot;
  709. u32 int_regs, payload;
  710. u32 buffstatus;
  711. /*
  712. * When this function is called from the interrupt handler to enqueue
  713. * a follow-up packet, the SKIP register gets written and read back
  714. * almost immediately. With ISP1761, this register requires a delay of
  715. * 195ns between a write and subsequent read (see section 15.1.1.3).
  716. */
  717. ndelay(195);
  718. skip_map = isp1760_readl(hcd->regs + HC_INT_PTD_SKIPMAP_REG);
  719. BUG_ON(!skip_map);
  720. slot = __ffs(skip_map);
  721. queue_entry = 1 << slot;
  722. int_regs = INT_REGS_OFFSET + slot * sizeof(struct ptd);
  723. payload = alloc_mem(priv, qtd->length);
  724. enqueue_one_int_qtd(int_regs, payload, priv, qh, qtd->urb, slot, qtd);
  725. or_map = isp1760_readl(hcd->regs + HC_INT_IRQ_MASK_OR_REG);
  726. or_map |= queue_entry;
  727. isp1760_writel(or_map, hcd->regs + HC_INT_IRQ_MASK_OR_REG);
  728. skip_map &= ~queue_entry;
  729. isp1760_writel(skip_map, hcd->regs + HC_INT_PTD_SKIPMAP_REG);
  730. buffstatus = isp1760_readl(hcd->regs + HC_BUFFER_STATUS_REG);
  731. buffstatus |= INT_BUFFER;
  732. isp1760_writel(buffstatus, hcd->regs + HC_BUFFER_STATUS_REG);
  733. }
  734. static void isp1760_urb_done(struct isp1760_hcd *priv, struct urb *urb, int status)
  735. __releases(priv->lock)
  736. __acquires(priv->lock)
  737. {
  738. if (!urb->unlinked) {
  739. if (status == -EINPROGRESS)
  740. status = 0;
  741. }
  742. /* complete() can reenter this HCD */
  743. usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb);
  744. spin_unlock(&priv->lock);
  745. usb_hcd_giveback_urb(priv_to_hcd(priv), urb, status);
  746. spin_lock(&priv->lock);
  747. }
  748. static void isp1760_qtd_free(struct isp1760_qtd *qtd)
  749. {
  750. kmem_cache_free(qtd_cachep, qtd);
  751. }
  752. static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd)
  753. {
  754. struct isp1760_qtd *tmp_qtd;
  755. tmp_qtd = qtd->hw_next;
  756. list_del(&qtd->qtd_list);
  757. isp1760_qtd_free(qtd);
  758. return tmp_qtd;
  759. }
  760. /*
  761. * Remove this QTD from the QH list and free its memory. If this QTD
  762. * isn't the last one than remove also his successor(s).
  763. * Returns the QTD which is part of an new URB and should be enqueued.
  764. */
  765. static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd)
  766. {
  767. struct isp1760_qtd *tmp_qtd;
  768. int last_one;
  769. do {
  770. tmp_qtd = qtd->hw_next;
  771. last_one = qtd->status & URB_COMPLETE_NOTIFY;
  772. list_del(&qtd->qtd_list);
  773. isp1760_qtd_free(qtd);
  774. qtd = tmp_qtd;
  775. } while (!last_one && qtd);
  776. return qtd;
  777. }
  778. static void do_atl_int(struct usb_hcd *usb_hcd)
  779. {
  780. struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
  781. u32 done_map, skip_map;
  782. struct ptd ptd;
  783. struct urb *urb = NULL;
  784. u32 atl_regs_base;
  785. u32 atl_regs;
  786. u32 queue_entry;
  787. u32 payload;
  788. u32 length;
  789. u32 or_map;
  790. u32 status = -EINVAL;
  791. int error;
  792. struct isp1760_qtd *qtd;
  793. struct isp1760_qh *qh;
  794. u32 rl;
  795. u32 nakcount;
  796. done_map = isp1760_readl(usb_hcd->regs +
  797. HC_ATL_PTD_DONEMAP_REG);
  798. skip_map = isp1760_readl(usb_hcd->regs +
  799. HC_ATL_PTD_SKIPMAP_REG);
  800. or_map = isp1760_readl(usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
  801. or_map &= ~done_map;
  802. isp1760_writel(or_map, usb_hcd->regs + HC_ATL_IRQ_MASK_OR_REG);
  803. atl_regs_base = ATL_REGS_OFFSET;
  804. while (done_map) {
  805. u32 dw1;
  806. u32 dw2;
  807. u32 dw3;
  808. status = 0;
  809. queue_entry = __ffs(done_map);
  810. done_map &= ~(1 << queue_entry);
  811. skip_map |= 1 << queue_entry;
  812. atl_regs = atl_regs_base + queue_entry * sizeof(struct ptd);
  813. urb = priv->atl_ints[queue_entry].urb;
  814. qtd = priv->atl_ints[queue_entry].qtd;
  815. qh = priv->atl_ints[queue_entry].qh;
  816. payload = priv->atl_ints[queue_entry].payload;
  817. if (!qh) {
  818. printk(KERN_ERR "qh is 0\n");
  819. continue;
  820. }
  821. isp1760_writel(atl_regs + ISP_BANK(0), usb_hcd->regs +
  822. HC_MEMORY_REG);
  823. isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
  824. HC_MEMORY_REG);
  825. /*
  826. * write bank1 address twice to ensure the 90ns delay (time
  827. * between BANK0 write and the priv_read_copy() call is at
  828. * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 109ns)
  829. */
  830. isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
  831. HC_MEMORY_REG);
  832. priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + atl_regs +
  833. ISP_BANK(0), sizeof(ptd));
  834. dw1 = le32_to_cpu(ptd.dw1);
  835. dw2 = le32_to_cpu(ptd.dw2);
  836. dw3 = le32_to_cpu(ptd.dw3);
  837. rl = (dw2 >> 25) & 0x0f;
  838. nakcount = (dw3 >> 19) & 0xf;
  839. /* Transfer Error, *but* active and no HALT -> reload */
  840. if ((dw3 & DW3_ERROR_BIT) && (dw3 & DW3_QTD_ACTIVE) &&
  841. !(dw3 & DW3_HALT_BIT)) {
  842. /* according to ppriv code, we have to
  843. * reload this one if trasfered bytes != requested bytes
  844. * else act like everything went smooth..
  845. * XXX This just doesn't feel right and hasn't
  846. * triggered so far.
  847. */
  848. length = PTD_XFERRED_LENGTH(dw3);
  849. printk(KERN_ERR "Should reload now.... transfered %d "
  850. "of %zu\n", length, qtd->length);
  851. BUG();
  852. }
  853. if (!nakcount && (dw3 & DW3_QTD_ACTIVE)) {
  854. u32 buffstatus;
  855. /* XXX
  856. * NAKs are handled in HW by the chip. Usually if the
  857. * device is not able to send data fast enough.
  858. * This did not trigger for a long time now.
  859. */
  860. printk(KERN_ERR "Reloading ptd %p/%p... qh %p readed: "
  861. "%d of %zu done: %08x cur: %08x\n", qtd,
  862. urb, qh, PTD_XFERRED_LENGTH(dw3),
  863. qtd->length, done_map,
  864. (1 << queue_entry));
  865. /* RL counter = ERR counter */
  866. dw3 &= ~(0xf << 19);
  867. dw3 |= rl << 19;
  868. dw3 &= ~(3 << (55 - 32));
  869. dw3 |= ERR_COUNTER << (55 - 32);
  870. /*
  871. * It is not needed to write skip map back because it
  872. * is unchanged. Just make sure that this entry is
  873. * unskipped once it gets written to the HW.
  874. */
  875. skip_map &= ~(1 << queue_entry);
  876. or_map = isp1760_readl(usb_hcd->regs +
  877. HC_ATL_IRQ_MASK_OR_REG);
  878. or_map |= 1 << queue_entry;
  879. isp1760_writel(or_map, usb_hcd->regs +
  880. HC_ATL_IRQ_MASK_OR_REG);
  881. ptd.dw3 = cpu_to_le32(dw3);
  882. priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs +
  883. atl_regs, sizeof(ptd));
  884. ptd.dw0 |= cpu_to_le32(PTD_VALID);
  885. priv_write_copy(priv, (u32 *)&ptd, usb_hcd->regs +
  886. atl_regs, sizeof(ptd));
  887. buffstatus = isp1760_readl(usb_hcd->regs +
  888. HC_BUFFER_STATUS_REG);
  889. buffstatus |= ATL_BUFFER;
  890. isp1760_writel(buffstatus, usb_hcd->regs +
  891. HC_BUFFER_STATUS_REG);
  892. continue;
  893. }
  894. error = check_error(&ptd);
  895. if (error) {
  896. status = error;
  897. priv->atl_ints[queue_entry].qh->toggle = 0;
  898. priv->atl_ints[queue_entry].qh->ping = 0;
  899. urb->status = -EPIPE;
  900. #if 0
  901. printk(KERN_ERR "Error in %s().\n", __func__);
  902. printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
  903. "dw3: %08x dw4: %08x dw5: %08x dw6: "
  904. "%08x dw7: %08x\n",
  905. ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
  906. ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
  907. #endif
  908. } else {
  909. if (usb_pipetype(urb->pipe) == PIPE_BULK) {
  910. priv->atl_ints[queue_entry].qh->toggle = dw3 &
  911. (1 << 25);
  912. priv->atl_ints[queue_entry].qh->ping = dw3 &
  913. (1 << 26);
  914. }
  915. }
  916. length = PTD_XFERRED_LENGTH(dw3);
  917. if (length) {
  918. switch (DW1_GET_PID(dw1)) {
  919. case IN_PID:
  920. priv_read_copy(priv,
  921. priv->atl_ints[queue_entry].data_buffer,
  922. usb_hcd->regs + payload + ISP_BANK(1),
  923. length);
  924. case OUT_PID:
  925. urb->actual_length += length;
  926. case SETUP_PID:
  927. break;
  928. }
  929. }
  930. priv->atl_ints[queue_entry].data_buffer = NULL;
  931. priv->atl_ints[queue_entry].urb = NULL;
  932. priv->atl_ints[queue_entry].qtd = NULL;
  933. priv->atl_ints[queue_entry].qh = NULL;
  934. free_mem(priv, payload);
  935. isp1760_writel(skip_map, usb_hcd->regs +
  936. HC_ATL_PTD_SKIPMAP_REG);
  937. if (urb->status == -EPIPE) {
  938. /* HALT was received */
  939. qtd = clean_up_qtdlist(qtd);
  940. isp1760_urb_done(priv, urb, urb->status);
  941. } else if (usb_pipebulk(urb->pipe) && (length < qtd->length)) {
  942. /* short BULK received */
  943. if (urb->transfer_flags & URB_SHORT_NOT_OK) {
  944. urb->status = -EREMOTEIO;
  945. isp1760_dbg(priv, "short bulk, %d instead %zu "
  946. "with URB_SHORT_NOT_OK flag.\n",
  947. length, qtd->length);
  948. }
  949. if (urb->status == -EINPROGRESS)
  950. urb->status = 0;
  951. qtd = clean_up_qtdlist(qtd);
  952. isp1760_urb_done(priv, urb, urb->status);
  953. } else if (qtd->status & URB_COMPLETE_NOTIFY) {
  954. /* that was the last qtd of that URB */
  955. if (urb->status == -EINPROGRESS)
  956. urb->status = 0;
  957. qtd = clean_this_qtd(qtd);
  958. isp1760_urb_done(priv, urb, urb->status);
  959. } else {
  960. /* next QTD of this URB */
  961. qtd = clean_this_qtd(qtd);
  962. BUG_ON(!qtd);
  963. }
  964. if (qtd)
  965. enqueue_an_ATL_packet(usb_hcd, qh, qtd);
  966. skip_map = isp1760_readl(usb_hcd->regs +
  967. HC_ATL_PTD_SKIPMAP_REG);
  968. }
  969. }
  970. static void do_intl_int(struct usb_hcd *usb_hcd)
  971. {
  972. struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
  973. u32 done_map, skip_map;
  974. struct ptd ptd;
  975. struct urb *urb = NULL;
  976. u32 int_regs;
  977. u32 int_regs_base;
  978. u32 payload;
  979. u32 length;
  980. u32 or_map;
  981. int error;
  982. u32 queue_entry;
  983. struct isp1760_qtd *qtd;
  984. struct isp1760_qh *qh;
  985. done_map = isp1760_readl(usb_hcd->regs +
  986. HC_INT_PTD_DONEMAP_REG);
  987. skip_map = isp1760_readl(usb_hcd->regs +
  988. HC_INT_PTD_SKIPMAP_REG);
  989. or_map = isp1760_readl(usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG);
  990. or_map &= ~done_map;
  991. isp1760_writel(or_map, usb_hcd->regs + HC_INT_IRQ_MASK_OR_REG);
  992. int_regs_base = INT_REGS_OFFSET;
  993. while (done_map) {
  994. u32 dw1;
  995. u32 dw3;
  996. queue_entry = __ffs(done_map);
  997. done_map &= ~(1 << queue_entry);
  998. skip_map |= 1 << queue_entry;
  999. int_regs = int_regs_base + queue_entry * sizeof(struct ptd);
  1000. urb = priv->int_ints[queue_entry].urb;
  1001. qtd = priv->int_ints[queue_entry].qtd;
  1002. qh = priv->int_ints[queue_entry].qh;
  1003. payload = priv->int_ints[queue_entry].payload;
  1004. if (!qh) {
  1005. printk(KERN_ERR "(INT) qh is 0\n");
  1006. continue;
  1007. }
  1008. isp1760_writel(int_regs + ISP_BANK(0), usb_hcd->regs +
  1009. HC_MEMORY_REG);
  1010. isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
  1011. HC_MEMORY_REG);
  1012. /*
  1013. * write bank1 address twice to ensure the 90ns delay (time
  1014. * between BANK0 write and the priv_read_copy() call is at
  1015. * least 3*t_WHWL + 2*t_w11 = 3*25ns + 2*17ns = 92ns)
  1016. */
  1017. isp1760_writel(payload + ISP_BANK(1), usb_hcd->regs +
  1018. HC_MEMORY_REG);
  1019. priv_read_copy(priv, (u32 *)&ptd, usb_hcd->regs + int_regs +
  1020. ISP_BANK(0), sizeof(ptd));
  1021. dw1 = le32_to_cpu(ptd.dw1);
  1022. dw3 = le32_to_cpu(ptd.dw3);
  1023. check_int_err_status(le32_to_cpu(ptd.dw4));
  1024. error = check_error(&ptd);
  1025. if (error) {
  1026. #if 0
  1027. printk(KERN_ERR "Error in %s().\n", __func__);
  1028. printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
  1029. "dw3: %08x dw4: %08x dw5: %08x dw6: "
  1030. "%08x dw7: %08x\n",
  1031. ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
  1032. ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
  1033. #endif
  1034. urb->status = -EPIPE;
  1035. priv->int_ints[queue_entry].qh->toggle = 0;
  1036. priv->int_ints[queue_entry].qh->ping = 0;
  1037. } else {
  1038. priv->int_ints[queue_entry].qh->toggle =
  1039. dw3 & (1 << 25);
  1040. priv->int_ints[queue_entry].qh->ping = dw3 & (1 << 26);
  1041. }
  1042. if (urb->dev->speed != USB_SPEED_HIGH)
  1043. length = PTD_XFERRED_LENGTH_LO(dw3);
  1044. else
  1045. length = PTD_XFERRED_LENGTH(dw3);
  1046. if (length) {
  1047. switch (DW1_GET_PID(dw1)) {
  1048. case IN_PID:
  1049. priv_read_copy(priv,
  1050. priv->int_ints[queue_entry].data_buffer,
  1051. usb_hcd->regs + payload + ISP_BANK(1),
  1052. length);
  1053. case OUT_PID:
  1054. urb->actual_length += length;
  1055. case SETUP_PID:
  1056. break;
  1057. }
  1058. }
  1059. priv->int_ints[queue_entry].data_buffer = NULL;
  1060. priv->int_ints[queue_entry].urb = NULL;
  1061. priv->int_ints[queue_entry].qtd = NULL;
  1062. priv->int_ints[queue_entry].qh = NULL;
  1063. isp1760_writel(skip_map, usb_hcd->regs +
  1064. HC_INT_PTD_SKIPMAP_REG);
  1065. free_mem(priv, payload);
  1066. if (urb->status == -EPIPE) {
  1067. /* HALT received */
  1068. qtd = clean_up_qtdlist(qtd);
  1069. isp1760_urb_done(priv, urb, urb->status);
  1070. } else if (qtd->status & URB_COMPLETE_NOTIFY) {
  1071. if (urb->status == -EINPROGRESS)
  1072. urb->status = 0;
  1073. qtd = clean_this_qtd(qtd);
  1074. isp1760_urb_done(priv, urb, urb->status);
  1075. } else {
  1076. /* next QTD of this URB */
  1077. qtd = clean_this_qtd(qtd);
  1078. BUG_ON(!qtd);
  1079. }
  1080. if (qtd)
  1081. enqueue_an_INT_packet(usb_hcd, qh, qtd);
  1082. skip_map = isp1760_readl(usb_hcd->regs +
  1083. HC_INT_PTD_SKIPMAP_REG);
  1084. }
  1085. }
  1086. #define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
  1087. static struct isp1760_qh *qh_make(struct isp1760_hcd *priv, struct urb *urb,
  1088. gfp_t flags)
  1089. {
  1090. struct isp1760_qh *qh;
  1091. int is_input, type;
  1092. qh = isp1760_qh_alloc(priv, flags);
  1093. if (!qh)
  1094. return qh;
  1095. /*
  1096. * init endpoint/device data for this QH
  1097. */
  1098. is_input = usb_pipein(urb->pipe);
  1099. type = usb_pipetype(urb->pipe);
  1100. if (type == PIPE_INTERRUPT) {
  1101. if (urb->dev->speed == USB_SPEED_HIGH) {
  1102. qh->period = urb->interval >> 3;
  1103. if (qh->period == 0 && urb->interval != 1) {
  1104. /* NOTE interval 2 or 4 uframes could work.
  1105. * But interval 1 scheduling is simpler, and
  1106. * includes high bandwidth.
  1107. */
  1108. printk(KERN_ERR "intr period %d uframes, NYET!",
  1109. urb->interval);
  1110. qh_destroy(qh);
  1111. return NULL;
  1112. }
  1113. } else {
  1114. qh->period = urb->interval;
  1115. }
  1116. }
  1117. /* support for tt scheduling, and access to toggles */
  1118. qh->dev = urb->dev;
  1119. if (!usb_pipecontrol(urb->pipe))
  1120. usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input,
  1121. 1);
  1122. return qh;
  1123. }
  1124. /*
  1125. * For control/bulk/interrupt, return QH with these TDs appended.
  1126. * Allocates and initializes the QH if necessary.
  1127. * Returns null if it can't allocate a QH it needs to.
  1128. * If the QH has TDs (urbs) already, that's great.
  1129. */
  1130. static struct isp1760_qh *qh_append_tds(struct isp1760_hcd *priv,
  1131. struct urb *urb, struct list_head *qtd_list, int epnum,
  1132. void **ptr)
  1133. {
  1134. struct isp1760_qh *qh;
  1135. struct isp1760_qtd *qtd;
  1136. struct isp1760_qtd *prev_qtd;
  1137. qh = (struct isp1760_qh *)*ptr;
  1138. if (!qh) {
  1139. /* can't sleep here, we have priv->lock... */
  1140. qh = qh_make(priv, urb, GFP_ATOMIC);
  1141. if (!qh)
  1142. return qh;
  1143. *ptr = qh;
  1144. }
  1145. qtd = list_entry(qtd_list->next, struct isp1760_qtd,
  1146. qtd_list);
  1147. if (!list_empty(&qh->qtd_list))
  1148. prev_qtd = list_entry(qh->qtd_list.prev,
  1149. struct isp1760_qtd, qtd_list);
  1150. else
  1151. prev_qtd = NULL;
  1152. list_splice(qtd_list, qh->qtd_list.prev);
  1153. if (prev_qtd) {
  1154. BUG_ON(prev_qtd->hw_next);
  1155. prev_qtd->hw_next = qtd;
  1156. }
  1157. urb->hcpriv = qh;
  1158. return qh;
  1159. }
  1160. static void qtd_list_free(struct isp1760_hcd *priv, struct urb *urb,
  1161. struct list_head *qtd_list)
  1162. {
  1163. struct list_head *entry, *temp;
  1164. list_for_each_safe(entry, temp, qtd_list) {
  1165. struct isp1760_qtd *qtd;
  1166. qtd = list_entry(entry, struct isp1760_qtd, qtd_list);
  1167. list_del(&qtd->qtd_list);
  1168. isp1760_qtd_free(qtd);
  1169. }
  1170. }
  1171. static int isp1760_prepare_enqueue(struct isp1760_hcd *priv, struct urb *urb,
  1172. struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p)
  1173. {
  1174. struct isp1760_qtd *qtd;
  1175. int epnum;
  1176. unsigned long flags;
  1177. struct isp1760_qh *qh = NULL;
  1178. int rc;
  1179. int qh_busy;
  1180. qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list);
  1181. epnum = urb->ep->desc.bEndpointAddress;
  1182. spin_lock_irqsave(&priv->lock, flags);
  1183. if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &priv_to_hcd(priv)->flags)) {
  1184. rc = -ESHUTDOWN;
  1185. goto done;
  1186. }
  1187. rc = usb_hcd_link_urb_to_ep(priv_to_hcd(priv), urb);
  1188. if (rc)
  1189. goto done;
  1190. qh = urb->ep->hcpriv;
  1191. if (qh)
  1192. qh_busy = !list_empty(&qh->qtd_list);
  1193. else
  1194. qh_busy = 0;
  1195. qh = qh_append_tds(priv, urb, qtd_list, epnum, &urb->ep->hcpriv);
  1196. if (!qh) {
  1197. usb_hcd_unlink_urb_from_ep(priv_to_hcd(priv), urb);
  1198. rc = -ENOMEM;
  1199. goto done;
  1200. }
  1201. if (!qh_busy)
  1202. p(priv_to_hcd(priv), qh, qtd);
  1203. done:
  1204. spin_unlock_irqrestore(&priv->lock, flags);
  1205. if (!qh)
  1206. qtd_list_free(priv, urb, qtd_list);
  1207. return rc;
  1208. }
  1209. static struct isp1760_qtd *isp1760_qtd_alloc(struct isp1760_hcd *priv,
  1210. gfp_t flags)
  1211. {
  1212. struct isp1760_qtd *qtd;
  1213. qtd = kmem_cache_zalloc(qtd_cachep, flags);
  1214. if (qtd)
  1215. INIT_LIST_HEAD(&qtd->qtd_list);
  1216. return qtd;
  1217. }
  1218. /*
  1219. * create a list of filled qtds for this URB; won't link into qh.
  1220. */
  1221. static struct list_head *qh_urb_transaction(struct isp1760_hcd *priv,
  1222. struct urb *urb, struct list_head *head, gfp_t flags)
  1223. {
  1224. struct isp1760_qtd *qtd, *qtd_prev;
  1225. void *buf;
  1226. int len, maxpacket;
  1227. int is_input;
  1228. u32 token;
  1229. /*
  1230. * URBs map to sequences of QTDs: one logical transaction
  1231. */
  1232. qtd = isp1760_qtd_alloc(priv, flags);
  1233. if (!qtd)
  1234. return NULL;
  1235. list_add_tail(&qtd->qtd_list, head);
  1236. qtd->urb = urb;
  1237. urb->status = -EINPROGRESS;
  1238. token = 0;
  1239. /* for split transactions, SplitXState initialized to zero */
  1240. len = urb->transfer_buffer_length;
  1241. is_input = usb_pipein(urb->pipe);
  1242. if (usb_pipecontrol(urb->pipe)) {
  1243. /* SETUP pid */
  1244. qtd_fill(qtd, urb->setup_packet,
  1245. sizeof(struct usb_ctrlrequest),
  1246. token | SETUP_PID);
  1247. /* ... and always at least one more pid */
  1248. token ^= DATA_TOGGLE;
  1249. qtd_prev = qtd;
  1250. qtd = isp1760_qtd_alloc(priv, flags);
  1251. if (!qtd)
  1252. goto cleanup;
  1253. qtd->urb = urb;
  1254. qtd_prev->hw_next = qtd;
  1255. list_add_tail(&qtd->qtd_list, head);
  1256. /* for zero length DATA stages, STATUS is always IN */
  1257. if (len == 0)
  1258. token |= IN_PID;
  1259. }
  1260. /*
  1261. * data transfer stage: buffer setup
  1262. */
  1263. buf = urb->transfer_buffer;
  1264. if (is_input)
  1265. token |= IN_PID;
  1266. else
  1267. token |= OUT_PID;
  1268. maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
  1269. /*
  1270. * buffer gets wrapped in one or more qtds;
  1271. * last one may be "short" (including zero len)
  1272. * and may serve as a control status ack
  1273. */
  1274. for (;;) {
  1275. int this_qtd_len;
  1276. if (!buf && len) {
  1277. /* XXX This looks like usb storage / SCSI bug */
  1278. printk(KERN_ERR "buf is null, dma is %08lx len is %d\n",
  1279. (long unsigned)urb->transfer_dma, len);
  1280. WARN_ON(1);
  1281. }
  1282. this_qtd_len = qtd_fill(qtd, buf, len, token);
  1283. len -= this_qtd_len;
  1284. buf += this_qtd_len;
  1285. /* qh makes control packets use qtd toggle; maybe switch it */
  1286. if ((maxpacket & (this_qtd_len + (maxpacket - 1))) == 0)
  1287. token ^= DATA_TOGGLE;
  1288. if (len <= 0)
  1289. break;
  1290. qtd_prev = qtd;
  1291. qtd = isp1760_qtd_alloc(priv, flags);
  1292. if (!qtd)
  1293. goto cleanup;
  1294. qtd->urb = urb;
  1295. qtd_prev->hw_next = qtd;
  1296. list_add_tail(&qtd->qtd_list, head);
  1297. }
  1298. /*
  1299. * control requests may need a terminating data "status" ack;
  1300. * bulk ones may need a terminating short packet (zero length).
  1301. */
  1302. if (urb->transfer_buffer_length != 0) {
  1303. int one_more = 0;
  1304. if (usb_pipecontrol(urb->pipe)) {
  1305. one_more = 1;
  1306. /* "in" <--> "out" */
  1307. token ^= IN_PID;
  1308. /* force DATA1 */
  1309. token |= DATA_TOGGLE;
  1310. } else if (usb_pipebulk(urb->pipe)
  1311. && (urb->transfer_flags & URB_ZERO_PACKET)
  1312. && !(urb->transfer_buffer_length % maxpacket)) {
  1313. one_more = 1;
  1314. }
  1315. if (one_more) {
  1316. qtd_prev = qtd;
  1317. qtd = isp1760_qtd_alloc(priv, flags);
  1318. if (!qtd)
  1319. goto cleanup;
  1320. qtd->urb = urb;
  1321. qtd_prev->hw_next = qtd;
  1322. list_add_tail(&qtd->qtd_list, head);
  1323. /* never any data in such packets */
  1324. qtd_fill(qtd, NULL, 0, token);
  1325. }
  1326. }
  1327. qtd->status = URB_COMPLETE_NOTIFY;
  1328. return head;
  1329. cleanup:
  1330. qtd_list_free(priv, urb, head);
  1331. return NULL;
  1332. }
  1333. static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
  1334. gfp_t mem_flags)
  1335. {
  1336. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1337. struct list_head qtd_list;
  1338. packet_enqueue *pe;
  1339. INIT_LIST_HEAD(&qtd_list);
  1340. switch (usb_pipetype(urb->pipe)) {
  1341. case PIPE_CONTROL:
  1342. case PIPE_BULK:
  1343. if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags))
  1344. return -ENOMEM;
  1345. pe = enqueue_an_ATL_packet;
  1346. break;
  1347. case PIPE_INTERRUPT:
  1348. if (!qh_urb_transaction(priv, urb, &qtd_list, mem_flags))
  1349. return -ENOMEM;
  1350. pe = enqueue_an_INT_packet;
  1351. break;
  1352. case PIPE_ISOCHRONOUS:
  1353. printk(KERN_ERR "PIPE_ISOCHRONOUS ain't supported\n");
  1354. default:
  1355. return -EPIPE;
  1356. }
  1357. return isp1760_prepare_enqueue(priv, urb, &qtd_list, mem_flags, pe);
  1358. }
  1359. static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
  1360. int status)
  1361. {
  1362. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1363. struct inter_packet_info *ints;
  1364. u32 i;
  1365. u32 reg_base, or_reg, skip_reg;
  1366. unsigned long flags;
  1367. struct ptd ptd;
  1368. switch (usb_pipetype(urb->pipe)) {
  1369. case PIPE_ISOCHRONOUS:
  1370. return -EPIPE;
  1371. break;
  1372. case PIPE_INTERRUPT:
  1373. ints = priv->int_ints;
  1374. reg_base = INT_REGS_OFFSET;
  1375. or_reg = HC_INT_IRQ_MASK_OR_REG;
  1376. skip_reg = HC_INT_PTD_SKIPMAP_REG;
  1377. break;
  1378. default:
  1379. ints = priv->atl_ints;
  1380. reg_base = ATL_REGS_OFFSET;
  1381. or_reg = HC_ATL_IRQ_MASK_OR_REG;
  1382. skip_reg = HC_ATL_PTD_SKIPMAP_REG;
  1383. break;
  1384. }
  1385. memset(&ptd, 0, sizeof(ptd));
  1386. spin_lock_irqsave(&priv->lock, flags);
  1387. for (i = 0; i < 32; i++) {
  1388. if (ints->urb == urb) {
  1389. u32 skip_map;
  1390. u32 or_map;
  1391. struct isp1760_qtd *qtd;
  1392. skip_map = isp1760_readl(hcd->regs + skip_reg);
  1393. skip_map |= 1 << i;
  1394. isp1760_writel(skip_map, hcd->regs + skip_reg);
  1395. or_map = isp1760_readl(hcd->regs + or_reg);
  1396. or_map &= ~(1 << i);
  1397. isp1760_writel(or_map, hcd->regs + or_reg);
  1398. priv_write_copy(priv, (u32 *)&ptd, hcd->regs + reg_base
  1399. + i * sizeof(ptd), sizeof(ptd));
  1400. qtd = ints->qtd;
  1401. clean_up_qtdlist(qtd);
  1402. free_mem(priv, ints->payload);
  1403. ints->urb = NULL;
  1404. ints->qh = NULL;
  1405. ints->qtd = NULL;
  1406. ints->data_buffer = NULL;
  1407. ints->payload = 0;
  1408. isp1760_urb_done(priv, urb, status);
  1409. break;
  1410. }
  1411. ints++;
  1412. }
  1413. spin_unlock_irqrestore(&priv->lock, flags);
  1414. return 0;
  1415. }
  1416. static irqreturn_t isp1760_irq(struct usb_hcd *usb_hcd)
  1417. {
  1418. struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
  1419. u32 imask;
  1420. irqreturn_t irqret = IRQ_NONE;
  1421. spin_lock(&priv->lock);
  1422. if (!(usb_hcd->state & HC_STATE_RUNNING))
  1423. goto leave;
  1424. imask = isp1760_readl(usb_hcd->regs + HC_INTERRUPT_REG);
  1425. if (unlikely(!imask))
  1426. goto leave;
  1427. isp1760_writel(imask, usb_hcd->regs + HC_INTERRUPT_REG);
  1428. if (imask & HC_ATL_INT)
  1429. do_atl_int(usb_hcd);
  1430. if (imask & HC_INTL_INT)
  1431. do_intl_int(usb_hcd);
  1432. irqret = IRQ_HANDLED;
  1433. leave:
  1434. spin_unlock(&priv->lock);
  1435. return irqret;
  1436. }
  1437. static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
  1438. {
  1439. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1440. u32 temp, status = 0;
  1441. u32 mask;
  1442. int retval = 1;
  1443. unsigned long flags;
  1444. /* if !USB_SUSPEND, root hub timers won't get shut down ... */
  1445. if (!HC_IS_RUNNING(hcd->state))
  1446. return 0;
  1447. /* init status to no-changes */
  1448. buf[0] = 0;
  1449. mask = PORT_CSC;
  1450. spin_lock_irqsave(&priv->lock, flags);
  1451. temp = isp1760_readl(hcd->regs + HC_PORTSC1);
  1452. if (temp & PORT_OWNER) {
  1453. if (temp & PORT_CSC) {
  1454. temp &= ~PORT_CSC;
  1455. isp1760_writel(temp, hcd->regs + HC_PORTSC1);
  1456. goto done;
  1457. }
  1458. }
  1459. /*
  1460. * Return status information even for ports with OWNER set.
  1461. * Otherwise khubd wouldn't see the disconnect event when a
  1462. * high-speed device is switched over to the companion
  1463. * controller by the user.
  1464. */
  1465. if ((temp & mask) != 0
  1466. || ((temp & PORT_RESUME) != 0
  1467. && time_after_eq(jiffies,
  1468. priv->reset_done))) {
  1469. buf [0] |= 1 << (0 + 1);
  1470. status = STS_PCD;
  1471. }
  1472. /* FIXME autosuspend idle root hubs */
  1473. done:
  1474. spin_unlock_irqrestore(&priv->lock, flags);
  1475. return status ? retval : 0;
  1476. }
  1477. static void isp1760_hub_descriptor(struct isp1760_hcd *priv,
  1478. struct usb_hub_descriptor *desc)
  1479. {
  1480. int ports = HCS_N_PORTS(priv->hcs_params);
  1481. u16 temp;
  1482. desc->bDescriptorType = 0x29;
  1483. /* priv 1.0, 2.3.9 says 20ms max */
  1484. desc->bPwrOn2PwrGood = 10;
  1485. desc->bHubContrCurrent = 0;
  1486. desc->bNbrPorts = ports;
  1487. temp = 1 + (ports / 8);
  1488. desc->bDescLength = 7 + 2 * temp;
  1489. /* two bitmaps: ports removable, and usb 1.0 legacy PortPwrCtrlMask */
  1490. memset(&desc->bitmap[0], 0, temp);
  1491. memset(&desc->bitmap[temp], 0xff, temp);
  1492. /* per-port overcurrent reporting */
  1493. temp = 0x0008;
  1494. if (HCS_PPC(priv->hcs_params))
  1495. /* per-port power control */
  1496. temp |= 0x0001;
  1497. else
  1498. /* no power switching */
  1499. temp |= 0x0002;
  1500. desc->wHubCharacteristics = cpu_to_le16(temp);
  1501. }
  1502. #define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
  1503. static int check_reset_complete(struct isp1760_hcd *priv, int index,
  1504. u32 __iomem *status_reg, int port_status)
  1505. {
  1506. if (!(port_status & PORT_CONNECT))
  1507. return port_status;
  1508. /* if reset finished and it's still not enabled -- handoff */
  1509. if (!(port_status & PORT_PE)) {
  1510. printk(KERN_ERR "port %d full speed --> companion\n",
  1511. index + 1);
  1512. port_status |= PORT_OWNER;
  1513. port_status &= ~PORT_RWC_BITS;
  1514. isp1760_writel(port_status, status_reg);
  1515. } else
  1516. printk(KERN_ERR "port %d high speed\n", index + 1);
  1517. return port_status;
  1518. }
  1519. static int isp1760_hub_control(struct usb_hcd *hcd, u16 typeReq,
  1520. u16 wValue, u16 wIndex, char *buf, u16 wLength)
  1521. {
  1522. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1523. int ports = HCS_N_PORTS(priv->hcs_params);
  1524. u32 __iomem *status_reg = hcd->regs + HC_PORTSC1;
  1525. u32 temp, status;
  1526. unsigned long flags;
  1527. int retval = 0;
  1528. unsigned selector;
  1529. /*
  1530. * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
  1531. * HCS_INDICATOR may say we can change LEDs to off/amber/green.
  1532. * (track current state ourselves) ... blink for diagnostics,
  1533. * power, "this is the one", etc. EHCI spec supports this.
  1534. */
  1535. spin_lock_irqsave(&priv->lock, flags);
  1536. switch (typeReq) {
  1537. case ClearHubFeature:
  1538. switch (wValue) {
  1539. case C_HUB_LOCAL_POWER:
  1540. case C_HUB_OVER_CURRENT:
  1541. /* no hub-wide feature/status flags */
  1542. break;
  1543. default:
  1544. goto error;
  1545. }
  1546. break;
  1547. case ClearPortFeature:
  1548. if (!wIndex || wIndex > ports)
  1549. goto error;
  1550. wIndex--;
  1551. temp = isp1760_readl(status_reg);
  1552. /*
  1553. * Even if OWNER is set, so the port is owned by the
  1554. * companion controller, khubd needs to be able to clear
  1555. * the port-change status bits (especially
  1556. * USB_PORT_FEAT_C_CONNECTION).
  1557. */
  1558. switch (wValue) {
  1559. case USB_PORT_FEAT_ENABLE:
  1560. isp1760_writel(temp & ~PORT_PE, status_reg);
  1561. break;
  1562. case USB_PORT_FEAT_C_ENABLE:
  1563. /* XXX error? */
  1564. break;
  1565. case USB_PORT_FEAT_SUSPEND:
  1566. if (temp & PORT_RESET)
  1567. goto error;
  1568. if (temp & PORT_SUSPEND) {
  1569. if ((temp & PORT_PE) == 0)
  1570. goto error;
  1571. /* resume signaling for 20 msec */
  1572. temp &= ~(PORT_RWC_BITS);
  1573. isp1760_writel(temp | PORT_RESUME,
  1574. status_reg);
  1575. priv->reset_done = jiffies +
  1576. msecs_to_jiffies(20);
  1577. }
  1578. break;
  1579. case USB_PORT_FEAT_C_SUSPEND:
  1580. /* we auto-clear this feature */
  1581. break;
  1582. case USB_PORT_FEAT_POWER:
  1583. if (HCS_PPC(priv->hcs_params))
  1584. isp1760_writel(temp & ~PORT_POWER, status_reg);
  1585. break;
  1586. case USB_PORT_FEAT_C_CONNECTION:
  1587. isp1760_writel(temp | PORT_CSC,
  1588. status_reg);
  1589. break;
  1590. case USB_PORT_FEAT_C_OVER_CURRENT:
  1591. /* XXX error ?*/
  1592. break;
  1593. case USB_PORT_FEAT_C_RESET:
  1594. /* GetPortStatus clears reset */
  1595. break;
  1596. default:
  1597. goto error;
  1598. }
  1599. isp1760_readl(hcd->regs + HC_USBCMD);
  1600. break;
  1601. case GetHubDescriptor:
  1602. isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)
  1603. buf);
  1604. break;
  1605. case GetHubStatus:
  1606. /* no hub-wide feature/status flags */
  1607. memset(buf, 0, 4);
  1608. break;
  1609. case GetPortStatus:
  1610. if (!wIndex || wIndex > ports)
  1611. goto error;
  1612. wIndex--;
  1613. status = 0;
  1614. temp = isp1760_readl(status_reg);
  1615. /* wPortChange bits */
  1616. if (temp & PORT_CSC)
  1617. status |= 1 << USB_PORT_FEAT_C_CONNECTION;
  1618. /* whoever resumes must GetPortStatus to complete it!! */
  1619. if (temp & PORT_RESUME) {
  1620. printk(KERN_ERR "Port resume should be skipped.\n");
  1621. /* Remote Wakeup received? */
  1622. if (!priv->reset_done) {
  1623. /* resume signaling for 20 msec */
  1624. priv->reset_done = jiffies
  1625. + msecs_to_jiffies(20);
  1626. /* check the port again */
  1627. mod_timer(&priv_to_hcd(priv)->rh_timer,
  1628. priv->reset_done);
  1629. }
  1630. /* resume completed? */
  1631. else if (time_after_eq(jiffies,
  1632. priv->reset_done)) {
  1633. status |= 1 << USB_PORT_FEAT_C_SUSPEND;
  1634. priv->reset_done = 0;
  1635. /* stop resume signaling */
  1636. temp = isp1760_readl(status_reg);
  1637. isp1760_writel(
  1638. temp & ~(PORT_RWC_BITS | PORT_RESUME),
  1639. status_reg);
  1640. retval = handshake(priv, status_reg,
  1641. PORT_RESUME, 0, 2000 /* 2msec */);
  1642. if (retval != 0) {
  1643. isp1760_err(priv,
  1644. "port %d resume error %d\n",
  1645. wIndex + 1, retval);
  1646. goto error;
  1647. }
  1648. temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
  1649. }
  1650. }
  1651. /* whoever resets must GetPortStatus to complete it!! */
  1652. if ((temp & PORT_RESET)
  1653. && time_after_eq(jiffies,
  1654. priv->reset_done)) {
  1655. status |= 1 << USB_PORT_FEAT_C_RESET;
  1656. priv->reset_done = 0;
  1657. /* force reset to complete */
  1658. isp1760_writel(temp & ~PORT_RESET,
  1659. status_reg);
  1660. /* REVISIT: some hardware needs 550+ usec to clear
  1661. * this bit; seems too long to spin routinely...
  1662. */
  1663. retval = handshake(priv, status_reg,
  1664. PORT_RESET, 0, 750);
  1665. if (retval != 0) {
  1666. isp1760_err(priv, "port %d reset error %d\n",
  1667. wIndex + 1, retval);
  1668. goto error;
  1669. }
  1670. /* see what we found out */
  1671. temp = check_reset_complete(priv, wIndex, status_reg,
  1672. isp1760_readl(status_reg));
  1673. }
  1674. /*
  1675. * Even if OWNER is set, there's no harm letting khubd
  1676. * see the wPortStatus values (they should all be 0 except
  1677. * for PORT_POWER anyway).
  1678. */
  1679. if (temp & PORT_OWNER)
  1680. printk(KERN_ERR "Warning: PORT_OWNER is set\n");
  1681. if (temp & PORT_CONNECT) {
  1682. status |= 1 << USB_PORT_FEAT_CONNECTION;
  1683. /* status may be from integrated TT */
  1684. status |= ehci_port_speed(priv, temp);
  1685. }
  1686. if (temp & PORT_PE)
  1687. status |= 1 << USB_PORT_FEAT_ENABLE;
  1688. if (temp & (PORT_SUSPEND|PORT_RESUME))
  1689. status |= 1 << USB_PORT_FEAT_SUSPEND;
  1690. if (temp & PORT_RESET)
  1691. status |= 1 << USB_PORT_FEAT_RESET;
  1692. if (temp & PORT_POWER)
  1693. status |= 1 << USB_PORT_FEAT_POWER;
  1694. put_unaligned(cpu_to_le32(status), (__le32 *) buf);
  1695. break;
  1696. case SetHubFeature:
  1697. switch (wValue) {
  1698. case C_HUB_LOCAL_POWER:
  1699. case C_HUB_OVER_CURRENT:
  1700. /* no hub-wide feature/status flags */
  1701. break;
  1702. default:
  1703. goto error;
  1704. }
  1705. break;
  1706. case SetPortFeature:
  1707. selector = wIndex >> 8;
  1708. wIndex &= 0xff;
  1709. if (!wIndex || wIndex > ports)
  1710. goto error;
  1711. wIndex--;
  1712. temp = isp1760_readl(status_reg);
  1713. if (temp & PORT_OWNER)
  1714. break;
  1715. /* temp &= ~PORT_RWC_BITS; */
  1716. switch (wValue) {
  1717. case USB_PORT_FEAT_ENABLE:
  1718. isp1760_writel(temp | PORT_PE, status_reg);
  1719. break;
  1720. case USB_PORT_FEAT_SUSPEND:
  1721. if ((temp & PORT_PE) == 0
  1722. || (temp & PORT_RESET) != 0)
  1723. goto error;
  1724. isp1760_writel(temp | PORT_SUSPEND, status_reg);
  1725. break;
  1726. case USB_PORT_FEAT_POWER:
  1727. if (HCS_PPC(priv->hcs_params))
  1728. isp1760_writel(temp | PORT_POWER,
  1729. status_reg);
  1730. break;
  1731. case USB_PORT_FEAT_RESET:
  1732. if (temp & PORT_RESUME)
  1733. goto error;
  1734. /* line status bits may report this as low speed,
  1735. * which can be fine if this root hub has a
  1736. * transaction translator built in.
  1737. */
  1738. if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
  1739. && PORT_USB11(temp)) {
  1740. temp |= PORT_OWNER;
  1741. } else {
  1742. temp |= PORT_RESET;
  1743. temp &= ~PORT_PE;
  1744. /*
  1745. * caller must wait, then call GetPortStatus
  1746. * usb 2.0 spec says 50 ms resets on root
  1747. */
  1748. priv->reset_done = jiffies +
  1749. msecs_to_jiffies(50);
  1750. }
  1751. isp1760_writel(temp, status_reg);
  1752. break;
  1753. default:
  1754. goto error;
  1755. }
  1756. isp1760_readl(hcd->regs + HC_USBCMD);
  1757. break;
  1758. default:
  1759. error:
  1760. /* "stall" on error */
  1761. retval = -EPIPE;
  1762. }
  1763. spin_unlock_irqrestore(&priv->lock, flags);
  1764. return retval;
  1765. }
  1766. static void isp1760_endpoint_disable(struct usb_hcd *usb_hcd,
  1767. struct usb_host_endpoint *ep)
  1768. {
  1769. struct isp1760_hcd *priv = hcd_to_priv(usb_hcd);
  1770. struct isp1760_qh *qh;
  1771. struct isp1760_qtd *qtd;
  1772. unsigned long flags;
  1773. spin_lock_irqsave(&priv->lock, flags);
  1774. qh = ep->hcpriv;
  1775. if (!qh)
  1776. goto out;
  1777. ep->hcpriv = NULL;
  1778. do {
  1779. /* more than entry might get removed */
  1780. if (list_empty(&qh->qtd_list))
  1781. break;
  1782. qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd,
  1783. qtd_list);
  1784. if (qtd->status & URB_ENQUEUED) {
  1785. spin_unlock_irqrestore(&priv->lock, flags);
  1786. isp1760_urb_dequeue(usb_hcd, qtd->urb, -ECONNRESET);
  1787. spin_lock_irqsave(&priv->lock, flags);
  1788. } else {
  1789. struct urb *urb;
  1790. urb = qtd->urb;
  1791. clean_up_qtdlist(qtd);
  1792. isp1760_urb_done(priv, urb, -ECONNRESET);
  1793. }
  1794. } while (1);
  1795. qh_destroy(qh);
  1796. /* remove requests and leak them.
  1797. * ATL are pretty fast done, INT could take a while...
  1798. * The latter shoule be removed
  1799. */
  1800. out:
  1801. spin_unlock_irqrestore(&priv->lock, flags);
  1802. }
  1803. static int isp1760_get_frame(struct usb_hcd *hcd)
  1804. {
  1805. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1806. u32 fr;
  1807. fr = isp1760_readl(hcd->regs + HC_FRINDEX);
  1808. return (fr >> 3) % priv->periodic_size;
  1809. }
  1810. static void isp1760_stop(struct usb_hcd *hcd)
  1811. {
  1812. struct isp1760_hcd *priv = hcd_to_priv(hcd);
  1813. u32 temp;
  1814. isp1760_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
  1815. NULL, 0);
  1816. mdelay(20);
  1817. spin_lock_irq(&priv->lock);
  1818. ehci_reset(priv);
  1819. /* Disable IRQ */
  1820. temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
  1821. isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
  1822. spin_unlock_irq(&priv->lock);
  1823. isp1760_writel(0, hcd->regs + HC_CONFIGFLAG);
  1824. }
  1825. static void isp1760_shutdown(struct usb_hcd *hcd)
  1826. {
  1827. u32 command, temp;
  1828. isp1760_stop(hcd);
  1829. temp = isp1760_readl(hcd->regs + HC_HW_MODE_CTRL);
  1830. isp1760_writel(temp &= ~HW_GLOBAL_INTR_EN, hcd->regs + HC_HW_MODE_CTRL);
  1831. command = isp1760_readl(hcd->regs + HC_USBCMD);
  1832. command &= ~CMD_RUN;
  1833. isp1760_writel(command, hcd->regs + HC_USBCMD);
  1834. }
  1835. static const struct hc_driver isp1760_hc_driver = {
  1836. .description = "isp1760-hcd",
  1837. .product_desc = "NXP ISP1760 USB Host Controller",
  1838. .hcd_priv_size = sizeof(struct isp1760_hcd),
  1839. .irq = isp1760_irq,
  1840. .flags = HCD_MEMORY | HCD_USB2,
  1841. .reset = isp1760_hc_setup,
  1842. .start = isp1760_run,
  1843. .stop = isp1760_stop,
  1844. .shutdown = isp1760_shutdown,
  1845. .urb_enqueue = isp1760_urb_enqueue,
  1846. .urb_dequeue = isp1760_urb_dequeue,
  1847. .endpoint_disable = isp1760_endpoint_disable,
  1848. .get_frame_number = isp1760_get_frame,
  1849. .hub_status_data = isp1760_hub_status_data,
  1850. .hub_control = isp1760_hub_control,
  1851. };
  1852. int __init init_kmem_once(void)
  1853. {
  1854. qtd_cachep = kmem_cache_create("isp1760_qtd",
  1855. sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
  1856. SLAB_MEM_SPREAD, NULL);
  1857. if (!qtd_cachep)
  1858. return -ENOMEM;
  1859. qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh),
  1860. 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
  1861. if (!qh_cachep) {
  1862. kmem_cache_destroy(qtd_cachep);
  1863. return -ENOMEM;
  1864. }
  1865. return 0;
  1866. }
  1867. void deinit_kmem_cache(void)
  1868. {
  1869. kmem_cache_destroy(qtd_cachep);
  1870. kmem_cache_destroy(qh_cachep);
  1871. }
  1872. struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
  1873. int irq, unsigned long irqflags,
  1874. struct device *dev, const char *busname,
  1875. unsigned int devflags)
  1876. {
  1877. struct usb_hcd *hcd;
  1878. struct isp1760_hcd *priv;
  1879. int ret;
  1880. if (usb_disabled())
  1881. return ERR_PTR(-ENODEV);
  1882. /* prevent usb-core allocating DMA pages */
  1883. dev->dma_mask = NULL;
  1884. hcd = usb_create_hcd(&isp1760_hc_driver, dev, dev_name(dev));
  1885. if (!hcd)
  1886. return ERR_PTR(-ENOMEM);
  1887. priv = hcd_to_priv(hcd);
  1888. priv->devflags = devflags;
  1889. init_memory(priv);
  1890. hcd->regs = ioremap(res_start, res_len);
  1891. if (!hcd->regs) {
  1892. ret = -EIO;
  1893. goto err_put;
  1894. }
  1895. hcd->irq = irq;
  1896. hcd->rsrc_start = res_start;
  1897. hcd->rsrc_len = res_len;
  1898. ret = usb_add_hcd(hcd, irq, irqflags);
  1899. if (ret)
  1900. goto err_unmap;
  1901. return hcd;
  1902. err_unmap:
  1903. iounmap(hcd->regs);
  1904. err_put:
  1905. usb_put_hcd(hcd);
  1906. return ERR_PTR(ret);
  1907. }
  1908. MODULE_DESCRIPTION("Driver for the ISP1760 USB-controller from NXP");
  1909. MODULE_AUTHOR("Sebastian Siewior <bigeasy@linuxtronix.de>");
  1910. MODULE_LICENSE("GPL v2");