s3c2410_udc.c 48 KB

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  1. /*
  2. * linux/drivers/usb/gadget/s3c2410_udc.c
  3. *
  4. * Samsung S3C24xx series on-chip full speed USB device controllers
  5. *
  6. * Copyright (C) 2004-2007 Herbert Pötzl - Arnaud Patard
  7. * Additional cleanups by Ben Dooks <ben-linux@fluff.org>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. *
  23. */
  24. #include <linux/module.h>
  25. #include <linux/kernel.h>
  26. #include <linux/delay.h>
  27. #include <linux/ioport.h>
  28. #include <linux/sched.h>
  29. #include <linux/slab.h>
  30. #include <linux/smp_lock.h>
  31. #include <linux/errno.h>
  32. #include <linux/init.h>
  33. #include <linux/timer.h>
  34. #include <linux/list.h>
  35. #include <linux/interrupt.h>
  36. #include <linux/platform_device.h>
  37. #include <linux/clk.h>
  38. #include <linux/gpio.h>
  39. #include <linux/debugfs.h>
  40. #include <linux/seq_file.h>
  41. #include <linux/usb.h>
  42. #include <linux/usb/gadget.h>
  43. #include <asm/byteorder.h>
  44. #include <asm/io.h>
  45. #include <asm/irq.h>
  46. #include <asm/system.h>
  47. #include <asm/unaligned.h>
  48. #include <mach/irqs.h>
  49. #include <mach/hardware.h>
  50. #include <plat/regs-udc.h>
  51. #include <plat/udc.h>
  52. #include "s3c2410_udc.h"
  53. #define DRIVER_DESC "S3C2410 USB Device Controller Gadget"
  54. #define DRIVER_VERSION "29 Apr 2007"
  55. #define DRIVER_AUTHOR "Herbert Pötzl <herbert@13thfloor.at>, " \
  56. "Arnaud Patard <arnaud.patard@rtp-net.org>"
  57. static const char gadget_name[] = "s3c2410_udc";
  58. static const char driver_desc[] = DRIVER_DESC;
  59. static struct s3c2410_udc *the_controller;
  60. static struct clk *udc_clock;
  61. static struct clk *usb_bus_clock;
  62. static void __iomem *base_addr;
  63. static u64 rsrc_start;
  64. static u64 rsrc_len;
  65. static struct dentry *s3c2410_udc_debugfs_root;
  66. static inline u32 udc_read(u32 reg)
  67. {
  68. return readb(base_addr + reg);
  69. }
  70. static inline void udc_write(u32 value, u32 reg)
  71. {
  72. writeb(value, base_addr + reg);
  73. }
  74. static inline void udc_writeb(void __iomem *base, u32 value, u32 reg)
  75. {
  76. writeb(value, base + reg);
  77. }
  78. static struct s3c2410_udc_mach_info *udc_info;
  79. /*************************** DEBUG FUNCTION ***************************/
  80. #define DEBUG_NORMAL 1
  81. #define DEBUG_VERBOSE 2
  82. #ifdef CONFIG_USB_S3C2410_DEBUG
  83. #define USB_S3C2410_DEBUG_LEVEL 0
  84. static uint32_t s3c2410_ticks = 0;
  85. static int dprintk(int level, const char *fmt, ...)
  86. {
  87. static char printk_buf[1024];
  88. static long prevticks;
  89. static int invocation;
  90. va_list args;
  91. int len;
  92. if (level > USB_S3C2410_DEBUG_LEVEL)
  93. return 0;
  94. if (s3c2410_ticks != prevticks) {
  95. prevticks = s3c2410_ticks;
  96. invocation = 0;
  97. }
  98. len = scnprintf(printk_buf,
  99. sizeof(printk_buf), "%1lu.%02d USB: ",
  100. prevticks, invocation++);
  101. va_start(args, fmt);
  102. len = vscnprintf(printk_buf+len,
  103. sizeof(printk_buf)-len, fmt, args);
  104. va_end(args);
  105. return printk(KERN_DEBUG "%s", printk_buf);
  106. }
  107. #else
  108. static int dprintk(int level, const char *fmt, ...)
  109. {
  110. return 0;
  111. }
  112. #endif
  113. static int s3c2410_udc_debugfs_seq_show(struct seq_file *m, void *p)
  114. {
  115. u32 addr_reg,pwr_reg,ep_int_reg,usb_int_reg;
  116. u32 ep_int_en_reg, usb_int_en_reg, ep0_csr;
  117. u32 ep1_i_csr1,ep1_i_csr2,ep1_o_csr1,ep1_o_csr2;
  118. u32 ep2_i_csr1,ep2_i_csr2,ep2_o_csr1,ep2_o_csr2;
  119. addr_reg = udc_read(S3C2410_UDC_FUNC_ADDR_REG);
  120. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  121. ep_int_reg = udc_read(S3C2410_UDC_EP_INT_REG);
  122. usb_int_reg = udc_read(S3C2410_UDC_USB_INT_REG);
  123. ep_int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  124. usb_int_en_reg = udc_read(S3C2410_UDC_USB_INT_EN_REG);
  125. udc_write(0, S3C2410_UDC_INDEX_REG);
  126. ep0_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  127. udc_write(1, S3C2410_UDC_INDEX_REG);
  128. ep1_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  129. ep1_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  130. ep1_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  131. ep1_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  132. udc_write(2, S3C2410_UDC_INDEX_REG);
  133. ep2_i_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  134. ep2_i_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  135. ep2_o_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  136. ep2_o_csr2 = udc_read(S3C2410_UDC_IN_CSR2_REG);
  137. seq_printf(m, "FUNC_ADDR_REG : 0x%04X\n"
  138. "PWR_REG : 0x%04X\n"
  139. "EP_INT_REG : 0x%04X\n"
  140. "USB_INT_REG : 0x%04X\n"
  141. "EP_INT_EN_REG : 0x%04X\n"
  142. "USB_INT_EN_REG : 0x%04X\n"
  143. "EP0_CSR : 0x%04X\n"
  144. "EP1_I_CSR1 : 0x%04X\n"
  145. "EP1_I_CSR2 : 0x%04X\n"
  146. "EP1_O_CSR1 : 0x%04X\n"
  147. "EP1_O_CSR2 : 0x%04X\n"
  148. "EP2_I_CSR1 : 0x%04X\n"
  149. "EP2_I_CSR2 : 0x%04X\n"
  150. "EP2_O_CSR1 : 0x%04X\n"
  151. "EP2_O_CSR2 : 0x%04X\n",
  152. addr_reg,pwr_reg,ep_int_reg,usb_int_reg,
  153. ep_int_en_reg, usb_int_en_reg, ep0_csr,
  154. ep1_i_csr1,ep1_i_csr2,ep1_o_csr1,ep1_o_csr2,
  155. ep2_i_csr1,ep2_i_csr2,ep2_o_csr1,ep2_o_csr2
  156. );
  157. return 0;
  158. }
  159. static int s3c2410_udc_debugfs_fops_open(struct inode *inode,
  160. struct file *file)
  161. {
  162. return single_open(file, s3c2410_udc_debugfs_seq_show, NULL);
  163. }
  164. static const struct file_operations s3c2410_udc_debugfs_fops = {
  165. .open = s3c2410_udc_debugfs_fops_open,
  166. .read = seq_read,
  167. .llseek = seq_lseek,
  168. .release = single_release,
  169. .owner = THIS_MODULE,
  170. };
  171. /* io macros */
  172. static inline void s3c2410_udc_clear_ep0_opr(void __iomem *base)
  173. {
  174. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  175. udc_writeb(base, S3C2410_UDC_EP0_CSR_SOPKTRDY,
  176. S3C2410_UDC_EP0_CSR_REG);
  177. }
  178. static inline void s3c2410_udc_clear_ep0_sst(void __iomem *base)
  179. {
  180. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  181. writeb(0x00, base + S3C2410_UDC_EP0_CSR_REG);
  182. }
  183. static inline void s3c2410_udc_clear_ep0_se(void __iomem *base)
  184. {
  185. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  186. udc_writeb(base, S3C2410_UDC_EP0_CSR_SSE, S3C2410_UDC_EP0_CSR_REG);
  187. }
  188. static inline void s3c2410_udc_set_ep0_ipr(void __iomem *base)
  189. {
  190. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  191. udc_writeb(base, S3C2410_UDC_EP0_CSR_IPKRDY, S3C2410_UDC_EP0_CSR_REG);
  192. }
  193. static inline void s3c2410_udc_set_ep0_de(void __iomem *base)
  194. {
  195. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  196. udc_writeb(base, S3C2410_UDC_EP0_CSR_DE, S3C2410_UDC_EP0_CSR_REG);
  197. }
  198. inline void s3c2410_udc_set_ep0_ss(void __iomem *b)
  199. {
  200. udc_writeb(b, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  201. udc_writeb(b, S3C2410_UDC_EP0_CSR_SENDSTL, S3C2410_UDC_EP0_CSR_REG);
  202. }
  203. static inline void s3c2410_udc_set_ep0_de_out(void __iomem *base)
  204. {
  205. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  206. udc_writeb(base,(S3C2410_UDC_EP0_CSR_SOPKTRDY
  207. | S3C2410_UDC_EP0_CSR_DE),
  208. S3C2410_UDC_EP0_CSR_REG);
  209. }
  210. static inline void s3c2410_udc_set_ep0_sse_out(void __iomem *base)
  211. {
  212. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  213. udc_writeb(base, (S3C2410_UDC_EP0_CSR_SOPKTRDY
  214. | S3C2410_UDC_EP0_CSR_SSE),
  215. S3C2410_UDC_EP0_CSR_REG);
  216. }
  217. static inline void s3c2410_udc_set_ep0_de_in(void __iomem *base)
  218. {
  219. udc_writeb(base, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  220. udc_writeb(base, (S3C2410_UDC_EP0_CSR_IPKRDY
  221. | S3C2410_UDC_EP0_CSR_DE),
  222. S3C2410_UDC_EP0_CSR_REG);
  223. }
  224. /*------------------------- I/O ----------------------------------*/
  225. /*
  226. * s3c2410_udc_done
  227. */
  228. static void s3c2410_udc_done(struct s3c2410_ep *ep,
  229. struct s3c2410_request *req, int status)
  230. {
  231. unsigned halted = ep->halted;
  232. list_del_init(&req->queue);
  233. if (likely (req->req.status == -EINPROGRESS))
  234. req->req.status = status;
  235. else
  236. status = req->req.status;
  237. ep->halted = 1;
  238. req->req.complete(&ep->ep, &req->req);
  239. ep->halted = halted;
  240. }
  241. static void s3c2410_udc_nuke(struct s3c2410_udc *udc,
  242. struct s3c2410_ep *ep, int status)
  243. {
  244. /* Sanity check */
  245. if (&ep->queue == NULL)
  246. return;
  247. while (!list_empty (&ep->queue)) {
  248. struct s3c2410_request *req;
  249. req = list_entry (ep->queue.next, struct s3c2410_request,
  250. queue);
  251. s3c2410_udc_done(ep, req, status);
  252. }
  253. }
  254. static inline void s3c2410_udc_clear_ep_state(struct s3c2410_udc *dev)
  255. {
  256. unsigned i;
  257. /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
  258. * fifos, and pending transactions mustn't be continued in any case.
  259. */
  260. for (i = 1; i < S3C2410_ENDPOINTS; i++)
  261. s3c2410_udc_nuke(dev, &dev->ep[i], -ECONNABORTED);
  262. }
  263. static inline int s3c2410_udc_fifo_count_out(void)
  264. {
  265. int tmp;
  266. tmp = udc_read(S3C2410_UDC_OUT_FIFO_CNT2_REG) << 8;
  267. tmp |= udc_read(S3C2410_UDC_OUT_FIFO_CNT1_REG);
  268. return tmp;
  269. }
  270. /*
  271. * s3c2410_udc_write_packet
  272. */
  273. static inline int s3c2410_udc_write_packet(int fifo,
  274. struct s3c2410_request *req,
  275. unsigned max)
  276. {
  277. unsigned len = min(req->req.length - req->req.actual, max);
  278. u8 *buf = req->req.buf + req->req.actual;
  279. prefetch(buf);
  280. dprintk(DEBUG_VERBOSE, "%s %d %d %d %d\n", __func__,
  281. req->req.actual, req->req.length, len, req->req.actual + len);
  282. req->req.actual += len;
  283. udelay(5);
  284. writesb(base_addr + fifo, buf, len);
  285. return len;
  286. }
  287. /*
  288. * s3c2410_udc_write_fifo
  289. *
  290. * return: 0 = still running, 1 = completed, negative = errno
  291. */
  292. static int s3c2410_udc_write_fifo(struct s3c2410_ep *ep,
  293. struct s3c2410_request *req)
  294. {
  295. unsigned count;
  296. int is_last;
  297. u32 idx;
  298. int fifo_reg;
  299. u32 ep_csr;
  300. idx = ep->bEndpointAddress & 0x7F;
  301. switch (idx) {
  302. default:
  303. idx = 0;
  304. case 0:
  305. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  306. break;
  307. case 1:
  308. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  309. break;
  310. case 2:
  311. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  312. break;
  313. case 3:
  314. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  315. break;
  316. case 4:
  317. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  318. break;
  319. }
  320. count = s3c2410_udc_write_packet(fifo_reg, req, ep->ep.maxpacket);
  321. /* last packet is often short (sometimes a zlp) */
  322. if (count != ep->ep.maxpacket)
  323. is_last = 1;
  324. else if (req->req.length != req->req.actual || req->req.zero)
  325. is_last = 0;
  326. else
  327. is_last = 2;
  328. /* Only ep0 debug messages are interesting */
  329. if (idx == 0)
  330. dprintk(DEBUG_NORMAL,
  331. "Written ep%d %d.%d of %d b [last %d,z %d]\n",
  332. idx, count, req->req.actual, req->req.length,
  333. is_last, req->req.zero);
  334. if (is_last) {
  335. /* The order is important. It prevents sending 2 packets
  336. * at the same time */
  337. if (idx == 0) {
  338. /* Reset signal => no need to say 'data sent' */
  339. if (! (udc_read(S3C2410_UDC_USB_INT_REG)
  340. & S3C2410_UDC_USBINT_RESET))
  341. s3c2410_udc_set_ep0_de_in(base_addr);
  342. ep->dev->ep0state=EP0_IDLE;
  343. } else {
  344. udc_write(idx, S3C2410_UDC_INDEX_REG);
  345. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  346. udc_write(idx, S3C2410_UDC_INDEX_REG);
  347. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  348. S3C2410_UDC_IN_CSR1_REG);
  349. }
  350. s3c2410_udc_done(ep, req, 0);
  351. is_last = 1;
  352. } else {
  353. if (idx == 0) {
  354. /* Reset signal => no need to say 'data sent' */
  355. if (! (udc_read(S3C2410_UDC_USB_INT_REG)
  356. & S3C2410_UDC_USBINT_RESET))
  357. s3c2410_udc_set_ep0_ipr(base_addr);
  358. } else {
  359. udc_write(idx, S3C2410_UDC_INDEX_REG);
  360. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  361. udc_write(idx, S3C2410_UDC_INDEX_REG);
  362. udc_write(ep_csr | S3C2410_UDC_ICSR1_PKTRDY,
  363. S3C2410_UDC_IN_CSR1_REG);
  364. }
  365. }
  366. return is_last;
  367. }
  368. static inline int s3c2410_udc_read_packet(int fifo, u8 *buf,
  369. struct s3c2410_request *req, unsigned avail)
  370. {
  371. unsigned len;
  372. len = min(req->req.length - req->req.actual, avail);
  373. req->req.actual += len;
  374. readsb(fifo + base_addr, buf, len);
  375. return len;
  376. }
  377. /*
  378. * return: 0 = still running, 1 = queue empty, negative = errno
  379. */
  380. static int s3c2410_udc_read_fifo(struct s3c2410_ep *ep,
  381. struct s3c2410_request *req)
  382. {
  383. u8 *buf;
  384. u32 ep_csr;
  385. unsigned bufferspace;
  386. int is_last=1;
  387. unsigned avail;
  388. int fifo_count = 0;
  389. u32 idx;
  390. int fifo_reg;
  391. idx = ep->bEndpointAddress & 0x7F;
  392. switch (idx) {
  393. default:
  394. idx = 0;
  395. case 0:
  396. fifo_reg = S3C2410_UDC_EP0_FIFO_REG;
  397. break;
  398. case 1:
  399. fifo_reg = S3C2410_UDC_EP1_FIFO_REG;
  400. break;
  401. case 2:
  402. fifo_reg = S3C2410_UDC_EP2_FIFO_REG;
  403. break;
  404. case 3:
  405. fifo_reg = S3C2410_UDC_EP3_FIFO_REG;
  406. break;
  407. case 4:
  408. fifo_reg = S3C2410_UDC_EP4_FIFO_REG;
  409. break;
  410. }
  411. if (!req->req.length)
  412. return 1;
  413. buf = req->req.buf + req->req.actual;
  414. bufferspace = req->req.length - req->req.actual;
  415. if (!bufferspace) {
  416. dprintk(DEBUG_NORMAL, "%s: buffer full!\n", __func__);
  417. return -1;
  418. }
  419. udc_write(idx, S3C2410_UDC_INDEX_REG);
  420. fifo_count = s3c2410_udc_fifo_count_out();
  421. dprintk(DEBUG_NORMAL, "%s fifo count : %d\n", __func__, fifo_count);
  422. if (fifo_count > ep->ep.maxpacket)
  423. avail = ep->ep.maxpacket;
  424. else
  425. avail = fifo_count;
  426. fifo_count = s3c2410_udc_read_packet(fifo_reg, buf, req, avail);
  427. /* checking this with ep0 is not accurate as we already
  428. * read a control request
  429. **/
  430. if (idx != 0 && fifo_count < ep->ep.maxpacket) {
  431. is_last = 1;
  432. /* overflowed this request? flush extra data */
  433. if (fifo_count != avail)
  434. req->req.status = -EOVERFLOW;
  435. } else {
  436. is_last = (req->req.length <= req->req.actual) ? 1 : 0;
  437. }
  438. udc_write(idx, S3C2410_UDC_INDEX_REG);
  439. fifo_count = s3c2410_udc_fifo_count_out();
  440. /* Only ep0 debug messages are interesting */
  441. if (idx == 0)
  442. dprintk(DEBUG_VERBOSE, "%s fifo count : %d [last %d]\n",
  443. __func__, fifo_count,is_last);
  444. if (is_last) {
  445. if (idx == 0) {
  446. s3c2410_udc_set_ep0_de_out(base_addr);
  447. ep->dev->ep0state = EP0_IDLE;
  448. } else {
  449. udc_write(idx, S3C2410_UDC_INDEX_REG);
  450. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  451. udc_write(idx, S3C2410_UDC_INDEX_REG);
  452. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  453. S3C2410_UDC_OUT_CSR1_REG);
  454. }
  455. s3c2410_udc_done(ep, req, 0);
  456. } else {
  457. if (idx == 0) {
  458. s3c2410_udc_clear_ep0_opr(base_addr);
  459. } else {
  460. udc_write(idx, S3C2410_UDC_INDEX_REG);
  461. ep_csr = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  462. udc_write(idx, S3C2410_UDC_INDEX_REG);
  463. udc_write(ep_csr & ~S3C2410_UDC_OCSR1_PKTRDY,
  464. S3C2410_UDC_OUT_CSR1_REG);
  465. }
  466. }
  467. return is_last;
  468. }
  469. static int s3c2410_udc_read_fifo_crq(struct usb_ctrlrequest *crq)
  470. {
  471. unsigned char *outbuf = (unsigned char*)crq;
  472. int bytes_read = 0;
  473. udc_write(0, S3C2410_UDC_INDEX_REG);
  474. bytes_read = s3c2410_udc_fifo_count_out();
  475. dprintk(DEBUG_NORMAL, "%s: fifo_count=%d\n", __func__, bytes_read);
  476. if (bytes_read > sizeof(struct usb_ctrlrequest))
  477. bytes_read = sizeof(struct usb_ctrlrequest);
  478. readsb(S3C2410_UDC_EP0_FIFO_REG + base_addr, outbuf, bytes_read);
  479. dprintk(DEBUG_VERBOSE, "%s: len=%d %02x:%02x {%x,%x,%x}\n", __func__,
  480. bytes_read, crq->bRequest, crq->bRequestType,
  481. crq->wValue, crq->wIndex, crq->wLength);
  482. return bytes_read;
  483. }
  484. static int s3c2410_udc_get_status(struct s3c2410_udc *dev,
  485. struct usb_ctrlrequest *crq)
  486. {
  487. u16 status = 0;
  488. u8 ep_num = crq->wIndex & 0x7F;
  489. u8 is_in = crq->wIndex & USB_DIR_IN;
  490. switch (crq->bRequestType & USB_RECIP_MASK) {
  491. case USB_RECIP_INTERFACE:
  492. break;
  493. case USB_RECIP_DEVICE:
  494. status = dev->devstatus;
  495. break;
  496. case USB_RECIP_ENDPOINT:
  497. if (ep_num > 4 || crq->wLength > 2)
  498. return 1;
  499. if (ep_num == 0) {
  500. udc_write(0, S3C2410_UDC_INDEX_REG);
  501. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  502. status = status & S3C2410_UDC_EP0_CSR_SENDSTL;
  503. } else {
  504. udc_write(ep_num, S3C2410_UDC_INDEX_REG);
  505. if (is_in) {
  506. status = udc_read(S3C2410_UDC_IN_CSR1_REG);
  507. status = status & S3C2410_UDC_ICSR1_SENDSTL;
  508. } else {
  509. status = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  510. status = status & S3C2410_UDC_OCSR1_SENDSTL;
  511. }
  512. }
  513. status = status ? 1 : 0;
  514. break;
  515. default:
  516. return 1;
  517. }
  518. /* Seems to be needed to get it working. ouch :( */
  519. udelay(5);
  520. udc_write(status & 0xFF, S3C2410_UDC_EP0_FIFO_REG);
  521. udc_write(status >> 8, S3C2410_UDC_EP0_FIFO_REG);
  522. s3c2410_udc_set_ep0_de_in(base_addr);
  523. return 0;
  524. }
  525. /*------------------------- usb state machine -------------------------------*/
  526. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value);
  527. static void s3c2410_udc_handle_ep0_idle(struct s3c2410_udc *dev,
  528. struct s3c2410_ep *ep,
  529. struct usb_ctrlrequest *crq,
  530. u32 ep0csr)
  531. {
  532. int len, ret, tmp;
  533. /* start control request? */
  534. if (!(ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY))
  535. return;
  536. s3c2410_udc_nuke(dev, ep, -EPROTO);
  537. len = s3c2410_udc_read_fifo_crq(crq);
  538. if (len != sizeof(*crq)) {
  539. dprintk(DEBUG_NORMAL, "setup begin: fifo READ ERROR"
  540. " wanted %d bytes got %d. Stalling out...\n",
  541. sizeof(*crq), len);
  542. s3c2410_udc_set_ep0_ss(base_addr);
  543. return;
  544. }
  545. dprintk(DEBUG_NORMAL, "bRequest = %d bRequestType %d wLength = %d\n",
  546. crq->bRequest, crq->bRequestType, crq->wLength);
  547. /* cope with automagic for some standard requests. */
  548. dev->req_std = (crq->bRequestType & USB_TYPE_MASK)
  549. == USB_TYPE_STANDARD;
  550. dev->req_config = 0;
  551. dev->req_pending = 1;
  552. switch (crq->bRequest) {
  553. case USB_REQ_SET_CONFIGURATION:
  554. dprintk(DEBUG_NORMAL, "USB_REQ_SET_CONFIGURATION ... \n");
  555. if (crq->bRequestType == USB_RECIP_DEVICE) {
  556. dev->req_config = 1;
  557. s3c2410_udc_set_ep0_de_out(base_addr);
  558. }
  559. break;
  560. case USB_REQ_SET_INTERFACE:
  561. dprintk(DEBUG_NORMAL, "USB_REQ_SET_INTERFACE ... \n");
  562. if (crq->bRequestType == USB_RECIP_INTERFACE) {
  563. dev->req_config = 1;
  564. s3c2410_udc_set_ep0_de_out(base_addr);
  565. }
  566. break;
  567. case USB_REQ_SET_ADDRESS:
  568. dprintk(DEBUG_NORMAL, "USB_REQ_SET_ADDRESS ... \n");
  569. if (crq->bRequestType == USB_RECIP_DEVICE) {
  570. tmp = crq->wValue & 0x7F;
  571. dev->address = tmp;
  572. udc_write((tmp | S3C2410_UDC_FUNCADDR_UPDATE),
  573. S3C2410_UDC_FUNC_ADDR_REG);
  574. s3c2410_udc_set_ep0_de_out(base_addr);
  575. return;
  576. }
  577. break;
  578. case USB_REQ_GET_STATUS:
  579. dprintk(DEBUG_NORMAL, "USB_REQ_GET_STATUS ... \n");
  580. s3c2410_udc_clear_ep0_opr(base_addr);
  581. if (dev->req_std) {
  582. if (!s3c2410_udc_get_status(dev, crq)) {
  583. return;
  584. }
  585. }
  586. break;
  587. case USB_REQ_CLEAR_FEATURE:
  588. s3c2410_udc_clear_ep0_opr(base_addr);
  589. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  590. break;
  591. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  592. break;
  593. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 0);
  594. s3c2410_udc_set_ep0_de_out(base_addr);
  595. return;
  596. case USB_REQ_SET_FEATURE:
  597. s3c2410_udc_clear_ep0_opr(base_addr);
  598. if (crq->bRequestType != USB_RECIP_ENDPOINT)
  599. break;
  600. if (crq->wValue != USB_ENDPOINT_HALT || crq->wLength != 0)
  601. break;
  602. s3c2410_udc_set_halt(&dev->ep[crq->wIndex & 0x7f].ep, 1);
  603. s3c2410_udc_set_ep0_de_out(base_addr);
  604. return;
  605. default:
  606. s3c2410_udc_clear_ep0_opr(base_addr);
  607. break;
  608. }
  609. if (crq->bRequestType & USB_DIR_IN)
  610. dev->ep0state = EP0_IN_DATA_PHASE;
  611. else
  612. dev->ep0state = EP0_OUT_DATA_PHASE;
  613. ret = dev->driver->setup(&dev->gadget, crq);
  614. if (ret < 0) {
  615. if (dev->req_config) {
  616. dprintk(DEBUG_NORMAL, "config change %02x fail %d?\n",
  617. crq->bRequest, ret);
  618. return;
  619. }
  620. if (ret == -EOPNOTSUPP)
  621. dprintk(DEBUG_NORMAL, "Operation not supported\n");
  622. else
  623. dprintk(DEBUG_NORMAL,
  624. "dev->driver->setup failed. (%d)\n", ret);
  625. udelay(5);
  626. s3c2410_udc_set_ep0_ss(base_addr);
  627. s3c2410_udc_set_ep0_de_out(base_addr);
  628. dev->ep0state = EP0_IDLE;
  629. /* deferred i/o == no response yet */
  630. } else if (dev->req_pending) {
  631. dprintk(DEBUG_VERBOSE, "dev->req_pending... what now?\n");
  632. dev->req_pending=0;
  633. }
  634. dprintk(DEBUG_VERBOSE, "ep0state %s\n", ep0states[dev->ep0state]);
  635. }
  636. static void s3c2410_udc_handle_ep0(struct s3c2410_udc *dev)
  637. {
  638. u32 ep0csr;
  639. struct s3c2410_ep *ep = &dev->ep[0];
  640. struct s3c2410_request *req;
  641. struct usb_ctrlrequest crq;
  642. if (list_empty(&ep->queue))
  643. req = NULL;
  644. else
  645. req = list_entry(ep->queue.next, struct s3c2410_request, queue);
  646. /* We make the assumption that S3C2410_UDC_IN_CSR1_REG equal to
  647. * S3C2410_UDC_EP0_CSR_REG when index is zero */
  648. udc_write(0, S3C2410_UDC_INDEX_REG);
  649. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  650. dprintk(DEBUG_NORMAL, "ep0csr %x ep0state %s\n",
  651. ep0csr, ep0states[dev->ep0state]);
  652. /* clear stall status */
  653. if (ep0csr & S3C2410_UDC_EP0_CSR_SENTSTL) {
  654. s3c2410_udc_nuke(dev, ep, -EPIPE);
  655. dprintk(DEBUG_NORMAL, "... clear SENT_STALL ...\n");
  656. s3c2410_udc_clear_ep0_sst(base_addr);
  657. dev->ep0state = EP0_IDLE;
  658. return;
  659. }
  660. /* clear setup end */
  661. if (ep0csr & S3C2410_UDC_EP0_CSR_SE) {
  662. dprintk(DEBUG_NORMAL, "... serviced SETUP_END ...\n");
  663. s3c2410_udc_nuke(dev, ep, 0);
  664. s3c2410_udc_clear_ep0_se(base_addr);
  665. dev->ep0state = EP0_IDLE;
  666. }
  667. switch (dev->ep0state) {
  668. case EP0_IDLE:
  669. s3c2410_udc_handle_ep0_idle(dev, ep, &crq, ep0csr);
  670. break;
  671. case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
  672. dprintk(DEBUG_NORMAL, "EP0_IN_DATA_PHASE ... what now?\n");
  673. if (!(ep0csr & S3C2410_UDC_EP0_CSR_IPKRDY) && req) {
  674. s3c2410_udc_write_fifo(ep, req);
  675. }
  676. break;
  677. case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
  678. dprintk(DEBUG_NORMAL, "EP0_OUT_DATA_PHASE ... what now?\n");
  679. if ((ep0csr & S3C2410_UDC_EP0_CSR_OPKRDY) && req ) {
  680. s3c2410_udc_read_fifo(ep,req);
  681. }
  682. break;
  683. case EP0_END_XFER:
  684. dprintk(DEBUG_NORMAL, "EP0_END_XFER ... what now?\n");
  685. dev->ep0state = EP0_IDLE;
  686. break;
  687. case EP0_STALL:
  688. dprintk(DEBUG_NORMAL, "EP0_STALL ... what now?\n");
  689. dev->ep0state = EP0_IDLE;
  690. break;
  691. }
  692. }
  693. /*
  694. * handle_ep - Manage I/O endpoints
  695. */
  696. static void s3c2410_udc_handle_ep(struct s3c2410_ep *ep)
  697. {
  698. struct s3c2410_request *req;
  699. int is_in = ep->bEndpointAddress & USB_DIR_IN;
  700. u32 ep_csr1;
  701. u32 idx;
  702. if (likely (!list_empty(&ep->queue)))
  703. req = list_entry(ep->queue.next,
  704. struct s3c2410_request, queue);
  705. else
  706. req = NULL;
  707. idx = ep->bEndpointAddress & 0x7F;
  708. if (is_in) {
  709. udc_write(idx, S3C2410_UDC_INDEX_REG);
  710. ep_csr1 = udc_read(S3C2410_UDC_IN_CSR1_REG);
  711. dprintk(DEBUG_VERBOSE, "ep%01d write csr:%02x %d\n",
  712. idx, ep_csr1, req ? 1 : 0);
  713. if (ep_csr1 & S3C2410_UDC_ICSR1_SENTSTL) {
  714. dprintk(DEBUG_VERBOSE, "st\n");
  715. udc_write(idx, S3C2410_UDC_INDEX_REG);
  716. udc_write(ep_csr1 & ~S3C2410_UDC_ICSR1_SENTSTL,
  717. S3C2410_UDC_IN_CSR1_REG);
  718. return;
  719. }
  720. if (!(ep_csr1 & S3C2410_UDC_ICSR1_PKTRDY) && req) {
  721. s3c2410_udc_write_fifo(ep,req);
  722. }
  723. } else {
  724. udc_write(idx, S3C2410_UDC_INDEX_REG);
  725. ep_csr1 = udc_read(S3C2410_UDC_OUT_CSR1_REG);
  726. dprintk(DEBUG_VERBOSE, "ep%01d rd csr:%02x\n", idx, ep_csr1);
  727. if (ep_csr1 & S3C2410_UDC_OCSR1_SENTSTL) {
  728. udc_write(idx, S3C2410_UDC_INDEX_REG);
  729. udc_write(ep_csr1 & ~S3C2410_UDC_OCSR1_SENTSTL,
  730. S3C2410_UDC_OUT_CSR1_REG);
  731. return;
  732. }
  733. if ((ep_csr1 & S3C2410_UDC_OCSR1_PKTRDY) && req) {
  734. s3c2410_udc_read_fifo(ep,req);
  735. }
  736. }
  737. }
  738. #include <mach/regs-irq.h>
  739. /*
  740. * s3c2410_udc_irq - interrupt handler
  741. */
  742. static irqreturn_t s3c2410_udc_irq(int dummy, void *_dev)
  743. {
  744. struct s3c2410_udc *dev = _dev;
  745. int usb_status;
  746. int usbd_status;
  747. int pwr_reg;
  748. int ep0csr;
  749. int i;
  750. u32 idx;
  751. unsigned long flags;
  752. spin_lock_irqsave(&dev->lock, flags);
  753. /* Driver connected ? */
  754. if (!dev->driver) {
  755. /* Clear interrupts */
  756. udc_write(udc_read(S3C2410_UDC_USB_INT_REG),
  757. S3C2410_UDC_USB_INT_REG);
  758. udc_write(udc_read(S3C2410_UDC_EP_INT_REG),
  759. S3C2410_UDC_EP_INT_REG);
  760. }
  761. /* Save index */
  762. idx = udc_read(S3C2410_UDC_INDEX_REG);
  763. /* Read status registers */
  764. usb_status = udc_read(S3C2410_UDC_USB_INT_REG);
  765. usbd_status = udc_read(S3C2410_UDC_EP_INT_REG);
  766. pwr_reg = udc_read(S3C2410_UDC_PWR_REG);
  767. udc_writeb(base_addr, S3C2410_UDC_INDEX_EP0, S3C2410_UDC_INDEX_REG);
  768. ep0csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  769. dprintk(DEBUG_NORMAL, "usbs=%02x, usbds=%02x, pwr=%02x ep0csr=%02x\n",
  770. usb_status, usbd_status, pwr_reg, ep0csr);
  771. /*
  772. * Now, handle interrupts. There's two types :
  773. * - Reset, Resume, Suspend coming -> usb_int_reg
  774. * - EP -> ep_int_reg
  775. */
  776. /* RESET */
  777. if (usb_status & S3C2410_UDC_USBINT_RESET) {
  778. /* two kind of reset :
  779. * - reset start -> pwr reg = 8
  780. * - reset end -> pwr reg = 0
  781. **/
  782. dprintk(DEBUG_NORMAL, "USB reset csr %x pwr %x\n",
  783. ep0csr, pwr_reg);
  784. dev->gadget.speed = USB_SPEED_UNKNOWN;
  785. udc_write(0x00, S3C2410_UDC_INDEX_REG);
  786. udc_write((dev->ep[0].ep.maxpacket & 0x7ff) >> 3,
  787. S3C2410_UDC_MAXP_REG);
  788. dev->address = 0;
  789. dev->ep0state = EP0_IDLE;
  790. dev->gadget.speed = USB_SPEED_FULL;
  791. /* clear interrupt */
  792. udc_write(S3C2410_UDC_USBINT_RESET,
  793. S3C2410_UDC_USB_INT_REG);
  794. udc_write(idx, S3C2410_UDC_INDEX_REG);
  795. spin_unlock_irqrestore(&dev->lock, flags);
  796. return IRQ_HANDLED;
  797. }
  798. /* RESUME */
  799. if (usb_status & S3C2410_UDC_USBINT_RESUME) {
  800. dprintk(DEBUG_NORMAL, "USB resume\n");
  801. /* clear interrupt */
  802. udc_write(S3C2410_UDC_USBINT_RESUME,
  803. S3C2410_UDC_USB_INT_REG);
  804. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  805. && dev->driver
  806. && dev->driver->resume)
  807. dev->driver->resume(&dev->gadget);
  808. }
  809. /* SUSPEND */
  810. if (usb_status & S3C2410_UDC_USBINT_SUSPEND) {
  811. dprintk(DEBUG_NORMAL, "USB suspend\n");
  812. /* clear interrupt */
  813. udc_write(S3C2410_UDC_USBINT_SUSPEND,
  814. S3C2410_UDC_USB_INT_REG);
  815. if (dev->gadget.speed != USB_SPEED_UNKNOWN
  816. && dev->driver
  817. && dev->driver->suspend)
  818. dev->driver->suspend(&dev->gadget);
  819. dev->ep0state = EP0_IDLE;
  820. }
  821. /* EP */
  822. /* control traffic */
  823. /* check on ep0csr != 0 is not a good idea as clearing in_pkt_ready
  824. * generate an interrupt
  825. */
  826. if (usbd_status & S3C2410_UDC_INT_EP0) {
  827. dprintk(DEBUG_VERBOSE, "USB ep0 irq\n");
  828. /* Clear the interrupt bit by setting it to 1 */
  829. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_REG);
  830. s3c2410_udc_handle_ep0(dev);
  831. }
  832. /* endpoint data transfers */
  833. for (i = 1; i < S3C2410_ENDPOINTS; i++) {
  834. u32 tmp = 1 << i;
  835. if (usbd_status & tmp) {
  836. dprintk(DEBUG_VERBOSE, "USB ep%d irq\n", i);
  837. /* Clear the interrupt bit by setting it to 1 */
  838. udc_write(tmp, S3C2410_UDC_EP_INT_REG);
  839. s3c2410_udc_handle_ep(&dev->ep[i]);
  840. }
  841. }
  842. dprintk(DEBUG_VERBOSE, "irq: %d s3c2410_udc_done.\n", IRQ_USBD);
  843. /* Restore old index */
  844. udc_write(idx, S3C2410_UDC_INDEX_REG);
  845. spin_unlock_irqrestore(&dev->lock, flags);
  846. return IRQ_HANDLED;
  847. }
  848. /*------------------------- s3c2410_ep_ops ----------------------------------*/
  849. static inline struct s3c2410_ep *to_s3c2410_ep(struct usb_ep *ep)
  850. {
  851. return container_of(ep, struct s3c2410_ep, ep);
  852. }
  853. static inline struct s3c2410_udc *to_s3c2410_udc(struct usb_gadget *gadget)
  854. {
  855. return container_of(gadget, struct s3c2410_udc, gadget);
  856. }
  857. static inline struct s3c2410_request *to_s3c2410_req(struct usb_request *req)
  858. {
  859. return container_of(req, struct s3c2410_request, req);
  860. }
  861. /*
  862. * s3c2410_udc_ep_enable
  863. */
  864. static int s3c2410_udc_ep_enable(struct usb_ep *_ep,
  865. const struct usb_endpoint_descriptor *desc)
  866. {
  867. struct s3c2410_udc *dev;
  868. struct s3c2410_ep *ep;
  869. u32 max, tmp;
  870. unsigned long flags;
  871. u32 csr1,csr2;
  872. u32 int_en_reg;
  873. ep = to_s3c2410_ep(_ep);
  874. if (!_ep || !desc || ep->desc
  875. || _ep->name == ep0name
  876. || desc->bDescriptorType != USB_DT_ENDPOINT)
  877. return -EINVAL;
  878. dev = ep->dev;
  879. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  880. return -ESHUTDOWN;
  881. max = le16_to_cpu(desc->wMaxPacketSize) & 0x1fff;
  882. local_irq_save (flags);
  883. _ep->maxpacket = max & 0x7ff;
  884. ep->desc = desc;
  885. ep->halted = 0;
  886. ep->bEndpointAddress = desc->bEndpointAddress;
  887. /* set max packet */
  888. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  889. udc_write(max >> 3, S3C2410_UDC_MAXP_REG);
  890. /* set type, direction, address; reset fifo counters */
  891. if (desc->bEndpointAddress & USB_DIR_IN) {
  892. csr1 = S3C2410_UDC_ICSR1_FFLUSH|S3C2410_UDC_ICSR1_CLRDT;
  893. csr2 = S3C2410_UDC_ICSR2_MODEIN|S3C2410_UDC_ICSR2_DMAIEN;
  894. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  895. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  896. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  897. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  898. } else {
  899. /* don't flush in fifo or it will cause endpoint interrupt */
  900. csr1 = S3C2410_UDC_ICSR1_CLRDT;
  901. csr2 = S3C2410_UDC_ICSR2_DMAIEN;
  902. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  903. udc_write(csr1, S3C2410_UDC_IN_CSR1_REG);
  904. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  905. udc_write(csr2, S3C2410_UDC_IN_CSR2_REG);
  906. csr1 = S3C2410_UDC_OCSR1_FFLUSH | S3C2410_UDC_OCSR1_CLRDT;
  907. csr2 = S3C2410_UDC_OCSR2_DMAIEN;
  908. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  909. udc_write(csr1, S3C2410_UDC_OUT_CSR1_REG);
  910. udc_write(ep->num, S3C2410_UDC_INDEX_REG);
  911. udc_write(csr2, S3C2410_UDC_OUT_CSR2_REG);
  912. }
  913. /* enable irqs */
  914. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  915. udc_write(int_en_reg | (1 << ep->num), S3C2410_UDC_EP_INT_EN_REG);
  916. /* print some debug message */
  917. tmp = desc->bEndpointAddress;
  918. dprintk (DEBUG_NORMAL, "enable %s(%d) ep%x%s-blk max %02x\n",
  919. _ep->name,ep->num, tmp,
  920. desc->bEndpointAddress & USB_DIR_IN ? "in" : "out", max);
  921. local_irq_restore (flags);
  922. s3c2410_udc_set_halt(_ep, 0);
  923. return 0;
  924. }
  925. /*
  926. * s3c2410_udc_ep_disable
  927. */
  928. static int s3c2410_udc_ep_disable(struct usb_ep *_ep)
  929. {
  930. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  931. unsigned long flags;
  932. u32 int_en_reg;
  933. if (!_ep || !ep->desc) {
  934. dprintk(DEBUG_NORMAL, "%s not enabled\n",
  935. _ep ? ep->ep.name : NULL);
  936. return -EINVAL;
  937. }
  938. local_irq_save(flags);
  939. dprintk(DEBUG_NORMAL, "ep_disable: %s\n", _ep->name);
  940. ep->desc = NULL;
  941. ep->halted = 1;
  942. s3c2410_udc_nuke (ep->dev, ep, -ESHUTDOWN);
  943. /* disable irqs */
  944. int_en_reg = udc_read(S3C2410_UDC_EP_INT_EN_REG);
  945. udc_write(int_en_reg & ~(1<<ep->num), S3C2410_UDC_EP_INT_EN_REG);
  946. local_irq_restore(flags);
  947. dprintk(DEBUG_NORMAL, "%s disabled\n", _ep->name);
  948. return 0;
  949. }
  950. /*
  951. * s3c2410_udc_alloc_request
  952. */
  953. static struct usb_request *
  954. s3c2410_udc_alloc_request(struct usb_ep *_ep, gfp_t mem_flags)
  955. {
  956. struct s3c2410_request *req;
  957. dprintk(DEBUG_VERBOSE,"%s(%p,%d)\n", __func__, _ep, mem_flags);
  958. if (!_ep)
  959. return NULL;
  960. req = kzalloc (sizeof(struct s3c2410_request), mem_flags);
  961. if (!req)
  962. return NULL;
  963. INIT_LIST_HEAD (&req->queue);
  964. return &req->req;
  965. }
  966. /*
  967. * s3c2410_udc_free_request
  968. */
  969. static void
  970. s3c2410_udc_free_request(struct usb_ep *_ep, struct usb_request *_req)
  971. {
  972. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  973. struct s3c2410_request *req = to_s3c2410_req(_req);
  974. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  975. if (!ep || !_req || (!ep->desc && _ep->name != ep0name))
  976. return;
  977. WARN_ON (!list_empty (&req->queue));
  978. kfree(req);
  979. }
  980. /*
  981. * s3c2410_udc_queue
  982. */
  983. static int s3c2410_udc_queue(struct usb_ep *_ep, struct usb_request *_req,
  984. gfp_t gfp_flags)
  985. {
  986. struct s3c2410_request *req = to_s3c2410_req(_req);
  987. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  988. struct s3c2410_udc *dev;
  989. u32 ep_csr = 0;
  990. int fifo_count = 0;
  991. unsigned long flags;
  992. if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  993. dprintk(DEBUG_NORMAL, "%s: invalid args\n", __func__);
  994. return -EINVAL;
  995. }
  996. dev = ep->dev;
  997. if (unlikely (!dev->driver
  998. || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
  999. return -ESHUTDOWN;
  1000. }
  1001. local_irq_save (flags);
  1002. if (unlikely(!_req || !_req->complete
  1003. || !_req->buf || !list_empty(&req->queue))) {
  1004. if (!_req)
  1005. dprintk(DEBUG_NORMAL, "%s: 1 X X X\n", __func__);
  1006. else {
  1007. dprintk(DEBUG_NORMAL, "%s: 0 %01d %01d %01d\n",
  1008. __func__, !_req->complete,!_req->buf,
  1009. !list_empty(&req->queue));
  1010. }
  1011. local_irq_restore(flags);
  1012. return -EINVAL;
  1013. }
  1014. _req->status = -EINPROGRESS;
  1015. _req->actual = 0;
  1016. dprintk(DEBUG_VERBOSE, "%s: ep%x len %d\n",
  1017. __func__, ep->bEndpointAddress, _req->length);
  1018. if (ep->bEndpointAddress) {
  1019. udc_write(ep->bEndpointAddress & 0x7F, S3C2410_UDC_INDEX_REG);
  1020. ep_csr = udc_read((ep->bEndpointAddress & USB_DIR_IN)
  1021. ? S3C2410_UDC_IN_CSR1_REG
  1022. : S3C2410_UDC_OUT_CSR1_REG);
  1023. fifo_count = s3c2410_udc_fifo_count_out();
  1024. } else {
  1025. udc_write(0, S3C2410_UDC_INDEX_REG);
  1026. ep_csr = udc_read(S3C2410_UDC_IN_CSR1_REG);
  1027. fifo_count = s3c2410_udc_fifo_count_out();
  1028. }
  1029. /* kickstart this i/o queue? */
  1030. if (list_empty(&ep->queue) && !ep->halted) {
  1031. if (ep->bEndpointAddress == 0 /* ep0 */) {
  1032. switch (dev->ep0state) {
  1033. case EP0_IN_DATA_PHASE:
  1034. if (!(ep_csr&S3C2410_UDC_EP0_CSR_IPKRDY)
  1035. && s3c2410_udc_write_fifo(ep,
  1036. req)) {
  1037. dev->ep0state = EP0_IDLE;
  1038. req = NULL;
  1039. }
  1040. break;
  1041. case EP0_OUT_DATA_PHASE:
  1042. if ((!_req->length)
  1043. || ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1044. && s3c2410_udc_read_fifo(ep,
  1045. req))) {
  1046. dev->ep0state = EP0_IDLE;
  1047. req = NULL;
  1048. }
  1049. break;
  1050. default:
  1051. local_irq_restore(flags);
  1052. return -EL2HLT;
  1053. }
  1054. } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0
  1055. && (!(ep_csr&S3C2410_UDC_OCSR1_PKTRDY))
  1056. && s3c2410_udc_write_fifo(ep, req)) {
  1057. req = NULL;
  1058. } else if ((ep_csr & S3C2410_UDC_OCSR1_PKTRDY)
  1059. && fifo_count
  1060. && s3c2410_udc_read_fifo(ep, req)) {
  1061. req = NULL;
  1062. }
  1063. }
  1064. /* pio or dma irq handler advances the queue. */
  1065. if (likely (req != 0))
  1066. list_add_tail(&req->queue, &ep->queue);
  1067. local_irq_restore(flags);
  1068. dprintk(DEBUG_VERBOSE, "%s ok\n", __func__);
  1069. return 0;
  1070. }
  1071. /*
  1072. * s3c2410_udc_dequeue
  1073. */
  1074. static int s3c2410_udc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1075. {
  1076. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1077. struct s3c2410_udc *udc;
  1078. int retval = -EINVAL;
  1079. unsigned long flags;
  1080. struct s3c2410_request *req = NULL;
  1081. dprintk(DEBUG_VERBOSE, "%s(%p,%p)\n", __func__, _ep, _req);
  1082. if (!the_controller->driver)
  1083. return -ESHUTDOWN;
  1084. if (!_ep || !_req)
  1085. return retval;
  1086. udc = to_s3c2410_udc(ep->gadget);
  1087. local_irq_save (flags);
  1088. list_for_each_entry (req, &ep->queue, queue) {
  1089. if (&req->req == _req) {
  1090. list_del_init (&req->queue);
  1091. _req->status = -ECONNRESET;
  1092. retval = 0;
  1093. break;
  1094. }
  1095. }
  1096. if (retval == 0) {
  1097. dprintk(DEBUG_VERBOSE,
  1098. "dequeued req %p from %s, len %d buf %p\n",
  1099. req, _ep->name, _req->length, _req->buf);
  1100. s3c2410_udc_done(ep, req, -ECONNRESET);
  1101. }
  1102. local_irq_restore (flags);
  1103. return retval;
  1104. }
  1105. /*
  1106. * s3c2410_udc_set_halt
  1107. */
  1108. static int s3c2410_udc_set_halt(struct usb_ep *_ep, int value)
  1109. {
  1110. struct s3c2410_ep *ep = to_s3c2410_ep(_ep);
  1111. u32 ep_csr = 0;
  1112. unsigned long flags;
  1113. u32 idx;
  1114. if (unlikely (!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  1115. dprintk(DEBUG_NORMAL, "%s: inval 2\n", __func__);
  1116. return -EINVAL;
  1117. }
  1118. local_irq_save (flags);
  1119. idx = ep->bEndpointAddress & 0x7F;
  1120. if (idx == 0) {
  1121. s3c2410_udc_set_ep0_ss(base_addr);
  1122. s3c2410_udc_set_ep0_de_out(base_addr);
  1123. } else {
  1124. udc_write(idx, S3C2410_UDC_INDEX_REG);
  1125. ep_csr = udc_read((ep->bEndpointAddress &USB_DIR_IN)
  1126. ? S3C2410_UDC_IN_CSR1_REG
  1127. : S3C2410_UDC_OUT_CSR1_REG);
  1128. if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
  1129. if (value)
  1130. udc_write(ep_csr | S3C2410_UDC_ICSR1_SENDSTL,
  1131. S3C2410_UDC_IN_CSR1_REG);
  1132. else {
  1133. ep_csr &= ~S3C2410_UDC_ICSR1_SENDSTL;
  1134. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1135. ep_csr |= S3C2410_UDC_ICSR1_CLRDT;
  1136. udc_write(ep_csr, S3C2410_UDC_IN_CSR1_REG);
  1137. }
  1138. } else {
  1139. if (value)
  1140. udc_write(ep_csr | S3C2410_UDC_OCSR1_SENDSTL,
  1141. S3C2410_UDC_OUT_CSR1_REG);
  1142. else {
  1143. ep_csr &= ~S3C2410_UDC_OCSR1_SENDSTL;
  1144. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1145. ep_csr |= S3C2410_UDC_OCSR1_CLRDT;
  1146. udc_write(ep_csr, S3C2410_UDC_OUT_CSR1_REG);
  1147. }
  1148. }
  1149. }
  1150. ep->halted = value ? 1 : 0;
  1151. local_irq_restore (flags);
  1152. return 0;
  1153. }
  1154. static const struct usb_ep_ops s3c2410_ep_ops = {
  1155. .enable = s3c2410_udc_ep_enable,
  1156. .disable = s3c2410_udc_ep_disable,
  1157. .alloc_request = s3c2410_udc_alloc_request,
  1158. .free_request = s3c2410_udc_free_request,
  1159. .queue = s3c2410_udc_queue,
  1160. .dequeue = s3c2410_udc_dequeue,
  1161. .set_halt = s3c2410_udc_set_halt,
  1162. };
  1163. /*------------------------- usb_gadget_ops ----------------------------------*/
  1164. /*
  1165. * s3c2410_udc_get_frame
  1166. */
  1167. static int s3c2410_udc_get_frame(struct usb_gadget *_gadget)
  1168. {
  1169. int tmp;
  1170. dprintk(DEBUG_VERBOSE, "%s()\n", __func__);
  1171. tmp = udc_read(S3C2410_UDC_FRAME_NUM2_REG) << 8;
  1172. tmp |= udc_read(S3C2410_UDC_FRAME_NUM1_REG);
  1173. return tmp;
  1174. }
  1175. /*
  1176. * s3c2410_udc_wakeup
  1177. */
  1178. static int s3c2410_udc_wakeup(struct usb_gadget *_gadget)
  1179. {
  1180. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1181. return 0;
  1182. }
  1183. /*
  1184. * s3c2410_udc_set_selfpowered
  1185. */
  1186. static int s3c2410_udc_set_selfpowered(struct usb_gadget *gadget, int value)
  1187. {
  1188. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1189. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1190. if (value)
  1191. udc->devstatus |= (1 << USB_DEVICE_SELF_POWERED);
  1192. else
  1193. udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
  1194. return 0;
  1195. }
  1196. static void s3c2410_udc_disable(struct s3c2410_udc *dev);
  1197. static void s3c2410_udc_enable(struct s3c2410_udc *dev);
  1198. static int s3c2410_udc_set_pullup(struct s3c2410_udc *udc, int is_on)
  1199. {
  1200. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1201. if (udc_info && udc_info->udc_command) {
  1202. if (is_on)
  1203. s3c2410_udc_enable(udc);
  1204. else {
  1205. if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
  1206. if (udc->driver && udc->driver->disconnect)
  1207. udc->driver->disconnect(&udc->gadget);
  1208. }
  1209. s3c2410_udc_disable(udc);
  1210. }
  1211. }
  1212. else
  1213. return -EOPNOTSUPP;
  1214. return 0;
  1215. }
  1216. static int s3c2410_udc_vbus_session(struct usb_gadget *gadget, int is_active)
  1217. {
  1218. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1219. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1220. udc->vbus = (is_active != 0);
  1221. s3c2410_udc_set_pullup(udc, is_active);
  1222. return 0;
  1223. }
  1224. static int s3c2410_udc_pullup(struct usb_gadget *gadget, int is_on)
  1225. {
  1226. struct s3c2410_udc *udc = to_s3c2410_udc(gadget);
  1227. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1228. s3c2410_udc_set_pullup(udc, is_on ? 0 : 1);
  1229. return 0;
  1230. }
  1231. static irqreturn_t s3c2410_udc_vbus_irq(int irq, void *_dev)
  1232. {
  1233. struct s3c2410_udc *dev = _dev;
  1234. unsigned int value;
  1235. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1236. value = gpio_get_value(udc_info->vbus_pin) ? 1 : 0;
  1237. if (udc_info->vbus_pin_inverted)
  1238. value = !value;
  1239. if (value != dev->vbus)
  1240. s3c2410_udc_vbus_session(&dev->gadget, value);
  1241. return IRQ_HANDLED;
  1242. }
  1243. static int s3c2410_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1244. {
  1245. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1246. if (udc_info && udc_info->vbus_draw) {
  1247. udc_info->vbus_draw(ma);
  1248. return 0;
  1249. }
  1250. return -ENOTSUPP;
  1251. }
  1252. static const struct usb_gadget_ops s3c2410_ops = {
  1253. .get_frame = s3c2410_udc_get_frame,
  1254. .wakeup = s3c2410_udc_wakeup,
  1255. .set_selfpowered = s3c2410_udc_set_selfpowered,
  1256. .pullup = s3c2410_udc_pullup,
  1257. .vbus_session = s3c2410_udc_vbus_session,
  1258. .vbus_draw = s3c2410_vbus_draw,
  1259. };
  1260. /*------------------------- gadget driver handling---------------------------*/
  1261. /*
  1262. * s3c2410_udc_disable
  1263. */
  1264. static void s3c2410_udc_disable(struct s3c2410_udc *dev)
  1265. {
  1266. dprintk(DEBUG_NORMAL, "%s()\n", __func__);
  1267. /* Disable all interrupts */
  1268. udc_write(0x00, S3C2410_UDC_USB_INT_EN_REG);
  1269. udc_write(0x00, S3C2410_UDC_EP_INT_EN_REG);
  1270. /* Clear the interrupt registers */
  1271. udc_write(S3C2410_UDC_USBINT_RESET
  1272. | S3C2410_UDC_USBINT_RESUME
  1273. | S3C2410_UDC_USBINT_SUSPEND,
  1274. S3C2410_UDC_USB_INT_REG);
  1275. udc_write(0x1F, S3C2410_UDC_EP_INT_REG);
  1276. /* Good bye, cruel world */
  1277. if (udc_info && udc_info->udc_command)
  1278. udc_info->udc_command(S3C2410_UDC_P_DISABLE);
  1279. /* Set speed to unknown */
  1280. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1281. }
  1282. /*
  1283. * s3c2410_udc_reinit
  1284. */
  1285. static void s3c2410_udc_reinit(struct s3c2410_udc *dev)
  1286. {
  1287. u32 i;
  1288. /* device/ep0 records init */
  1289. INIT_LIST_HEAD (&dev->gadget.ep_list);
  1290. INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
  1291. dev->ep0state = EP0_IDLE;
  1292. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1293. struct s3c2410_ep *ep = &dev->ep[i];
  1294. if (i != 0)
  1295. list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
  1296. ep->dev = dev;
  1297. ep->desc = NULL;
  1298. ep->halted = 0;
  1299. INIT_LIST_HEAD (&ep->queue);
  1300. }
  1301. }
  1302. /*
  1303. * s3c2410_udc_enable
  1304. */
  1305. static void s3c2410_udc_enable(struct s3c2410_udc *dev)
  1306. {
  1307. int i;
  1308. dprintk(DEBUG_NORMAL, "s3c2410_udc_enable called\n");
  1309. /* dev->gadget.speed = USB_SPEED_UNKNOWN; */
  1310. dev->gadget.speed = USB_SPEED_FULL;
  1311. /* Set MAXP for all endpoints */
  1312. for (i = 0; i < S3C2410_ENDPOINTS; i++) {
  1313. udc_write(i, S3C2410_UDC_INDEX_REG);
  1314. udc_write((dev->ep[i].ep.maxpacket & 0x7ff) >> 3,
  1315. S3C2410_UDC_MAXP_REG);
  1316. }
  1317. /* Set default power state */
  1318. udc_write(DEFAULT_POWER_STATE, S3C2410_UDC_PWR_REG);
  1319. /* Enable reset and suspend interrupt interrupts */
  1320. udc_write(S3C2410_UDC_USBINT_RESET | S3C2410_UDC_USBINT_SUSPEND,
  1321. S3C2410_UDC_USB_INT_EN_REG);
  1322. /* Enable ep0 interrupt */
  1323. udc_write(S3C2410_UDC_INT_EP0, S3C2410_UDC_EP_INT_EN_REG);
  1324. /* time to say "hello, world" */
  1325. if (udc_info && udc_info->udc_command)
  1326. udc_info->udc_command(S3C2410_UDC_P_ENABLE);
  1327. }
  1328. /*
  1329. * usb_gadget_register_driver
  1330. */
  1331. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1332. {
  1333. struct s3c2410_udc *udc = the_controller;
  1334. int retval;
  1335. dprintk(DEBUG_NORMAL, "usb_gadget_register_driver() '%s'\n",
  1336. driver->driver.name);
  1337. /* Sanity checks */
  1338. if (!udc)
  1339. return -ENODEV;
  1340. if (udc->driver)
  1341. return -EBUSY;
  1342. if (!driver->bind || !driver->setup
  1343. || driver->speed < USB_SPEED_FULL) {
  1344. printk(KERN_ERR "Invalid driver: bind %p setup %p speed %d\n",
  1345. driver->bind, driver->setup, driver->speed);
  1346. return -EINVAL;
  1347. }
  1348. #if defined(MODULE)
  1349. if (!driver->unbind) {
  1350. printk(KERN_ERR "Invalid driver: no unbind method\n");
  1351. return -EINVAL;
  1352. }
  1353. #endif
  1354. /* Hook the driver */
  1355. udc->driver = driver;
  1356. udc->gadget.dev.driver = &driver->driver;
  1357. /* Bind the driver */
  1358. if ((retval = device_add(&udc->gadget.dev)) != 0) {
  1359. printk(KERN_ERR "Error in device_add() : %d\n",retval);
  1360. goto register_error;
  1361. }
  1362. dprintk(DEBUG_NORMAL, "binding gadget driver '%s'\n",
  1363. driver->driver.name);
  1364. if ((retval = driver->bind (&udc->gadget)) != 0) {
  1365. device_del(&udc->gadget.dev);
  1366. goto register_error;
  1367. }
  1368. /* Enable udc */
  1369. s3c2410_udc_enable(udc);
  1370. return 0;
  1371. register_error:
  1372. udc->driver = NULL;
  1373. udc->gadget.dev.driver = NULL;
  1374. return retval;
  1375. }
  1376. /*
  1377. * usb_gadget_unregister_driver
  1378. */
  1379. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1380. {
  1381. struct s3c2410_udc *udc = the_controller;
  1382. if (!udc)
  1383. return -ENODEV;
  1384. if (!driver || driver != udc->driver || !driver->unbind)
  1385. return -EINVAL;
  1386. dprintk(DEBUG_NORMAL,"usb_gadget_register_driver() '%s'\n",
  1387. driver->driver.name);
  1388. if (driver->disconnect)
  1389. driver->disconnect(&udc->gadget);
  1390. device_del(&udc->gadget.dev);
  1391. udc->driver = NULL;
  1392. /* Disable udc */
  1393. s3c2410_udc_disable(udc);
  1394. return 0;
  1395. }
  1396. /*---------------------------------------------------------------------------*/
  1397. static struct s3c2410_udc memory = {
  1398. .gadget = {
  1399. .ops = &s3c2410_ops,
  1400. .ep0 = &memory.ep[0].ep,
  1401. .name = gadget_name,
  1402. .dev = {
  1403. .init_name = "gadget",
  1404. },
  1405. },
  1406. /* control endpoint */
  1407. .ep[0] = {
  1408. .num = 0,
  1409. .ep = {
  1410. .name = ep0name,
  1411. .ops = &s3c2410_ep_ops,
  1412. .maxpacket = EP0_FIFO_SIZE,
  1413. },
  1414. .dev = &memory,
  1415. },
  1416. /* first group of endpoints */
  1417. .ep[1] = {
  1418. .num = 1,
  1419. .ep = {
  1420. .name = "ep1-bulk",
  1421. .ops = &s3c2410_ep_ops,
  1422. .maxpacket = EP_FIFO_SIZE,
  1423. },
  1424. .dev = &memory,
  1425. .fifo_size = EP_FIFO_SIZE,
  1426. .bEndpointAddress = 1,
  1427. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1428. },
  1429. .ep[2] = {
  1430. .num = 2,
  1431. .ep = {
  1432. .name = "ep2-bulk",
  1433. .ops = &s3c2410_ep_ops,
  1434. .maxpacket = EP_FIFO_SIZE,
  1435. },
  1436. .dev = &memory,
  1437. .fifo_size = EP_FIFO_SIZE,
  1438. .bEndpointAddress = 2,
  1439. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1440. },
  1441. .ep[3] = {
  1442. .num = 3,
  1443. .ep = {
  1444. .name = "ep3-bulk",
  1445. .ops = &s3c2410_ep_ops,
  1446. .maxpacket = EP_FIFO_SIZE,
  1447. },
  1448. .dev = &memory,
  1449. .fifo_size = EP_FIFO_SIZE,
  1450. .bEndpointAddress = 3,
  1451. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1452. },
  1453. .ep[4] = {
  1454. .num = 4,
  1455. .ep = {
  1456. .name = "ep4-bulk",
  1457. .ops = &s3c2410_ep_ops,
  1458. .maxpacket = EP_FIFO_SIZE,
  1459. },
  1460. .dev = &memory,
  1461. .fifo_size = EP_FIFO_SIZE,
  1462. .bEndpointAddress = 4,
  1463. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  1464. }
  1465. };
  1466. /*
  1467. * probe - binds to the platform device
  1468. */
  1469. static int s3c2410_udc_probe(struct platform_device *pdev)
  1470. {
  1471. struct s3c2410_udc *udc = &memory;
  1472. struct device *dev = &pdev->dev;
  1473. int retval;
  1474. int irq;
  1475. dev_dbg(dev, "%s()\n", __func__);
  1476. usb_bus_clock = clk_get(NULL, "usb-bus-gadget");
  1477. if (IS_ERR(usb_bus_clock)) {
  1478. dev_err(dev, "failed to get usb bus clock source\n");
  1479. return PTR_ERR(usb_bus_clock);
  1480. }
  1481. clk_enable(usb_bus_clock);
  1482. udc_clock = clk_get(NULL, "usb-device");
  1483. if (IS_ERR(udc_clock)) {
  1484. dev_err(dev, "failed to get udc clock source\n");
  1485. return PTR_ERR(udc_clock);
  1486. }
  1487. clk_enable(udc_clock);
  1488. mdelay(10);
  1489. dev_dbg(dev, "got and enabled clocks\n");
  1490. if (strncmp(pdev->name, "s3c2440", 7) == 0) {
  1491. dev_info(dev, "S3C2440: increasing FIFO to 128 bytes\n");
  1492. memory.ep[1].fifo_size = S3C2440_EP_FIFO_SIZE;
  1493. memory.ep[2].fifo_size = S3C2440_EP_FIFO_SIZE;
  1494. memory.ep[3].fifo_size = S3C2440_EP_FIFO_SIZE;
  1495. memory.ep[4].fifo_size = S3C2440_EP_FIFO_SIZE;
  1496. }
  1497. spin_lock_init (&udc->lock);
  1498. udc_info = pdev->dev.platform_data;
  1499. rsrc_start = S3C2410_PA_USBDEV;
  1500. rsrc_len = S3C24XX_SZ_USBDEV;
  1501. if (!request_mem_region(rsrc_start, rsrc_len, gadget_name))
  1502. return -EBUSY;
  1503. base_addr = ioremap(rsrc_start, rsrc_len);
  1504. if (!base_addr) {
  1505. retval = -ENOMEM;
  1506. goto err_mem;
  1507. }
  1508. device_initialize(&udc->gadget.dev);
  1509. udc->gadget.dev.parent = &pdev->dev;
  1510. udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1511. the_controller = udc;
  1512. platform_set_drvdata(pdev, udc);
  1513. s3c2410_udc_disable(udc);
  1514. s3c2410_udc_reinit(udc);
  1515. /* irq setup after old hardware state is cleaned up */
  1516. retval = request_irq(IRQ_USBD, s3c2410_udc_irq,
  1517. IRQF_DISABLED, gadget_name, udc);
  1518. if (retval != 0) {
  1519. dev_err(dev, "cannot get irq %i, err %d\n", IRQ_USBD, retval);
  1520. retval = -EBUSY;
  1521. goto err_map;
  1522. }
  1523. dev_dbg(dev, "got irq %i\n", IRQ_USBD);
  1524. if (udc_info && udc_info->vbus_pin > 0) {
  1525. retval = gpio_request(udc_info->vbus_pin, "udc vbus");
  1526. if (retval < 0) {
  1527. dev_err(dev, "cannot claim vbus pin\n");
  1528. goto err_int;
  1529. }
  1530. irq = gpio_to_irq(udc_info->vbus_pin);
  1531. if (irq < 0) {
  1532. dev_err(dev, "no irq for gpio vbus pin\n");
  1533. goto err_gpio_claim;
  1534. }
  1535. retval = request_irq(irq, s3c2410_udc_vbus_irq,
  1536. IRQF_DISABLED | IRQF_TRIGGER_RISING
  1537. | IRQF_TRIGGER_FALLING | IRQF_SHARED,
  1538. gadget_name, udc);
  1539. if (retval != 0) {
  1540. dev_err(dev, "can't get vbus irq %d, err %d\n",
  1541. irq, retval);
  1542. retval = -EBUSY;
  1543. goto err_gpio_claim;
  1544. }
  1545. dev_dbg(dev, "got irq %i\n", irq);
  1546. } else {
  1547. udc->vbus = 1;
  1548. }
  1549. if (s3c2410_udc_debugfs_root) {
  1550. udc->regs_info = debugfs_create_file("registers", S_IRUGO,
  1551. s3c2410_udc_debugfs_root,
  1552. udc, &s3c2410_udc_debugfs_fops);
  1553. if (!udc->regs_info)
  1554. dev_warn(dev, "debugfs file creation failed\n");
  1555. }
  1556. dev_dbg(dev, "probe ok\n");
  1557. return 0;
  1558. err_gpio_claim:
  1559. if (udc_info && udc_info->vbus_pin > 0)
  1560. gpio_free(udc_info->vbus_pin);
  1561. err_int:
  1562. free_irq(IRQ_USBD, udc);
  1563. err_map:
  1564. iounmap(base_addr);
  1565. err_mem:
  1566. release_mem_region(rsrc_start, rsrc_len);
  1567. return retval;
  1568. }
  1569. /*
  1570. * s3c2410_udc_remove
  1571. */
  1572. static int s3c2410_udc_remove(struct platform_device *pdev)
  1573. {
  1574. struct s3c2410_udc *udc = platform_get_drvdata(pdev);
  1575. unsigned int irq;
  1576. dev_dbg(&pdev->dev, "%s()\n", __func__);
  1577. if (udc->driver)
  1578. return -EBUSY;
  1579. debugfs_remove(udc->regs_info);
  1580. if (udc_info && udc_info->vbus_pin > 0) {
  1581. irq = gpio_to_irq(udc_info->vbus_pin);
  1582. free_irq(irq, udc);
  1583. }
  1584. free_irq(IRQ_USBD, udc);
  1585. iounmap(base_addr);
  1586. release_mem_region(rsrc_start, rsrc_len);
  1587. platform_set_drvdata(pdev, NULL);
  1588. if (!IS_ERR(udc_clock) && udc_clock != NULL) {
  1589. clk_disable(udc_clock);
  1590. clk_put(udc_clock);
  1591. udc_clock = NULL;
  1592. }
  1593. if (!IS_ERR(usb_bus_clock) && usb_bus_clock != NULL) {
  1594. clk_disable(usb_bus_clock);
  1595. clk_put(usb_bus_clock);
  1596. usb_bus_clock = NULL;
  1597. }
  1598. dev_dbg(&pdev->dev, "%s: remove ok\n", __func__);
  1599. return 0;
  1600. }
  1601. #ifdef CONFIG_PM
  1602. static int s3c2410_udc_suspend(struct platform_device *pdev, pm_message_t message)
  1603. {
  1604. if (udc_info && udc_info->udc_command)
  1605. udc_info->udc_command(S3C2410_UDC_P_DISABLE);
  1606. return 0;
  1607. }
  1608. static int s3c2410_udc_resume(struct platform_device *pdev)
  1609. {
  1610. if (udc_info && udc_info->udc_command)
  1611. udc_info->udc_command(S3C2410_UDC_P_ENABLE);
  1612. return 0;
  1613. }
  1614. #else
  1615. #define s3c2410_udc_suspend NULL
  1616. #define s3c2410_udc_resume NULL
  1617. #endif
  1618. static struct platform_driver udc_driver_2410 = {
  1619. .driver = {
  1620. .name = "s3c2410-usbgadget",
  1621. .owner = THIS_MODULE,
  1622. },
  1623. .probe = s3c2410_udc_probe,
  1624. .remove = s3c2410_udc_remove,
  1625. .suspend = s3c2410_udc_suspend,
  1626. .resume = s3c2410_udc_resume,
  1627. };
  1628. static struct platform_driver udc_driver_2440 = {
  1629. .driver = {
  1630. .name = "s3c2440-usbgadget",
  1631. .owner = THIS_MODULE,
  1632. },
  1633. .probe = s3c2410_udc_probe,
  1634. .remove = s3c2410_udc_remove,
  1635. .suspend = s3c2410_udc_suspend,
  1636. .resume = s3c2410_udc_resume,
  1637. };
  1638. static int __init udc_init(void)
  1639. {
  1640. int retval;
  1641. dprintk(DEBUG_NORMAL, "%s: version %s\n", gadget_name, DRIVER_VERSION);
  1642. s3c2410_udc_debugfs_root = debugfs_create_dir(gadget_name, NULL);
  1643. if (IS_ERR(s3c2410_udc_debugfs_root)) {
  1644. printk(KERN_ERR "%s: debugfs dir creation failed %ld\n",
  1645. gadget_name, PTR_ERR(s3c2410_udc_debugfs_root));
  1646. s3c2410_udc_debugfs_root = NULL;
  1647. }
  1648. retval = platform_driver_register(&udc_driver_2410);
  1649. if (retval)
  1650. goto err;
  1651. retval = platform_driver_register(&udc_driver_2440);
  1652. if (retval)
  1653. goto err;
  1654. return 0;
  1655. err:
  1656. debugfs_remove(s3c2410_udc_debugfs_root);
  1657. return retval;
  1658. }
  1659. static void __exit udc_exit(void)
  1660. {
  1661. platform_driver_unregister(&udc_driver_2410);
  1662. platform_driver_unregister(&udc_driver_2440);
  1663. debugfs_remove(s3c2410_udc_debugfs_root);
  1664. }
  1665. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1666. EXPORT_SYMBOL(usb_gadget_register_driver);
  1667. module_init(udc_init);
  1668. module_exit(udc_exit);
  1669. MODULE_AUTHOR(DRIVER_AUTHOR);
  1670. MODULE_DESCRIPTION(DRIVER_DESC);
  1671. MODULE_VERSION(DRIVER_VERSION);
  1672. MODULE_LICENSE("GPL");
  1673. MODULE_ALIAS("platform:s3c2410-usbgadget");
  1674. MODULE_ALIAS("platform:s3c2440-usbgadget");