spi_s3c24xx.c 10 KB

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  1. /* linux/drivers/spi/spi_s3c24xx.c
  2. *
  3. * Copyright (c) 2006 Ben Dooks
  4. * Copyright (c) 2006 Simtec Electronics
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. */
  12. #include <linux/init.h>
  13. #include <linux/spinlock.h>
  14. #include <linux/workqueue.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/delay.h>
  17. #include <linux/errno.h>
  18. #include <linux/err.h>
  19. #include <linux/clk.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/gpio.h>
  22. #include <linux/spi/spi.h>
  23. #include <linux/spi/spi_bitbang.h>
  24. #include <asm/io.h>
  25. #include <asm/dma.h>
  26. #include <mach/hardware.h>
  27. #include <plat/regs-spi.h>
  28. #include <mach/spi.h>
  29. struct s3c24xx_spi {
  30. /* bitbang has to be first */
  31. struct spi_bitbang bitbang;
  32. struct completion done;
  33. void __iomem *regs;
  34. int irq;
  35. int len;
  36. int count;
  37. void (*set_cs)(struct s3c2410_spi_info *spi,
  38. int cs, int pol);
  39. /* data buffers */
  40. const unsigned char *tx;
  41. unsigned char *rx;
  42. struct clk *clk;
  43. struct resource *ioarea;
  44. struct spi_master *master;
  45. struct spi_device *curdev;
  46. struct device *dev;
  47. struct s3c2410_spi_info *pdata;
  48. };
  49. #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
  50. #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
  51. static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
  52. {
  53. return spi_master_get_devdata(sdev->master);
  54. }
  55. static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
  56. {
  57. gpio_set_value(spi->pin_cs, pol);
  58. }
  59. static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
  60. {
  61. struct s3c24xx_spi *hw = to_hw(spi);
  62. unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
  63. unsigned int spcon;
  64. switch (value) {
  65. case BITBANG_CS_INACTIVE:
  66. hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
  67. break;
  68. case BITBANG_CS_ACTIVE:
  69. spcon = readb(hw->regs + S3C2410_SPCON);
  70. if (spi->mode & SPI_CPHA)
  71. spcon |= S3C2410_SPCON_CPHA_FMTB;
  72. else
  73. spcon &= ~S3C2410_SPCON_CPHA_FMTB;
  74. if (spi->mode & SPI_CPOL)
  75. spcon |= S3C2410_SPCON_CPOL_HIGH;
  76. else
  77. spcon &= ~S3C2410_SPCON_CPOL_HIGH;
  78. spcon |= S3C2410_SPCON_ENSCK;
  79. /* write new configration */
  80. writeb(spcon, hw->regs + S3C2410_SPCON);
  81. hw->set_cs(hw->pdata, spi->chip_select, cspol);
  82. break;
  83. }
  84. }
  85. static int s3c24xx_spi_setupxfer(struct spi_device *spi,
  86. struct spi_transfer *t)
  87. {
  88. struct s3c24xx_spi *hw = to_hw(spi);
  89. unsigned int bpw;
  90. unsigned int hz;
  91. unsigned int div;
  92. bpw = t ? t->bits_per_word : spi->bits_per_word;
  93. hz = t ? t->speed_hz : spi->max_speed_hz;
  94. if (bpw != 8) {
  95. dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
  96. return -EINVAL;
  97. }
  98. div = clk_get_rate(hw->clk) / hz;
  99. /* is clk = pclk / (2 * (pre+1)), or is it
  100. * clk = (pclk * 2) / ( pre + 1) */
  101. div /= 2;
  102. if (div > 0)
  103. div -= 1;
  104. if (div > 255)
  105. div = 255;
  106. dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", div, hz);
  107. writeb(div, hw->regs + S3C2410_SPPRE);
  108. spin_lock(&hw->bitbang.lock);
  109. if (!hw->bitbang.busy) {
  110. hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
  111. /* need to ndelay for 0.5 clocktick ? */
  112. }
  113. spin_unlock(&hw->bitbang.lock);
  114. return 0;
  115. }
  116. /* the spi->mode bits understood by this driver: */
  117. #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
  118. static int s3c24xx_spi_setup(struct spi_device *spi)
  119. {
  120. int ret;
  121. if (!spi->bits_per_word)
  122. spi->bits_per_word = 8;
  123. if (spi->mode & ~MODEBITS) {
  124. dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
  125. spi->mode & ~MODEBITS);
  126. return -EINVAL;
  127. }
  128. ret = s3c24xx_spi_setupxfer(spi, NULL);
  129. if (ret < 0) {
  130. dev_err(&spi->dev, "setupxfer returned %d\n", ret);
  131. return ret;
  132. }
  133. dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n",
  134. __func__, spi->mode, spi->bits_per_word,
  135. spi->max_speed_hz);
  136. return 0;
  137. }
  138. static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
  139. {
  140. return hw->tx ? hw->tx[count] : 0;
  141. }
  142. static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
  143. {
  144. struct s3c24xx_spi *hw = to_hw(spi);
  145. dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
  146. t->tx_buf, t->rx_buf, t->len);
  147. hw->tx = t->tx_buf;
  148. hw->rx = t->rx_buf;
  149. hw->len = t->len;
  150. hw->count = 0;
  151. init_completion(&hw->done);
  152. /* send the first byte */
  153. writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
  154. wait_for_completion(&hw->done);
  155. return hw->count;
  156. }
  157. static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
  158. {
  159. struct s3c24xx_spi *hw = dev;
  160. unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
  161. unsigned int count = hw->count;
  162. if (spsta & S3C2410_SPSTA_DCOL) {
  163. dev_dbg(hw->dev, "data-collision\n");
  164. complete(&hw->done);
  165. goto irq_done;
  166. }
  167. if (!(spsta & S3C2410_SPSTA_READY)) {
  168. dev_dbg(hw->dev, "spi not ready for tx?\n");
  169. complete(&hw->done);
  170. goto irq_done;
  171. }
  172. hw->count++;
  173. if (hw->rx)
  174. hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
  175. count++;
  176. if (count < hw->len)
  177. writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
  178. else
  179. complete(&hw->done);
  180. irq_done:
  181. return IRQ_HANDLED;
  182. }
  183. static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
  184. {
  185. /* for the moment, permanently enable the clock */
  186. clk_enable(hw->clk);
  187. /* program defaults into the registers */
  188. writeb(0xff, hw->regs + S3C2410_SPPRE);
  189. writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
  190. writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
  191. if (hw->pdata) {
  192. if (hw->set_cs == s3c24xx_spi_gpiocs)
  193. gpio_direction_output(hw->pdata->pin_cs, 1);
  194. if (hw->pdata->gpio_setup)
  195. hw->pdata->gpio_setup(hw->pdata, 1);
  196. }
  197. }
  198. static int __init s3c24xx_spi_probe(struct platform_device *pdev)
  199. {
  200. struct s3c2410_spi_info *pdata;
  201. struct s3c24xx_spi *hw;
  202. struct spi_master *master;
  203. struct resource *res;
  204. int err = 0;
  205. master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
  206. if (master == NULL) {
  207. dev_err(&pdev->dev, "No memory for spi_master\n");
  208. err = -ENOMEM;
  209. goto err_nomem;
  210. }
  211. hw = spi_master_get_devdata(master);
  212. memset(hw, 0, sizeof(struct s3c24xx_spi));
  213. hw->master = spi_master_get(master);
  214. hw->pdata = pdata = pdev->dev.platform_data;
  215. hw->dev = &pdev->dev;
  216. if (pdata == NULL) {
  217. dev_err(&pdev->dev, "No platform data supplied\n");
  218. err = -ENOENT;
  219. goto err_no_pdata;
  220. }
  221. platform_set_drvdata(pdev, hw);
  222. init_completion(&hw->done);
  223. /* setup the master state. */
  224. master->num_chipselect = hw->pdata->num_cs;
  225. master->bus_num = pdata->bus_num;
  226. /* setup the state for the bitbang driver */
  227. hw->bitbang.master = hw->master;
  228. hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
  229. hw->bitbang.chipselect = s3c24xx_spi_chipsel;
  230. hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
  231. hw->bitbang.master->setup = s3c24xx_spi_setup;
  232. dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
  233. /* find and map our resources */
  234. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  235. if (res == NULL) {
  236. dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
  237. err = -ENOENT;
  238. goto err_no_iores;
  239. }
  240. hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
  241. pdev->name);
  242. if (hw->ioarea == NULL) {
  243. dev_err(&pdev->dev, "Cannot reserve region\n");
  244. err = -ENXIO;
  245. goto err_no_iores;
  246. }
  247. hw->regs = ioremap(res->start, (res->end - res->start)+1);
  248. if (hw->regs == NULL) {
  249. dev_err(&pdev->dev, "Cannot map IO\n");
  250. err = -ENXIO;
  251. goto err_no_iomap;
  252. }
  253. hw->irq = platform_get_irq(pdev, 0);
  254. if (hw->irq < 0) {
  255. dev_err(&pdev->dev, "No IRQ specified\n");
  256. err = -ENOENT;
  257. goto err_no_irq;
  258. }
  259. err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
  260. if (err) {
  261. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  262. goto err_no_irq;
  263. }
  264. hw->clk = clk_get(&pdev->dev, "spi");
  265. if (IS_ERR(hw->clk)) {
  266. dev_err(&pdev->dev, "No clock for device\n");
  267. err = PTR_ERR(hw->clk);
  268. goto err_no_clk;
  269. }
  270. /* setup any gpio we can */
  271. if (!pdata->set_cs) {
  272. if (pdata->pin_cs < 0) {
  273. dev_err(&pdev->dev, "No chipselect pin\n");
  274. goto err_register;
  275. }
  276. err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev));
  277. if (err) {
  278. dev_err(&pdev->dev, "Failed to get gpio for cs\n");
  279. goto err_register;
  280. }
  281. hw->set_cs = s3c24xx_spi_gpiocs;
  282. gpio_direction_output(pdata->pin_cs, 1);
  283. } else
  284. hw->set_cs = pdata->set_cs;
  285. s3c24xx_spi_initialsetup(hw);
  286. /* register our spi controller */
  287. err = spi_bitbang_start(&hw->bitbang);
  288. if (err) {
  289. dev_err(&pdev->dev, "Failed to register SPI master\n");
  290. goto err_register;
  291. }
  292. return 0;
  293. err_register:
  294. if (hw->set_cs == s3c24xx_spi_gpiocs)
  295. gpio_free(pdata->pin_cs);
  296. clk_disable(hw->clk);
  297. clk_put(hw->clk);
  298. err_no_clk:
  299. free_irq(hw->irq, hw);
  300. err_no_irq:
  301. iounmap(hw->regs);
  302. err_no_iomap:
  303. release_resource(hw->ioarea);
  304. kfree(hw->ioarea);
  305. err_no_iores:
  306. err_no_pdata:
  307. spi_master_put(hw->master);;
  308. err_nomem:
  309. return err;
  310. }
  311. static int __exit s3c24xx_spi_remove(struct platform_device *dev)
  312. {
  313. struct s3c24xx_spi *hw = platform_get_drvdata(dev);
  314. platform_set_drvdata(dev, NULL);
  315. spi_unregister_master(hw->master);
  316. clk_disable(hw->clk);
  317. clk_put(hw->clk);
  318. free_irq(hw->irq, hw);
  319. iounmap(hw->regs);
  320. if (hw->set_cs == s3c24xx_spi_gpiocs)
  321. gpio_free(hw->pdata->pin_cs);
  322. release_resource(hw->ioarea);
  323. kfree(hw->ioarea);
  324. spi_master_put(hw->master);
  325. return 0;
  326. }
  327. #ifdef CONFIG_PM
  328. static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
  329. {
  330. struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
  331. if (hw->pdata && hw->pdata->gpio_setup)
  332. hw->pdata->gpio_setup(hw->pdata, 0);
  333. clk_disable(hw->clk);
  334. return 0;
  335. }
  336. static int s3c24xx_spi_resume(struct platform_device *pdev)
  337. {
  338. struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
  339. s3c24xx_spi_initialsetup(hw);
  340. return 0;
  341. }
  342. #else
  343. #define s3c24xx_spi_suspend NULL
  344. #define s3c24xx_spi_resume NULL
  345. #endif
  346. MODULE_ALIAS("platform:s3c2410-spi");
  347. static struct platform_driver s3c24xx_spi_driver = {
  348. .remove = __exit_p(s3c24xx_spi_remove),
  349. .suspend = s3c24xx_spi_suspend,
  350. .resume = s3c24xx_spi_resume,
  351. .driver = {
  352. .name = "s3c2410-spi",
  353. .owner = THIS_MODULE,
  354. },
  355. };
  356. static int __init s3c24xx_spi_init(void)
  357. {
  358. return platform_driver_probe(&s3c24xx_spi_driver, s3c24xx_spi_probe);
  359. }
  360. static void __exit s3c24xx_spi_exit(void)
  361. {
  362. platform_driver_unregister(&s3c24xx_spi_driver);
  363. }
  364. module_init(s3c24xx_spi_init);
  365. module_exit(s3c24xx_spi_exit);
  366. MODULE_DESCRIPTION("S3C24XX SPI Driver");
  367. MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
  368. MODULE_LICENSE("GPL");