qeth_core_main.c 123 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <asm/ebcdic.h>
  22. #include <asm/io.h>
  23. #include "qeth_core.h"
  24. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  25. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  26. /* N P A M L V H */
  27. [QETH_DBF_SETUP] = {"qeth_setup",
  28. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  29. [QETH_DBF_QERR] = {"qeth_qerr",
  30. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  31. [QETH_DBF_TRACE] = {"qeth_trace",
  32. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  33. [QETH_DBF_MSG] = {"qeth_msg",
  34. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  35. [QETH_DBF_SENSE] = {"qeth_sense",
  36. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  37. [QETH_DBF_MISC] = {"qeth_misc",
  38. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  39. [QETH_DBF_CTRL] = {"qeth_control",
  40. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  41. };
  42. EXPORT_SYMBOL_GPL(qeth_dbf);
  43. struct qeth_card_list_struct qeth_core_card_list;
  44. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  45. struct kmem_cache *qeth_core_header_cache;
  46. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  47. static struct device *qeth_core_root_dev;
  48. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  49. static struct lock_class_key qdio_out_skb_queue_key;
  50. static void qeth_send_control_data_cb(struct qeth_channel *,
  51. struct qeth_cmd_buffer *);
  52. static int qeth_issue_next_read(struct qeth_card *);
  53. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  54. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  55. static void qeth_free_buffer_pool(struct qeth_card *);
  56. static int qeth_qdio_establish(struct qeth_card *);
  57. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  58. struct qdio_buffer *buffer, int is_tso,
  59. int *next_element_to_fill)
  60. {
  61. struct skb_frag_struct *frag;
  62. int fragno;
  63. unsigned long addr;
  64. int element, cnt, dlen;
  65. fragno = skb_shinfo(skb)->nr_frags;
  66. element = *next_element_to_fill;
  67. dlen = 0;
  68. if (is_tso)
  69. buffer->element[element].flags =
  70. SBAL_FLAGS_MIDDLE_FRAG;
  71. else
  72. buffer->element[element].flags =
  73. SBAL_FLAGS_FIRST_FRAG;
  74. dlen = skb->len - skb->data_len;
  75. if (dlen) {
  76. buffer->element[element].addr = skb->data;
  77. buffer->element[element].length = dlen;
  78. element++;
  79. }
  80. for (cnt = 0; cnt < fragno; cnt++) {
  81. frag = &skb_shinfo(skb)->frags[cnt];
  82. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  83. frag->page_offset;
  84. buffer->element[element].addr = (char *)addr;
  85. buffer->element[element].length = frag->size;
  86. if (cnt < (fragno - 1))
  87. buffer->element[element].flags =
  88. SBAL_FLAGS_MIDDLE_FRAG;
  89. else
  90. buffer->element[element].flags =
  91. SBAL_FLAGS_LAST_FRAG;
  92. element++;
  93. }
  94. *next_element_to_fill = element;
  95. }
  96. static inline const char *qeth_get_cardname(struct qeth_card *card)
  97. {
  98. if (card->info.guestlan) {
  99. switch (card->info.type) {
  100. case QETH_CARD_TYPE_OSAE:
  101. return " Guest LAN QDIO";
  102. case QETH_CARD_TYPE_IQD:
  103. return " Guest LAN Hiper";
  104. default:
  105. return " unknown";
  106. }
  107. } else {
  108. switch (card->info.type) {
  109. case QETH_CARD_TYPE_OSAE:
  110. return " OSD Express";
  111. case QETH_CARD_TYPE_IQD:
  112. return " HiperSockets";
  113. case QETH_CARD_TYPE_OSN:
  114. return " OSN QDIO";
  115. default:
  116. return " unknown";
  117. }
  118. }
  119. return " n/a";
  120. }
  121. /* max length to be returned: 14 */
  122. const char *qeth_get_cardname_short(struct qeth_card *card)
  123. {
  124. if (card->info.guestlan) {
  125. switch (card->info.type) {
  126. case QETH_CARD_TYPE_OSAE:
  127. return "GuestLAN QDIO";
  128. case QETH_CARD_TYPE_IQD:
  129. return "GuestLAN Hiper";
  130. default:
  131. return "unknown";
  132. }
  133. } else {
  134. switch (card->info.type) {
  135. case QETH_CARD_TYPE_OSAE:
  136. switch (card->info.link_type) {
  137. case QETH_LINK_TYPE_FAST_ETH:
  138. return "OSD_100";
  139. case QETH_LINK_TYPE_HSTR:
  140. return "HSTR";
  141. case QETH_LINK_TYPE_GBIT_ETH:
  142. return "OSD_1000";
  143. case QETH_LINK_TYPE_10GBIT_ETH:
  144. return "OSD_10GIG";
  145. case QETH_LINK_TYPE_LANE_ETH100:
  146. return "OSD_FE_LANE";
  147. case QETH_LINK_TYPE_LANE_TR:
  148. return "OSD_TR_LANE";
  149. case QETH_LINK_TYPE_LANE_ETH1000:
  150. return "OSD_GbE_LANE";
  151. case QETH_LINK_TYPE_LANE:
  152. return "OSD_ATM_LANE";
  153. default:
  154. return "OSD_Express";
  155. }
  156. case QETH_CARD_TYPE_IQD:
  157. return "HiperSockets";
  158. case QETH_CARD_TYPE_OSN:
  159. return "OSN";
  160. default:
  161. return "unknown";
  162. }
  163. }
  164. return "n/a";
  165. }
  166. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  167. int clear_start_mask)
  168. {
  169. unsigned long flags;
  170. spin_lock_irqsave(&card->thread_mask_lock, flags);
  171. card->thread_allowed_mask = threads;
  172. if (clear_start_mask)
  173. card->thread_start_mask &= threads;
  174. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  175. wake_up(&card->wait_q);
  176. }
  177. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  178. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  179. {
  180. unsigned long flags;
  181. int rc = 0;
  182. spin_lock_irqsave(&card->thread_mask_lock, flags);
  183. rc = (card->thread_running_mask & threads);
  184. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  185. return rc;
  186. }
  187. EXPORT_SYMBOL_GPL(qeth_threads_running);
  188. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  189. {
  190. return wait_event_interruptible(card->wait_q,
  191. qeth_threads_running(card, threads) == 0);
  192. }
  193. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  194. void qeth_clear_working_pool_list(struct qeth_card *card)
  195. {
  196. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  197. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  198. list_for_each_entry_safe(pool_entry, tmp,
  199. &card->qdio.in_buf_pool.entry_list, list){
  200. list_del(&pool_entry->list);
  201. }
  202. }
  203. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  204. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  205. {
  206. struct qeth_buffer_pool_entry *pool_entry;
  207. void *ptr;
  208. int i, j;
  209. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  210. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  211. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  212. if (!pool_entry) {
  213. qeth_free_buffer_pool(card);
  214. return -ENOMEM;
  215. }
  216. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  217. ptr = (void *) __get_free_page(GFP_KERNEL);
  218. if (!ptr) {
  219. while (j > 0)
  220. free_page((unsigned long)
  221. pool_entry->elements[--j]);
  222. kfree(pool_entry);
  223. qeth_free_buffer_pool(card);
  224. return -ENOMEM;
  225. }
  226. pool_entry->elements[j] = ptr;
  227. }
  228. list_add(&pool_entry->init_list,
  229. &card->qdio.init_pool.entry_list);
  230. }
  231. return 0;
  232. }
  233. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  234. {
  235. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  236. if ((card->state != CARD_STATE_DOWN) &&
  237. (card->state != CARD_STATE_RECOVER))
  238. return -EPERM;
  239. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  240. qeth_clear_working_pool_list(card);
  241. qeth_free_buffer_pool(card);
  242. card->qdio.in_buf_pool.buf_count = bufcnt;
  243. card->qdio.init_pool.buf_count = bufcnt;
  244. return qeth_alloc_buffer_pool(card);
  245. }
  246. int qeth_set_large_send(struct qeth_card *card,
  247. enum qeth_large_send_types type)
  248. {
  249. int rc = 0;
  250. if (card->dev == NULL) {
  251. card->options.large_send = type;
  252. return 0;
  253. }
  254. if (card->state == CARD_STATE_UP)
  255. netif_tx_disable(card->dev);
  256. card->options.large_send = type;
  257. switch (card->options.large_send) {
  258. case QETH_LARGE_SEND_TSO:
  259. if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
  260. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  261. NETIF_F_HW_CSUM;
  262. } else {
  263. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  264. NETIF_F_HW_CSUM);
  265. card->options.large_send = QETH_LARGE_SEND_NO;
  266. rc = -EOPNOTSUPP;
  267. }
  268. break;
  269. default: /* includes QETH_LARGE_SEND_NO */
  270. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  271. NETIF_F_HW_CSUM);
  272. break;
  273. }
  274. if (card->state == CARD_STATE_UP)
  275. netif_wake_queue(card->dev);
  276. return rc;
  277. }
  278. EXPORT_SYMBOL_GPL(qeth_set_large_send);
  279. static int qeth_issue_next_read(struct qeth_card *card)
  280. {
  281. int rc;
  282. struct qeth_cmd_buffer *iob;
  283. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  284. if (card->read.state != CH_STATE_UP)
  285. return -EIO;
  286. iob = qeth_get_buffer(&card->read);
  287. if (!iob) {
  288. dev_warn(&card->gdev->dev, "The qeth device driver "
  289. "failed to recover an error on the device\n");
  290. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  291. "available\n", dev_name(&card->gdev->dev));
  292. return -ENOMEM;
  293. }
  294. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  295. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  296. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  297. (addr_t) iob, 0, 0);
  298. if (rc) {
  299. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  300. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  301. atomic_set(&card->read.irq_pending, 0);
  302. qeth_schedule_recovery(card);
  303. wake_up(&card->wait_q);
  304. }
  305. return rc;
  306. }
  307. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  308. {
  309. struct qeth_reply *reply;
  310. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  311. if (reply) {
  312. atomic_set(&reply->refcnt, 1);
  313. atomic_set(&reply->received, 0);
  314. reply->card = card;
  315. };
  316. return reply;
  317. }
  318. static void qeth_get_reply(struct qeth_reply *reply)
  319. {
  320. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  321. atomic_inc(&reply->refcnt);
  322. }
  323. static void qeth_put_reply(struct qeth_reply *reply)
  324. {
  325. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  326. if (atomic_dec_and_test(&reply->refcnt))
  327. kfree(reply);
  328. }
  329. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  330. struct qeth_card *card)
  331. {
  332. char *ipa_name;
  333. int com = cmd->hdr.command;
  334. ipa_name = qeth_get_ipa_cmd_name(com);
  335. if (rc)
  336. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  337. ipa_name, com, QETH_CARD_IFNAME(card),
  338. rc, qeth_get_ipa_msg(rc));
  339. else
  340. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  341. ipa_name, com, QETH_CARD_IFNAME(card));
  342. }
  343. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  344. struct qeth_cmd_buffer *iob)
  345. {
  346. struct qeth_ipa_cmd *cmd = NULL;
  347. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  348. if (IS_IPA(iob->data)) {
  349. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  350. if (IS_IPA_REPLY(cmd)) {
  351. if (cmd->hdr.command < IPA_CMD_SETCCID ||
  352. cmd->hdr.command > IPA_CMD_MODCCID)
  353. qeth_issue_ipa_msg(cmd,
  354. cmd->hdr.return_code, card);
  355. return cmd;
  356. } else {
  357. switch (cmd->hdr.command) {
  358. case IPA_CMD_STOPLAN:
  359. dev_warn(&card->gdev->dev,
  360. "The link for interface %s on CHPID"
  361. " 0x%X failed\n",
  362. QETH_CARD_IFNAME(card),
  363. card->info.chpid);
  364. card->lan_online = 0;
  365. if (card->dev && netif_carrier_ok(card->dev))
  366. netif_carrier_off(card->dev);
  367. return NULL;
  368. case IPA_CMD_STARTLAN:
  369. dev_info(&card->gdev->dev,
  370. "The link for %s on CHPID 0x%X has"
  371. " been restored\n",
  372. QETH_CARD_IFNAME(card),
  373. card->info.chpid);
  374. netif_carrier_on(card->dev);
  375. card->lan_online = 1;
  376. qeth_schedule_recovery(card);
  377. return NULL;
  378. case IPA_CMD_MODCCID:
  379. return cmd;
  380. case IPA_CMD_REGISTER_LOCAL_ADDR:
  381. QETH_DBF_TEXT(TRACE, 3, "irla");
  382. break;
  383. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  384. QETH_DBF_TEXT(TRACE, 3, "urla");
  385. break;
  386. default:
  387. QETH_DBF_MESSAGE(2, "Received data is IPA "
  388. "but not a reply!\n");
  389. break;
  390. }
  391. }
  392. }
  393. return cmd;
  394. }
  395. void qeth_clear_ipacmd_list(struct qeth_card *card)
  396. {
  397. struct qeth_reply *reply, *r;
  398. unsigned long flags;
  399. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  400. spin_lock_irqsave(&card->lock, flags);
  401. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  402. qeth_get_reply(reply);
  403. reply->rc = -EIO;
  404. atomic_inc(&reply->received);
  405. list_del_init(&reply->list);
  406. wake_up(&reply->wait_q);
  407. qeth_put_reply(reply);
  408. }
  409. spin_unlock_irqrestore(&card->lock, flags);
  410. }
  411. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  412. static int qeth_check_idx_response(unsigned char *buffer)
  413. {
  414. if (!buffer)
  415. return 0;
  416. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  417. if ((buffer[2] & 0xc0) == 0xc0) {
  418. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  419. "with cause code 0x%02x%s\n",
  420. buffer[4],
  421. ((buffer[4] == 0x22) ?
  422. " -- try another portname" : ""));
  423. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  424. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  425. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  426. return -EIO;
  427. }
  428. return 0;
  429. }
  430. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  431. __u32 len)
  432. {
  433. struct qeth_card *card;
  434. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  435. card = CARD_FROM_CDEV(channel->ccwdev);
  436. if (channel == &card->read)
  437. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  438. else
  439. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  440. channel->ccw.count = len;
  441. channel->ccw.cda = (__u32) __pa(iob);
  442. }
  443. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  444. {
  445. __u8 index;
  446. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  447. index = channel->io_buf_no;
  448. do {
  449. if (channel->iob[index].state == BUF_STATE_FREE) {
  450. channel->iob[index].state = BUF_STATE_LOCKED;
  451. channel->io_buf_no = (channel->io_buf_no + 1) %
  452. QETH_CMD_BUFFER_NO;
  453. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  454. return channel->iob + index;
  455. }
  456. index = (index + 1) % QETH_CMD_BUFFER_NO;
  457. } while (index != channel->io_buf_no);
  458. return NULL;
  459. }
  460. void qeth_release_buffer(struct qeth_channel *channel,
  461. struct qeth_cmd_buffer *iob)
  462. {
  463. unsigned long flags;
  464. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  465. spin_lock_irqsave(&channel->iob_lock, flags);
  466. memset(iob->data, 0, QETH_BUFSIZE);
  467. iob->state = BUF_STATE_FREE;
  468. iob->callback = qeth_send_control_data_cb;
  469. iob->rc = 0;
  470. spin_unlock_irqrestore(&channel->iob_lock, flags);
  471. }
  472. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  473. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  474. {
  475. struct qeth_cmd_buffer *buffer = NULL;
  476. unsigned long flags;
  477. spin_lock_irqsave(&channel->iob_lock, flags);
  478. buffer = __qeth_get_buffer(channel);
  479. spin_unlock_irqrestore(&channel->iob_lock, flags);
  480. return buffer;
  481. }
  482. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  483. {
  484. struct qeth_cmd_buffer *buffer;
  485. wait_event(channel->wait_q,
  486. ((buffer = qeth_get_buffer(channel)) != NULL));
  487. return buffer;
  488. }
  489. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  490. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  491. {
  492. int cnt;
  493. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  494. qeth_release_buffer(channel, &channel->iob[cnt]);
  495. channel->buf_no = 0;
  496. channel->io_buf_no = 0;
  497. }
  498. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  499. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  500. struct qeth_cmd_buffer *iob)
  501. {
  502. struct qeth_card *card;
  503. struct qeth_reply *reply, *r;
  504. struct qeth_ipa_cmd *cmd;
  505. unsigned long flags;
  506. int keep_reply;
  507. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  508. card = CARD_FROM_CDEV(channel->ccwdev);
  509. if (qeth_check_idx_response(iob->data)) {
  510. qeth_clear_ipacmd_list(card);
  511. if (((iob->data[2] & 0xc0) == 0xc0) && iob->data[4] == 0xf6)
  512. dev_err(&card->gdev->dev,
  513. "The qeth device is not configured "
  514. "for the OSI layer required by z/VM\n");
  515. qeth_schedule_recovery(card);
  516. goto out;
  517. }
  518. cmd = qeth_check_ipa_data(card, iob);
  519. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  520. goto out;
  521. /*in case of OSN : check if cmd is set */
  522. if (card->info.type == QETH_CARD_TYPE_OSN &&
  523. cmd &&
  524. cmd->hdr.command != IPA_CMD_STARTLAN &&
  525. card->osn_info.assist_cb != NULL) {
  526. card->osn_info.assist_cb(card->dev, cmd);
  527. goto out;
  528. }
  529. spin_lock_irqsave(&card->lock, flags);
  530. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  531. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  532. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  533. qeth_get_reply(reply);
  534. list_del_init(&reply->list);
  535. spin_unlock_irqrestore(&card->lock, flags);
  536. keep_reply = 0;
  537. if (reply->callback != NULL) {
  538. if (cmd) {
  539. reply->offset = (__u16)((char *)cmd -
  540. (char *)iob->data);
  541. keep_reply = reply->callback(card,
  542. reply,
  543. (unsigned long)cmd);
  544. } else
  545. keep_reply = reply->callback(card,
  546. reply,
  547. (unsigned long)iob);
  548. }
  549. if (cmd)
  550. reply->rc = (u16) cmd->hdr.return_code;
  551. else if (iob->rc)
  552. reply->rc = iob->rc;
  553. if (keep_reply) {
  554. spin_lock_irqsave(&card->lock, flags);
  555. list_add_tail(&reply->list,
  556. &card->cmd_waiter_list);
  557. spin_unlock_irqrestore(&card->lock, flags);
  558. } else {
  559. atomic_inc(&reply->received);
  560. wake_up(&reply->wait_q);
  561. }
  562. qeth_put_reply(reply);
  563. goto out;
  564. }
  565. }
  566. spin_unlock_irqrestore(&card->lock, flags);
  567. out:
  568. memcpy(&card->seqno.pdu_hdr_ack,
  569. QETH_PDU_HEADER_SEQ_NO(iob->data),
  570. QETH_SEQ_NO_LENGTH);
  571. qeth_release_buffer(channel, iob);
  572. }
  573. static int qeth_setup_channel(struct qeth_channel *channel)
  574. {
  575. int cnt;
  576. QETH_DBF_TEXT(SETUP, 2, "setupch");
  577. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  578. channel->iob[cnt].data = (char *)
  579. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  580. if (channel->iob[cnt].data == NULL)
  581. break;
  582. channel->iob[cnt].state = BUF_STATE_FREE;
  583. channel->iob[cnt].channel = channel;
  584. channel->iob[cnt].callback = qeth_send_control_data_cb;
  585. channel->iob[cnt].rc = 0;
  586. }
  587. if (cnt < QETH_CMD_BUFFER_NO) {
  588. while (cnt-- > 0)
  589. kfree(channel->iob[cnt].data);
  590. return -ENOMEM;
  591. }
  592. channel->buf_no = 0;
  593. channel->io_buf_no = 0;
  594. atomic_set(&channel->irq_pending, 0);
  595. spin_lock_init(&channel->iob_lock);
  596. init_waitqueue_head(&channel->wait_q);
  597. return 0;
  598. }
  599. static int qeth_set_thread_start_bit(struct qeth_card *card,
  600. unsigned long thread)
  601. {
  602. unsigned long flags;
  603. spin_lock_irqsave(&card->thread_mask_lock, flags);
  604. if (!(card->thread_allowed_mask & thread) ||
  605. (card->thread_start_mask & thread)) {
  606. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  607. return -EPERM;
  608. }
  609. card->thread_start_mask |= thread;
  610. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  611. return 0;
  612. }
  613. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  614. {
  615. unsigned long flags;
  616. spin_lock_irqsave(&card->thread_mask_lock, flags);
  617. card->thread_start_mask &= ~thread;
  618. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  619. wake_up(&card->wait_q);
  620. }
  621. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  622. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  623. {
  624. unsigned long flags;
  625. spin_lock_irqsave(&card->thread_mask_lock, flags);
  626. card->thread_running_mask &= ~thread;
  627. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  628. wake_up(&card->wait_q);
  629. }
  630. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  631. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  632. {
  633. unsigned long flags;
  634. int rc = 0;
  635. spin_lock_irqsave(&card->thread_mask_lock, flags);
  636. if (card->thread_start_mask & thread) {
  637. if ((card->thread_allowed_mask & thread) &&
  638. !(card->thread_running_mask & thread)) {
  639. rc = 1;
  640. card->thread_start_mask &= ~thread;
  641. card->thread_running_mask |= thread;
  642. } else
  643. rc = -EPERM;
  644. }
  645. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  646. return rc;
  647. }
  648. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  649. {
  650. int rc = 0;
  651. wait_event(card->wait_q,
  652. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  653. return rc;
  654. }
  655. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  656. void qeth_schedule_recovery(struct qeth_card *card)
  657. {
  658. QETH_DBF_TEXT(TRACE, 2, "startrec");
  659. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  660. schedule_work(&card->kernel_thread_starter);
  661. }
  662. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  663. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  664. {
  665. int dstat, cstat;
  666. char *sense;
  667. sense = (char *) irb->ecw;
  668. cstat = irb->scsw.cmd.cstat;
  669. dstat = irb->scsw.cmd.dstat;
  670. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  671. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  672. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  673. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  674. dev_warn(&cdev->dev, "The qeth device driver "
  675. "failed to recover an error on the device\n");
  676. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x ",
  677. dev_name(&cdev->dev), dstat, cstat);
  678. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  679. 16, 1, irb, 64, 1);
  680. return 1;
  681. }
  682. if (dstat & DEV_STAT_UNIT_CHECK) {
  683. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  684. SENSE_RESETTING_EVENT_FLAG) {
  685. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  686. return 1;
  687. }
  688. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  689. SENSE_COMMAND_REJECT_FLAG) {
  690. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  691. return 1;
  692. }
  693. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  694. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  695. return 1;
  696. }
  697. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  698. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  699. return 0;
  700. }
  701. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  702. return 1;
  703. }
  704. return 0;
  705. }
  706. static long __qeth_check_irb_error(struct ccw_device *cdev,
  707. unsigned long intparm, struct irb *irb)
  708. {
  709. if (!IS_ERR(irb))
  710. return 0;
  711. switch (PTR_ERR(irb)) {
  712. case -EIO:
  713. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  714. dev_name(&cdev->dev));
  715. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  716. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  717. break;
  718. case -ETIMEDOUT:
  719. dev_warn(&cdev->dev, "A hardware operation timed out"
  720. " on the device\n");
  721. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  722. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  723. if (intparm == QETH_RCD_PARM) {
  724. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  725. if (card && (card->data.ccwdev == cdev)) {
  726. card->data.state = CH_STATE_DOWN;
  727. wake_up(&card->wait_q);
  728. }
  729. }
  730. break;
  731. default:
  732. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  733. dev_name(&cdev->dev), PTR_ERR(irb));
  734. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  735. QETH_DBF_TEXT(TRACE, 2, " rc???");
  736. }
  737. return PTR_ERR(irb);
  738. }
  739. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  740. struct irb *irb)
  741. {
  742. int rc;
  743. int cstat, dstat;
  744. struct qeth_cmd_buffer *buffer;
  745. struct qeth_channel *channel;
  746. struct qeth_card *card;
  747. struct qeth_cmd_buffer *iob;
  748. __u8 index;
  749. QETH_DBF_TEXT(TRACE, 5, "irq");
  750. if (__qeth_check_irb_error(cdev, intparm, irb))
  751. return;
  752. cstat = irb->scsw.cmd.cstat;
  753. dstat = irb->scsw.cmd.dstat;
  754. card = CARD_FROM_CDEV(cdev);
  755. if (!card)
  756. return;
  757. if (card->read.ccwdev == cdev) {
  758. channel = &card->read;
  759. QETH_DBF_TEXT(TRACE, 5, "read");
  760. } else if (card->write.ccwdev == cdev) {
  761. channel = &card->write;
  762. QETH_DBF_TEXT(TRACE, 5, "write");
  763. } else {
  764. channel = &card->data;
  765. QETH_DBF_TEXT(TRACE, 5, "data");
  766. }
  767. atomic_set(&channel->irq_pending, 0);
  768. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  769. channel->state = CH_STATE_STOPPED;
  770. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  771. channel->state = CH_STATE_HALTED;
  772. /*let's wake up immediately on data channel*/
  773. if ((channel == &card->data) && (intparm != 0) &&
  774. (intparm != QETH_RCD_PARM))
  775. goto out;
  776. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  777. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  778. /* we don't have to handle this further */
  779. intparm = 0;
  780. }
  781. if (intparm == QETH_HALT_CHANNEL_PARM) {
  782. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  783. /* we don't have to handle this further */
  784. intparm = 0;
  785. }
  786. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  787. (dstat & DEV_STAT_UNIT_CHECK) ||
  788. (cstat)) {
  789. if (irb->esw.esw0.erw.cons) {
  790. dev_warn(&channel->ccwdev->dev,
  791. "The qeth device driver failed to recover "
  792. "an error on the device\n");
  793. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  794. "0x%X dstat 0x%X\n",
  795. dev_name(&channel->ccwdev->dev), cstat, dstat);
  796. print_hex_dump(KERN_WARNING, "qeth: irb ",
  797. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  798. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  799. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  800. }
  801. if (intparm == QETH_RCD_PARM) {
  802. channel->state = CH_STATE_DOWN;
  803. goto out;
  804. }
  805. rc = qeth_get_problem(cdev, irb);
  806. if (rc) {
  807. qeth_clear_ipacmd_list(card);
  808. qeth_schedule_recovery(card);
  809. goto out;
  810. }
  811. }
  812. if (intparm == QETH_RCD_PARM) {
  813. channel->state = CH_STATE_RCD_DONE;
  814. goto out;
  815. }
  816. if (intparm) {
  817. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  818. buffer->state = BUF_STATE_PROCESSED;
  819. }
  820. if (channel == &card->data)
  821. return;
  822. if (channel == &card->read &&
  823. channel->state == CH_STATE_UP)
  824. qeth_issue_next_read(card);
  825. iob = channel->iob;
  826. index = channel->buf_no;
  827. while (iob[index].state == BUF_STATE_PROCESSED) {
  828. if (iob[index].callback != NULL)
  829. iob[index].callback(channel, iob + index);
  830. index = (index + 1) % QETH_CMD_BUFFER_NO;
  831. }
  832. channel->buf_no = index;
  833. out:
  834. wake_up(&card->wait_q);
  835. return;
  836. }
  837. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  838. struct qeth_qdio_out_buffer *buf)
  839. {
  840. int i;
  841. struct sk_buff *skb;
  842. /* is PCI flag set on buffer? */
  843. if (buf->buffer->element[0].flags & 0x40)
  844. atomic_dec(&queue->set_pci_flags_count);
  845. skb = skb_dequeue(&buf->skb_list);
  846. while (skb) {
  847. atomic_dec(&skb->users);
  848. dev_kfree_skb_any(skb);
  849. skb = skb_dequeue(&buf->skb_list);
  850. }
  851. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  852. if (buf->buffer->element[i].addr && buf->is_header[i])
  853. kmem_cache_free(qeth_core_header_cache,
  854. buf->buffer->element[i].addr);
  855. buf->is_header[i] = 0;
  856. buf->buffer->element[i].length = 0;
  857. buf->buffer->element[i].addr = NULL;
  858. buf->buffer->element[i].flags = 0;
  859. }
  860. buf->next_element_to_fill = 0;
  861. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  862. }
  863. void qeth_clear_qdio_buffers(struct qeth_card *card)
  864. {
  865. int i, j;
  866. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  867. /* clear outbound buffers to free skbs */
  868. for (i = 0; i < card->qdio.no_out_queues; ++i)
  869. if (card->qdio.out_qs[i]) {
  870. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  871. qeth_clear_output_buffer(card->qdio.out_qs[i],
  872. &card->qdio.out_qs[i]->bufs[j]);
  873. }
  874. }
  875. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  876. static void qeth_free_buffer_pool(struct qeth_card *card)
  877. {
  878. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  879. int i = 0;
  880. QETH_DBF_TEXT(TRACE, 5, "freepool");
  881. list_for_each_entry_safe(pool_entry, tmp,
  882. &card->qdio.init_pool.entry_list, init_list){
  883. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  884. free_page((unsigned long)pool_entry->elements[i]);
  885. list_del(&pool_entry->init_list);
  886. kfree(pool_entry);
  887. }
  888. }
  889. static void qeth_free_qdio_buffers(struct qeth_card *card)
  890. {
  891. int i, j;
  892. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  893. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  894. QETH_QDIO_UNINITIALIZED)
  895. return;
  896. kfree(card->qdio.in_q);
  897. card->qdio.in_q = NULL;
  898. /* inbound buffer pool */
  899. qeth_free_buffer_pool(card);
  900. /* free outbound qdio_qs */
  901. if (card->qdio.out_qs) {
  902. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  903. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  904. qeth_clear_output_buffer(card->qdio.out_qs[i],
  905. &card->qdio.out_qs[i]->bufs[j]);
  906. kfree(card->qdio.out_qs[i]);
  907. }
  908. kfree(card->qdio.out_qs);
  909. card->qdio.out_qs = NULL;
  910. }
  911. }
  912. static void qeth_clean_channel(struct qeth_channel *channel)
  913. {
  914. int cnt;
  915. QETH_DBF_TEXT(SETUP, 2, "freech");
  916. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  917. kfree(channel->iob[cnt].data);
  918. }
  919. static int qeth_is_1920_device(struct qeth_card *card)
  920. {
  921. int single_queue = 0;
  922. struct ccw_device *ccwdev;
  923. struct channelPath_dsc {
  924. u8 flags;
  925. u8 lsn;
  926. u8 desc;
  927. u8 chpid;
  928. u8 swla;
  929. u8 zeroes;
  930. u8 chla;
  931. u8 chpp;
  932. } *chp_dsc;
  933. QETH_DBF_TEXT(SETUP, 2, "chk_1920");
  934. ccwdev = card->data.ccwdev;
  935. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  936. if (chp_dsc != NULL) {
  937. /* CHPP field bit 6 == 1 -> single queue */
  938. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  939. kfree(chp_dsc);
  940. }
  941. QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
  942. return single_queue;
  943. }
  944. static void qeth_init_qdio_info(struct qeth_card *card)
  945. {
  946. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  947. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  948. /* inbound */
  949. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  950. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  951. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  952. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  953. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  954. }
  955. static void qeth_set_intial_options(struct qeth_card *card)
  956. {
  957. card->options.route4.type = NO_ROUTER;
  958. card->options.route6.type = NO_ROUTER;
  959. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  960. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  961. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  962. card->options.fake_broadcast = 0;
  963. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  964. card->options.performance_stats = 0;
  965. card->options.rx_sg_cb = QETH_RX_SG_CB;
  966. }
  967. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  968. {
  969. unsigned long flags;
  970. int rc = 0;
  971. spin_lock_irqsave(&card->thread_mask_lock, flags);
  972. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  973. (u8) card->thread_start_mask,
  974. (u8) card->thread_allowed_mask,
  975. (u8) card->thread_running_mask);
  976. rc = (card->thread_start_mask & thread);
  977. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  978. return rc;
  979. }
  980. static void qeth_start_kernel_thread(struct work_struct *work)
  981. {
  982. struct qeth_card *card = container_of(work, struct qeth_card,
  983. kernel_thread_starter);
  984. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  985. if (card->read.state != CH_STATE_UP &&
  986. card->write.state != CH_STATE_UP)
  987. return;
  988. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  989. kthread_run(card->discipline.recover, (void *) card,
  990. "qeth_recover");
  991. }
  992. static int qeth_setup_card(struct qeth_card *card)
  993. {
  994. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  995. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  996. card->read.state = CH_STATE_DOWN;
  997. card->write.state = CH_STATE_DOWN;
  998. card->data.state = CH_STATE_DOWN;
  999. card->state = CARD_STATE_DOWN;
  1000. card->lan_online = 0;
  1001. card->use_hard_stop = 0;
  1002. card->dev = NULL;
  1003. spin_lock_init(&card->vlanlock);
  1004. spin_lock_init(&card->mclock);
  1005. card->vlangrp = NULL;
  1006. spin_lock_init(&card->lock);
  1007. spin_lock_init(&card->ip_lock);
  1008. spin_lock_init(&card->thread_mask_lock);
  1009. card->thread_start_mask = 0;
  1010. card->thread_allowed_mask = 0;
  1011. card->thread_running_mask = 0;
  1012. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1013. INIT_LIST_HEAD(&card->ip_list);
  1014. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1015. if (!card->ip_tbd_list) {
  1016. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1017. return -ENOMEM;
  1018. }
  1019. INIT_LIST_HEAD(card->ip_tbd_list);
  1020. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1021. init_waitqueue_head(&card->wait_q);
  1022. /* intial options */
  1023. qeth_set_intial_options(card);
  1024. /* IP address takeover */
  1025. INIT_LIST_HEAD(&card->ipato.entries);
  1026. card->ipato.enabled = 0;
  1027. card->ipato.invert4 = 0;
  1028. card->ipato.invert6 = 0;
  1029. /* init QDIO stuff */
  1030. qeth_init_qdio_info(card);
  1031. return 0;
  1032. }
  1033. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1034. {
  1035. struct qeth_card *card = container_of(slr, struct qeth_card,
  1036. qeth_service_level);
  1037. seq_printf(m, "qeth: %s firmware level %s\n", CARD_BUS_ID(card),
  1038. card->info.mcl_level);
  1039. }
  1040. static struct qeth_card *qeth_alloc_card(void)
  1041. {
  1042. struct qeth_card *card;
  1043. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1044. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1045. if (!card)
  1046. return NULL;
  1047. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1048. if (qeth_setup_channel(&card->read)) {
  1049. kfree(card);
  1050. return NULL;
  1051. }
  1052. if (qeth_setup_channel(&card->write)) {
  1053. qeth_clean_channel(&card->read);
  1054. kfree(card);
  1055. return NULL;
  1056. }
  1057. card->options.layer2 = -1;
  1058. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1059. register_service_level(&card->qeth_service_level);
  1060. return card;
  1061. }
  1062. static int qeth_determine_card_type(struct qeth_card *card)
  1063. {
  1064. int i = 0;
  1065. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1066. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1067. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1068. while (known_devices[i][4]) {
  1069. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1070. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1071. card->info.type = known_devices[i][4];
  1072. card->qdio.no_out_queues = known_devices[i][8];
  1073. card->info.is_multicast_different = known_devices[i][9];
  1074. if (qeth_is_1920_device(card)) {
  1075. dev_info(&card->gdev->dev,
  1076. "Priority Queueing not supported\n");
  1077. card->qdio.no_out_queues = 1;
  1078. card->qdio.default_out_queue = 0;
  1079. }
  1080. return 0;
  1081. }
  1082. i++;
  1083. }
  1084. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1085. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1086. "unknown type\n");
  1087. return -ENOENT;
  1088. }
  1089. static int qeth_clear_channel(struct qeth_channel *channel)
  1090. {
  1091. unsigned long flags;
  1092. struct qeth_card *card;
  1093. int rc;
  1094. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1095. card = CARD_FROM_CDEV(channel->ccwdev);
  1096. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1097. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1098. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1099. if (rc)
  1100. return rc;
  1101. rc = wait_event_interruptible_timeout(card->wait_q,
  1102. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1103. if (rc == -ERESTARTSYS)
  1104. return rc;
  1105. if (channel->state != CH_STATE_STOPPED)
  1106. return -ETIME;
  1107. channel->state = CH_STATE_DOWN;
  1108. return 0;
  1109. }
  1110. static int qeth_halt_channel(struct qeth_channel *channel)
  1111. {
  1112. unsigned long flags;
  1113. struct qeth_card *card;
  1114. int rc;
  1115. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1116. card = CARD_FROM_CDEV(channel->ccwdev);
  1117. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1118. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1119. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1120. if (rc)
  1121. return rc;
  1122. rc = wait_event_interruptible_timeout(card->wait_q,
  1123. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1124. if (rc == -ERESTARTSYS)
  1125. return rc;
  1126. if (channel->state != CH_STATE_HALTED)
  1127. return -ETIME;
  1128. return 0;
  1129. }
  1130. static int qeth_halt_channels(struct qeth_card *card)
  1131. {
  1132. int rc1 = 0, rc2 = 0, rc3 = 0;
  1133. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1134. rc1 = qeth_halt_channel(&card->read);
  1135. rc2 = qeth_halt_channel(&card->write);
  1136. rc3 = qeth_halt_channel(&card->data);
  1137. if (rc1)
  1138. return rc1;
  1139. if (rc2)
  1140. return rc2;
  1141. return rc3;
  1142. }
  1143. static int qeth_clear_channels(struct qeth_card *card)
  1144. {
  1145. int rc1 = 0, rc2 = 0, rc3 = 0;
  1146. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1147. rc1 = qeth_clear_channel(&card->read);
  1148. rc2 = qeth_clear_channel(&card->write);
  1149. rc3 = qeth_clear_channel(&card->data);
  1150. if (rc1)
  1151. return rc1;
  1152. if (rc2)
  1153. return rc2;
  1154. return rc3;
  1155. }
  1156. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1157. {
  1158. int rc = 0;
  1159. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1160. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1161. if (halt)
  1162. rc = qeth_halt_channels(card);
  1163. if (rc)
  1164. return rc;
  1165. return qeth_clear_channels(card);
  1166. }
  1167. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1168. {
  1169. int rc = 0;
  1170. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1171. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1172. QETH_QDIO_CLEANING)) {
  1173. case QETH_QDIO_ESTABLISHED:
  1174. if (card->info.type == QETH_CARD_TYPE_IQD)
  1175. rc = qdio_cleanup(CARD_DDEV(card),
  1176. QDIO_FLAG_CLEANUP_USING_HALT);
  1177. else
  1178. rc = qdio_cleanup(CARD_DDEV(card),
  1179. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1180. if (rc)
  1181. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1182. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1183. break;
  1184. case QETH_QDIO_CLEANING:
  1185. return rc;
  1186. default:
  1187. break;
  1188. }
  1189. rc = qeth_clear_halt_card(card, use_halt);
  1190. if (rc)
  1191. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1192. card->state = CARD_STATE_DOWN;
  1193. return rc;
  1194. }
  1195. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1196. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1197. int *length)
  1198. {
  1199. struct ciw *ciw;
  1200. char *rcd_buf;
  1201. int ret;
  1202. struct qeth_channel *channel = &card->data;
  1203. unsigned long flags;
  1204. /*
  1205. * scan for RCD command in extended SenseID data
  1206. */
  1207. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1208. if (!ciw || ciw->cmd == 0)
  1209. return -EOPNOTSUPP;
  1210. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1211. if (!rcd_buf)
  1212. return -ENOMEM;
  1213. channel->ccw.cmd_code = ciw->cmd;
  1214. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1215. channel->ccw.count = ciw->count;
  1216. channel->ccw.flags = CCW_FLAG_SLI;
  1217. channel->state = CH_STATE_RCD;
  1218. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1219. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1220. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1221. QETH_RCD_TIMEOUT);
  1222. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1223. if (!ret)
  1224. wait_event(card->wait_q,
  1225. (channel->state == CH_STATE_RCD_DONE ||
  1226. channel->state == CH_STATE_DOWN));
  1227. if (channel->state == CH_STATE_DOWN)
  1228. ret = -EIO;
  1229. else
  1230. channel->state = CH_STATE_DOWN;
  1231. if (ret) {
  1232. kfree(rcd_buf);
  1233. *buffer = NULL;
  1234. *length = 0;
  1235. } else {
  1236. *length = ciw->count;
  1237. *buffer = rcd_buf;
  1238. }
  1239. return ret;
  1240. }
  1241. static int qeth_get_unitaddr(struct qeth_card *card)
  1242. {
  1243. int length;
  1244. char *prcd;
  1245. int rc;
  1246. QETH_DBF_TEXT(SETUP, 2, "getunit");
  1247. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  1248. if (rc) {
  1249. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  1250. dev_name(&card->gdev->dev), rc);
  1251. return rc;
  1252. }
  1253. card->info.chpid = prcd[30];
  1254. card->info.unit_addr2 = prcd[31];
  1255. card->info.cula = prcd[63];
  1256. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1257. (prcd[0x11] == _ascebc['M']));
  1258. kfree(prcd);
  1259. return 0;
  1260. }
  1261. static void qeth_init_tokens(struct qeth_card *card)
  1262. {
  1263. card->token.issuer_rm_w = 0x00010103UL;
  1264. card->token.cm_filter_w = 0x00010108UL;
  1265. card->token.cm_connection_w = 0x0001010aUL;
  1266. card->token.ulp_filter_w = 0x0001010bUL;
  1267. card->token.ulp_connection_w = 0x0001010dUL;
  1268. }
  1269. static void qeth_init_func_level(struct qeth_card *card)
  1270. {
  1271. if (card->ipato.enabled) {
  1272. if (card->info.type == QETH_CARD_TYPE_IQD)
  1273. card->info.func_level =
  1274. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1275. else
  1276. card->info.func_level =
  1277. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1278. } else {
  1279. if (card->info.type == QETH_CARD_TYPE_IQD)
  1280. /*FIXME:why do we have same values for dis and ena for
  1281. osae??? */
  1282. card->info.func_level =
  1283. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1284. else
  1285. card->info.func_level =
  1286. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1287. }
  1288. }
  1289. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1290. void (*idx_reply_cb)(struct qeth_channel *,
  1291. struct qeth_cmd_buffer *))
  1292. {
  1293. struct qeth_cmd_buffer *iob;
  1294. unsigned long flags;
  1295. int rc;
  1296. struct qeth_card *card;
  1297. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1298. card = CARD_FROM_CDEV(channel->ccwdev);
  1299. iob = qeth_get_buffer(channel);
  1300. iob->callback = idx_reply_cb;
  1301. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1302. channel->ccw.count = QETH_BUFSIZE;
  1303. channel->ccw.cda = (__u32) __pa(iob->data);
  1304. wait_event(card->wait_q,
  1305. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1306. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1307. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1308. rc = ccw_device_start(channel->ccwdev,
  1309. &channel->ccw, (addr_t) iob, 0, 0);
  1310. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1311. if (rc) {
  1312. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1313. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1314. atomic_set(&channel->irq_pending, 0);
  1315. wake_up(&card->wait_q);
  1316. return rc;
  1317. }
  1318. rc = wait_event_interruptible_timeout(card->wait_q,
  1319. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1320. if (rc == -ERESTARTSYS)
  1321. return rc;
  1322. if (channel->state != CH_STATE_UP) {
  1323. rc = -ETIME;
  1324. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1325. qeth_clear_cmd_buffers(channel);
  1326. } else
  1327. rc = 0;
  1328. return rc;
  1329. }
  1330. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1331. void (*idx_reply_cb)(struct qeth_channel *,
  1332. struct qeth_cmd_buffer *))
  1333. {
  1334. struct qeth_card *card;
  1335. struct qeth_cmd_buffer *iob;
  1336. unsigned long flags;
  1337. __u16 temp;
  1338. __u8 tmp;
  1339. int rc;
  1340. struct ccw_dev_id temp_devid;
  1341. card = CARD_FROM_CDEV(channel->ccwdev);
  1342. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1343. iob = qeth_get_buffer(channel);
  1344. iob->callback = idx_reply_cb;
  1345. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1346. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1347. channel->ccw.cda = (__u32) __pa(iob->data);
  1348. if (channel == &card->write) {
  1349. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1350. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1351. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1352. card->seqno.trans_hdr++;
  1353. } else {
  1354. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1355. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1356. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1357. }
  1358. tmp = ((__u8)card->info.portno) | 0x80;
  1359. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1360. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1361. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1362. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1363. &card->info.func_level, sizeof(__u16));
  1364. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1365. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1366. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1367. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1368. wait_event(card->wait_q,
  1369. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1370. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1371. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1372. rc = ccw_device_start(channel->ccwdev,
  1373. &channel->ccw, (addr_t) iob, 0, 0);
  1374. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1375. if (rc) {
  1376. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1377. rc);
  1378. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1379. atomic_set(&channel->irq_pending, 0);
  1380. wake_up(&card->wait_q);
  1381. return rc;
  1382. }
  1383. rc = wait_event_interruptible_timeout(card->wait_q,
  1384. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1385. if (rc == -ERESTARTSYS)
  1386. return rc;
  1387. if (channel->state != CH_STATE_ACTIVATING) {
  1388. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1389. " failed to recover an error on the device\n");
  1390. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1391. dev_name(&channel->ccwdev->dev));
  1392. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1393. qeth_clear_cmd_buffers(channel);
  1394. return -ETIME;
  1395. }
  1396. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1397. }
  1398. static int qeth_peer_func_level(int level)
  1399. {
  1400. if ((level & 0xff) == 8)
  1401. return (level & 0xff) + 0x400;
  1402. if (((level >> 8) & 3) == 1)
  1403. return (level & 0xff) + 0x200;
  1404. return level;
  1405. }
  1406. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1407. struct qeth_cmd_buffer *iob)
  1408. {
  1409. struct qeth_card *card;
  1410. __u16 temp;
  1411. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1412. if (channel->state == CH_STATE_DOWN) {
  1413. channel->state = CH_STATE_ACTIVATING;
  1414. goto out;
  1415. }
  1416. card = CARD_FROM_CDEV(channel->ccwdev);
  1417. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1418. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1419. dev_err(&card->write.ccwdev->dev,
  1420. "The adapter is used exclusively by another "
  1421. "host\n");
  1422. else
  1423. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1424. " negative reply\n",
  1425. dev_name(&card->write.ccwdev->dev));
  1426. goto out;
  1427. }
  1428. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1429. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1430. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1431. "function level mismatch (sent: 0x%x, received: "
  1432. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1433. card->info.func_level, temp);
  1434. goto out;
  1435. }
  1436. channel->state = CH_STATE_UP;
  1437. out:
  1438. qeth_release_buffer(channel, iob);
  1439. }
  1440. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1441. struct qeth_cmd_buffer *iob)
  1442. {
  1443. struct qeth_card *card;
  1444. __u16 temp;
  1445. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1446. if (channel->state == CH_STATE_DOWN) {
  1447. channel->state = CH_STATE_ACTIVATING;
  1448. goto out;
  1449. }
  1450. card = CARD_FROM_CDEV(channel->ccwdev);
  1451. if (qeth_check_idx_response(iob->data))
  1452. goto out;
  1453. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1454. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1455. dev_err(&card->write.ccwdev->dev,
  1456. "The adapter is used exclusively by another "
  1457. "host\n");
  1458. else
  1459. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1460. " negative reply\n",
  1461. dev_name(&card->read.ccwdev->dev));
  1462. goto out;
  1463. }
  1464. /**
  1465. * temporary fix for microcode bug
  1466. * to revert it,replace OR by AND
  1467. */
  1468. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1469. (card->info.type == QETH_CARD_TYPE_OSAE))
  1470. card->info.portname_required = 1;
  1471. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1472. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1473. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1474. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1475. dev_name(&card->read.ccwdev->dev),
  1476. card->info.func_level, temp);
  1477. goto out;
  1478. }
  1479. memcpy(&card->token.issuer_rm_r,
  1480. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1481. QETH_MPC_TOKEN_LENGTH);
  1482. memcpy(&card->info.mcl_level[0],
  1483. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1484. channel->state = CH_STATE_UP;
  1485. out:
  1486. qeth_release_buffer(channel, iob);
  1487. }
  1488. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1489. struct qeth_cmd_buffer *iob)
  1490. {
  1491. qeth_setup_ccw(&card->write, iob->data, len);
  1492. iob->callback = qeth_release_buffer;
  1493. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1494. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1495. card->seqno.trans_hdr++;
  1496. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1497. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1498. card->seqno.pdu_hdr++;
  1499. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1500. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1501. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1502. }
  1503. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1504. int qeth_send_control_data(struct qeth_card *card, int len,
  1505. struct qeth_cmd_buffer *iob,
  1506. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1507. unsigned long),
  1508. void *reply_param)
  1509. {
  1510. int rc;
  1511. unsigned long flags;
  1512. struct qeth_reply *reply = NULL;
  1513. unsigned long timeout, event_timeout;
  1514. struct qeth_ipa_cmd *cmd;
  1515. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1516. reply = qeth_alloc_reply(card);
  1517. if (!reply) {
  1518. return -ENOMEM;
  1519. }
  1520. reply->callback = reply_cb;
  1521. reply->param = reply_param;
  1522. if (card->state == CARD_STATE_DOWN)
  1523. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1524. else
  1525. reply->seqno = card->seqno.ipa++;
  1526. init_waitqueue_head(&reply->wait_q);
  1527. spin_lock_irqsave(&card->lock, flags);
  1528. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1529. spin_unlock_irqrestore(&card->lock, flags);
  1530. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1531. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1532. qeth_prepare_control_data(card, len, iob);
  1533. if (IS_IPA(iob->data))
  1534. event_timeout = QETH_IPA_TIMEOUT;
  1535. else
  1536. event_timeout = QETH_TIMEOUT;
  1537. timeout = jiffies + event_timeout;
  1538. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1539. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1540. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1541. (addr_t) iob, 0, 0);
  1542. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1543. if (rc) {
  1544. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1545. "ccw_device_start rc = %i\n",
  1546. dev_name(&card->write.ccwdev->dev), rc);
  1547. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1548. spin_lock_irqsave(&card->lock, flags);
  1549. list_del_init(&reply->list);
  1550. qeth_put_reply(reply);
  1551. spin_unlock_irqrestore(&card->lock, flags);
  1552. qeth_release_buffer(iob->channel, iob);
  1553. atomic_set(&card->write.irq_pending, 0);
  1554. wake_up(&card->wait_q);
  1555. return rc;
  1556. }
  1557. /* we have only one long running ipassist, since we can ensure
  1558. process context of this command we can sleep */
  1559. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1560. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1561. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1562. if (!wait_event_timeout(reply->wait_q,
  1563. atomic_read(&reply->received), event_timeout))
  1564. goto time_err;
  1565. } else {
  1566. while (!atomic_read(&reply->received)) {
  1567. if (time_after(jiffies, timeout))
  1568. goto time_err;
  1569. cpu_relax();
  1570. };
  1571. }
  1572. rc = reply->rc;
  1573. qeth_put_reply(reply);
  1574. return rc;
  1575. time_err:
  1576. spin_lock_irqsave(&reply->card->lock, flags);
  1577. list_del_init(&reply->list);
  1578. spin_unlock_irqrestore(&reply->card->lock, flags);
  1579. reply->rc = -ETIME;
  1580. atomic_inc(&reply->received);
  1581. wake_up(&reply->wait_q);
  1582. rc = reply->rc;
  1583. qeth_put_reply(reply);
  1584. return rc;
  1585. }
  1586. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1587. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1588. unsigned long data)
  1589. {
  1590. struct qeth_cmd_buffer *iob;
  1591. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1592. iob = (struct qeth_cmd_buffer *) data;
  1593. memcpy(&card->token.cm_filter_r,
  1594. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1595. QETH_MPC_TOKEN_LENGTH);
  1596. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1597. return 0;
  1598. }
  1599. static int qeth_cm_enable(struct qeth_card *card)
  1600. {
  1601. int rc;
  1602. struct qeth_cmd_buffer *iob;
  1603. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1604. iob = qeth_wait_for_buffer(&card->write);
  1605. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1606. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1607. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1608. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1609. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1610. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1611. qeth_cm_enable_cb, NULL);
  1612. return rc;
  1613. }
  1614. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1615. unsigned long data)
  1616. {
  1617. struct qeth_cmd_buffer *iob;
  1618. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1619. iob = (struct qeth_cmd_buffer *) data;
  1620. memcpy(&card->token.cm_connection_r,
  1621. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1622. QETH_MPC_TOKEN_LENGTH);
  1623. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1624. return 0;
  1625. }
  1626. static int qeth_cm_setup(struct qeth_card *card)
  1627. {
  1628. int rc;
  1629. struct qeth_cmd_buffer *iob;
  1630. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1631. iob = qeth_wait_for_buffer(&card->write);
  1632. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1633. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1634. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1635. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1636. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1637. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1638. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1639. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1640. qeth_cm_setup_cb, NULL);
  1641. return rc;
  1642. }
  1643. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1644. {
  1645. switch (card->info.type) {
  1646. case QETH_CARD_TYPE_UNKNOWN:
  1647. return 1500;
  1648. case QETH_CARD_TYPE_IQD:
  1649. return card->info.max_mtu;
  1650. case QETH_CARD_TYPE_OSAE:
  1651. switch (card->info.link_type) {
  1652. case QETH_LINK_TYPE_HSTR:
  1653. case QETH_LINK_TYPE_LANE_TR:
  1654. return 2000;
  1655. default:
  1656. return 1492;
  1657. }
  1658. default:
  1659. return 1500;
  1660. }
  1661. }
  1662. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1663. {
  1664. switch (cardtype) {
  1665. case QETH_CARD_TYPE_UNKNOWN:
  1666. case QETH_CARD_TYPE_OSAE:
  1667. case QETH_CARD_TYPE_OSN:
  1668. return 61440;
  1669. case QETH_CARD_TYPE_IQD:
  1670. return 57344;
  1671. default:
  1672. return 1500;
  1673. }
  1674. }
  1675. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1676. {
  1677. switch (cardtype) {
  1678. case QETH_CARD_TYPE_IQD:
  1679. return 1;
  1680. default:
  1681. return 0;
  1682. }
  1683. }
  1684. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1685. {
  1686. switch (framesize) {
  1687. case 0x4000:
  1688. return 8192;
  1689. case 0x6000:
  1690. return 16384;
  1691. case 0xa000:
  1692. return 32768;
  1693. case 0xffff:
  1694. return 57344;
  1695. default:
  1696. return 0;
  1697. }
  1698. }
  1699. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1700. {
  1701. switch (card->info.type) {
  1702. case QETH_CARD_TYPE_OSAE:
  1703. return ((mtu >= 576) && (mtu <= 61440));
  1704. case QETH_CARD_TYPE_IQD:
  1705. return ((mtu >= 576) &&
  1706. (mtu <= card->info.max_mtu + 4096 - 32));
  1707. case QETH_CARD_TYPE_OSN:
  1708. case QETH_CARD_TYPE_UNKNOWN:
  1709. default:
  1710. return 1;
  1711. }
  1712. }
  1713. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1714. unsigned long data)
  1715. {
  1716. __u16 mtu, framesize;
  1717. __u16 len;
  1718. __u8 link_type;
  1719. struct qeth_cmd_buffer *iob;
  1720. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1721. iob = (struct qeth_cmd_buffer *) data;
  1722. memcpy(&card->token.ulp_filter_r,
  1723. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1724. QETH_MPC_TOKEN_LENGTH);
  1725. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1726. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1727. mtu = qeth_get_mtu_outof_framesize(framesize);
  1728. if (!mtu) {
  1729. iob->rc = -EINVAL;
  1730. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1731. return 0;
  1732. }
  1733. card->info.max_mtu = mtu;
  1734. card->info.initial_mtu = mtu;
  1735. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1736. } else {
  1737. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1738. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1739. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1740. }
  1741. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1742. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1743. memcpy(&link_type,
  1744. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1745. card->info.link_type = link_type;
  1746. } else
  1747. card->info.link_type = 0;
  1748. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1749. return 0;
  1750. }
  1751. static int qeth_ulp_enable(struct qeth_card *card)
  1752. {
  1753. int rc;
  1754. char prot_type;
  1755. struct qeth_cmd_buffer *iob;
  1756. /*FIXME: trace view callbacks*/
  1757. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1758. iob = qeth_wait_for_buffer(&card->write);
  1759. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1760. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1761. (__u8) card->info.portno;
  1762. if (card->options.layer2)
  1763. if (card->info.type == QETH_CARD_TYPE_OSN)
  1764. prot_type = QETH_PROT_OSN2;
  1765. else
  1766. prot_type = QETH_PROT_LAYER2;
  1767. else
  1768. prot_type = QETH_PROT_TCPIP;
  1769. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1770. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1771. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1772. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1773. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1774. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1775. card->info.portname, 9);
  1776. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1777. qeth_ulp_enable_cb, NULL);
  1778. return rc;
  1779. }
  1780. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1781. unsigned long data)
  1782. {
  1783. struct qeth_cmd_buffer *iob;
  1784. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1785. iob = (struct qeth_cmd_buffer *) data;
  1786. memcpy(&card->token.ulp_connection_r,
  1787. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1788. QETH_MPC_TOKEN_LENGTH);
  1789. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1790. return 0;
  1791. }
  1792. static int qeth_ulp_setup(struct qeth_card *card)
  1793. {
  1794. int rc;
  1795. __u16 temp;
  1796. struct qeth_cmd_buffer *iob;
  1797. struct ccw_dev_id dev_id;
  1798. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1799. iob = qeth_wait_for_buffer(&card->write);
  1800. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1801. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1802. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1803. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1804. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1805. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1806. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1807. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1808. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1809. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1810. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1811. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1812. qeth_ulp_setup_cb, NULL);
  1813. return rc;
  1814. }
  1815. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1816. {
  1817. int i, j;
  1818. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1819. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1820. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1821. return 0;
  1822. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1823. GFP_KERNEL);
  1824. if (!card->qdio.in_q)
  1825. goto out_nomem;
  1826. QETH_DBF_TEXT(SETUP, 2, "inq");
  1827. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1828. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1829. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1830. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1831. card->qdio.in_q->bufs[i].buffer =
  1832. &card->qdio.in_q->qdio_bufs[i];
  1833. /* inbound buffer pool */
  1834. if (qeth_alloc_buffer_pool(card))
  1835. goto out_freeinq;
  1836. /* outbound */
  1837. card->qdio.out_qs =
  1838. kmalloc(card->qdio.no_out_queues *
  1839. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1840. if (!card->qdio.out_qs)
  1841. goto out_freepool;
  1842. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1843. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1844. GFP_KERNEL);
  1845. if (!card->qdio.out_qs[i])
  1846. goto out_freeoutq;
  1847. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1848. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1849. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1850. card->qdio.out_qs[i]->queue_no = i;
  1851. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1852. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1853. card->qdio.out_qs[i]->bufs[j].buffer =
  1854. &card->qdio.out_qs[i]->qdio_bufs[j];
  1855. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1856. skb_list);
  1857. lockdep_set_class(
  1858. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1859. &qdio_out_skb_queue_key);
  1860. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1861. }
  1862. }
  1863. return 0;
  1864. out_freeoutq:
  1865. while (i > 0)
  1866. kfree(card->qdio.out_qs[--i]);
  1867. kfree(card->qdio.out_qs);
  1868. card->qdio.out_qs = NULL;
  1869. out_freepool:
  1870. qeth_free_buffer_pool(card);
  1871. out_freeinq:
  1872. kfree(card->qdio.in_q);
  1873. card->qdio.in_q = NULL;
  1874. out_nomem:
  1875. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1876. return -ENOMEM;
  1877. }
  1878. static void qeth_create_qib_param_field(struct qeth_card *card,
  1879. char *param_field)
  1880. {
  1881. param_field[0] = _ascebc['P'];
  1882. param_field[1] = _ascebc['C'];
  1883. param_field[2] = _ascebc['I'];
  1884. param_field[3] = _ascebc['T'];
  1885. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1886. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1887. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1888. }
  1889. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1890. char *param_field)
  1891. {
  1892. param_field[16] = _ascebc['B'];
  1893. param_field[17] = _ascebc['L'];
  1894. param_field[18] = _ascebc['K'];
  1895. param_field[19] = _ascebc['T'];
  1896. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1897. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1898. *((unsigned int *) (&param_field[28])) =
  1899. card->info.blkt.inter_packet_jumbo;
  1900. }
  1901. static int qeth_qdio_activate(struct qeth_card *card)
  1902. {
  1903. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1904. return qdio_activate(CARD_DDEV(card));
  1905. }
  1906. static int qeth_dm_act(struct qeth_card *card)
  1907. {
  1908. int rc;
  1909. struct qeth_cmd_buffer *iob;
  1910. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1911. iob = qeth_wait_for_buffer(&card->write);
  1912. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1913. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1914. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1915. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1916. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1917. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1918. return rc;
  1919. }
  1920. static int qeth_mpc_initialize(struct qeth_card *card)
  1921. {
  1922. int rc;
  1923. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1924. rc = qeth_issue_next_read(card);
  1925. if (rc) {
  1926. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1927. return rc;
  1928. }
  1929. rc = qeth_cm_enable(card);
  1930. if (rc) {
  1931. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1932. goto out_qdio;
  1933. }
  1934. rc = qeth_cm_setup(card);
  1935. if (rc) {
  1936. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1937. goto out_qdio;
  1938. }
  1939. rc = qeth_ulp_enable(card);
  1940. if (rc) {
  1941. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1942. goto out_qdio;
  1943. }
  1944. rc = qeth_ulp_setup(card);
  1945. if (rc) {
  1946. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1947. goto out_qdio;
  1948. }
  1949. rc = qeth_alloc_qdio_buffers(card);
  1950. if (rc) {
  1951. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1952. goto out_qdio;
  1953. }
  1954. rc = qeth_qdio_establish(card);
  1955. if (rc) {
  1956. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1957. qeth_free_qdio_buffers(card);
  1958. goto out_qdio;
  1959. }
  1960. rc = qeth_qdio_activate(card);
  1961. if (rc) {
  1962. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1963. goto out_qdio;
  1964. }
  1965. rc = qeth_dm_act(card);
  1966. if (rc) {
  1967. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1968. goto out_qdio;
  1969. }
  1970. return 0;
  1971. out_qdio:
  1972. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1973. return rc;
  1974. }
  1975. static void qeth_print_status_with_portname(struct qeth_card *card)
  1976. {
  1977. char dbf_text[15];
  1978. int i;
  1979. sprintf(dbf_text, "%s", card->info.portname + 1);
  1980. for (i = 0; i < 8; i++)
  1981. dbf_text[i] =
  1982. (char) _ebcasc[(__u8) dbf_text[i]];
  1983. dbf_text[8] = 0;
  1984. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1985. "with link type %s (portname: %s)\n",
  1986. qeth_get_cardname(card),
  1987. (card->info.mcl_level[0]) ? " (level: " : "",
  1988. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1989. (card->info.mcl_level[0]) ? ")" : "",
  1990. qeth_get_cardname_short(card),
  1991. dbf_text);
  1992. }
  1993. static void qeth_print_status_no_portname(struct qeth_card *card)
  1994. {
  1995. if (card->info.portname[0])
  1996. dev_info(&card->gdev->dev, "Device is a%s "
  1997. "card%s%s%s\nwith link type %s "
  1998. "(no portname needed by interface).\n",
  1999. qeth_get_cardname(card),
  2000. (card->info.mcl_level[0]) ? " (level: " : "",
  2001. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2002. (card->info.mcl_level[0]) ? ")" : "",
  2003. qeth_get_cardname_short(card));
  2004. else
  2005. dev_info(&card->gdev->dev, "Device is a%s "
  2006. "card%s%s%s\nwith link type %s.\n",
  2007. qeth_get_cardname(card),
  2008. (card->info.mcl_level[0]) ? " (level: " : "",
  2009. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2010. (card->info.mcl_level[0]) ? ")" : "",
  2011. qeth_get_cardname_short(card));
  2012. }
  2013. void qeth_print_status_message(struct qeth_card *card)
  2014. {
  2015. switch (card->info.type) {
  2016. case QETH_CARD_TYPE_OSAE:
  2017. /* VM will use a non-zero first character
  2018. * to indicate a HiperSockets like reporting
  2019. * of the level OSA sets the first character to zero
  2020. * */
  2021. if (!card->info.mcl_level[0]) {
  2022. sprintf(card->info.mcl_level, "%02x%02x",
  2023. card->info.mcl_level[2],
  2024. card->info.mcl_level[3]);
  2025. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2026. break;
  2027. }
  2028. /* fallthrough */
  2029. case QETH_CARD_TYPE_IQD:
  2030. if ((card->info.guestlan) ||
  2031. (card->info.mcl_level[0] & 0x80)) {
  2032. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2033. card->info.mcl_level[0]];
  2034. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2035. card->info.mcl_level[1]];
  2036. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2037. card->info.mcl_level[2]];
  2038. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2039. card->info.mcl_level[3]];
  2040. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2041. }
  2042. break;
  2043. default:
  2044. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2045. }
  2046. if (card->info.portname_required)
  2047. qeth_print_status_with_portname(card);
  2048. else
  2049. qeth_print_status_no_portname(card);
  2050. }
  2051. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2052. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2053. {
  2054. struct qeth_buffer_pool_entry *entry;
  2055. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2056. list_for_each_entry(entry,
  2057. &card->qdio.init_pool.entry_list, init_list) {
  2058. qeth_put_buffer_pool_entry(card, entry);
  2059. }
  2060. }
  2061. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2062. struct qeth_card *card)
  2063. {
  2064. struct list_head *plh;
  2065. struct qeth_buffer_pool_entry *entry;
  2066. int i, free;
  2067. struct page *page;
  2068. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2069. return NULL;
  2070. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2071. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2072. free = 1;
  2073. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2074. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2075. free = 0;
  2076. break;
  2077. }
  2078. }
  2079. if (free) {
  2080. list_del_init(&entry->list);
  2081. return entry;
  2082. }
  2083. }
  2084. /* no free buffer in pool so take first one and swap pages */
  2085. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2086. struct qeth_buffer_pool_entry, list);
  2087. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2088. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2089. page = alloc_page(GFP_ATOMIC);
  2090. if (!page) {
  2091. return NULL;
  2092. } else {
  2093. free_page((unsigned long)entry->elements[i]);
  2094. entry->elements[i] = page_address(page);
  2095. if (card->options.performance_stats)
  2096. card->perf_stats.sg_alloc_page_rx++;
  2097. }
  2098. }
  2099. }
  2100. list_del_init(&entry->list);
  2101. return entry;
  2102. }
  2103. static int qeth_init_input_buffer(struct qeth_card *card,
  2104. struct qeth_qdio_buffer *buf)
  2105. {
  2106. struct qeth_buffer_pool_entry *pool_entry;
  2107. int i;
  2108. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2109. if (!pool_entry)
  2110. return 1;
  2111. /*
  2112. * since the buffer is accessed only from the input_tasklet
  2113. * there shouldn't be a need to synchronize; also, since we use
  2114. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2115. * buffers
  2116. */
  2117. buf->pool_entry = pool_entry;
  2118. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2119. buf->buffer->element[i].length = PAGE_SIZE;
  2120. buf->buffer->element[i].addr = pool_entry->elements[i];
  2121. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2122. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2123. else
  2124. buf->buffer->element[i].flags = 0;
  2125. }
  2126. return 0;
  2127. }
  2128. int qeth_init_qdio_queues(struct qeth_card *card)
  2129. {
  2130. int i, j;
  2131. int rc;
  2132. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2133. /* inbound queue */
  2134. memset(card->qdio.in_q->qdio_bufs, 0,
  2135. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2136. qeth_initialize_working_pool_list(card);
  2137. /*give only as many buffers to hardware as we have buffer pool entries*/
  2138. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2139. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2140. card->qdio.in_q->next_buf_to_init =
  2141. card->qdio.in_buf_pool.buf_count - 1;
  2142. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2143. card->qdio.in_buf_pool.buf_count - 1);
  2144. if (rc) {
  2145. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2146. return rc;
  2147. }
  2148. /* outbound queue */
  2149. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2150. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2151. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2152. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2153. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2154. &card->qdio.out_qs[i]->bufs[j]);
  2155. }
  2156. card->qdio.out_qs[i]->card = card;
  2157. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2158. card->qdio.out_qs[i]->do_pack = 0;
  2159. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2160. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2161. atomic_set(&card->qdio.out_qs[i]->state,
  2162. QETH_OUT_Q_UNLOCKED);
  2163. }
  2164. return 0;
  2165. }
  2166. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2167. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2168. {
  2169. switch (link_type) {
  2170. case QETH_LINK_TYPE_HSTR:
  2171. return 2;
  2172. default:
  2173. return 1;
  2174. }
  2175. }
  2176. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2177. struct qeth_ipa_cmd *cmd, __u8 command,
  2178. enum qeth_prot_versions prot)
  2179. {
  2180. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2181. cmd->hdr.command = command;
  2182. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2183. cmd->hdr.seqno = card->seqno.ipa;
  2184. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2185. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2186. if (card->options.layer2)
  2187. cmd->hdr.prim_version_no = 2;
  2188. else
  2189. cmd->hdr.prim_version_no = 1;
  2190. cmd->hdr.param_count = 1;
  2191. cmd->hdr.prot_version = prot;
  2192. cmd->hdr.ipa_supported = 0;
  2193. cmd->hdr.ipa_enabled = 0;
  2194. }
  2195. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2196. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2197. {
  2198. struct qeth_cmd_buffer *iob;
  2199. struct qeth_ipa_cmd *cmd;
  2200. iob = qeth_wait_for_buffer(&card->write);
  2201. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2202. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2203. return iob;
  2204. }
  2205. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2206. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2207. char prot_type)
  2208. {
  2209. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2210. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2211. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2212. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2213. }
  2214. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2215. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2216. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2217. unsigned long),
  2218. void *reply_param)
  2219. {
  2220. int rc;
  2221. char prot_type;
  2222. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2223. if (card->options.layer2)
  2224. if (card->info.type == QETH_CARD_TYPE_OSN)
  2225. prot_type = QETH_PROT_OSN2;
  2226. else
  2227. prot_type = QETH_PROT_LAYER2;
  2228. else
  2229. prot_type = QETH_PROT_TCPIP;
  2230. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2231. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2232. iob, reply_cb, reply_param);
  2233. return rc;
  2234. }
  2235. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2236. static int qeth_send_startstoplan(struct qeth_card *card,
  2237. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2238. {
  2239. int rc;
  2240. struct qeth_cmd_buffer *iob;
  2241. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2242. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2243. return rc;
  2244. }
  2245. int qeth_send_startlan(struct qeth_card *card)
  2246. {
  2247. int rc;
  2248. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2249. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2250. return rc;
  2251. }
  2252. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2253. int qeth_send_stoplan(struct qeth_card *card)
  2254. {
  2255. int rc = 0;
  2256. /*
  2257. * TODO: according to the IPA format document page 14,
  2258. * TCP/IP (we!) never issue a STOPLAN
  2259. * is this right ?!?
  2260. */
  2261. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2262. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2263. return rc;
  2264. }
  2265. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2266. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2267. struct qeth_reply *reply, unsigned long data)
  2268. {
  2269. struct qeth_ipa_cmd *cmd;
  2270. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2271. cmd = (struct qeth_ipa_cmd *) data;
  2272. if (cmd->hdr.return_code == 0)
  2273. cmd->hdr.return_code =
  2274. cmd->data.setadapterparms.hdr.return_code;
  2275. return 0;
  2276. }
  2277. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2278. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2279. struct qeth_reply *reply, unsigned long data)
  2280. {
  2281. struct qeth_ipa_cmd *cmd;
  2282. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2283. cmd = (struct qeth_ipa_cmd *) data;
  2284. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2285. card->info.link_type =
  2286. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2287. card->options.adp.supported_funcs =
  2288. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2289. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2290. }
  2291. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2292. __u32 command, __u32 cmdlen)
  2293. {
  2294. struct qeth_cmd_buffer *iob;
  2295. struct qeth_ipa_cmd *cmd;
  2296. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2297. QETH_PROT_IPV4);
  2298. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2299. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2300. cmd->data.setadapterparms.hdr.command_code = command;
  2301. cmd->data.setadapterparms.hdr.used_total = 1;
  2302. cmd->data.setadapterparms.hdr.seq_no = 1;
  2303. return iob;
  2304. }
  2305. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2306. int qeth_query_setadapterparms(struct qeth_card *card)
  2307. {
  2308. int rc;
  2309. struct qeth_cmd_buffer *iob;
  2310. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2311. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2312. sizeof(struct qeth_ipacmd_setadpparms));
  2313. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2314. return rc;
  2315. }
  2316. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2317. int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
  2318. const char *dbftext)
  2319. {
  2320. if (qdio_error) {
  2321. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2322. QETH_DBF_TEXT(QERR, 2, dbftext);
  2323. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2324. buf->element[15].flags & 0xff);
  2325. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2326. buf->element[14].flags & 0xff);
  2327. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2328. return 1;
  2329. }
  2330. return 0;
  2331. }
  2332. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2333. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2334. {
  2335. struct qeth_qdio_q *queue = card->qdio.in_q;
  2336. int count;
  2337. int i;
  2338. int rc;
  2339. int newcount = 0;
  2340. count = (index < queue->next_buf_to_init)?
  2341. card->qdio.in_buf_pool.buf_count -
  2342. (queue->next_buf_to_init - index) :
  2343. card->qdio.in_buf_pool.buf_count -
  2344. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2345. /* only requeue at a certain threshold to avoid SIGAs */
  2346. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2347. for (i = queue->next_buf_to_init;
  2348. i < queue->next_buf_to_init + count; ++i) {
  2349. if (qeth_init_input_buffer(card,
  2350. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2351. break;
  2352. } else {
  2353. newcount++;
  2354. }
  2355. }
  2356. if (newcount < count) {
  2357. /* we are in memory shortage so we switch back to
  2358. traditional skb allocation and drop packages */
  2359. atomic_set(&card->force_alloc_skb, 3);
  2360. count = newcount;
  2361. } else {
  2362. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2363. }
  2364. /*
  2365. * according to old code it should be avoided to requeue all
  2366. * 128 buffers in order to benefit from PCI avoidance.
  2367. * this function keeps at least one buffer (the buffer at
  2368. * 'index') un-requeued -> this buffer is the first buffer that
  2369. * will be requeued the next time
  2370. */
  2371. if (card->options.performance_stats) {
  2372. card->perf_stats.inbound_do_qdio_cnt++;
  2373. card->perf_stats.inbound_do_qdio_start_time =
  2374. qeth_get_micros();
  2375. }
  2376. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2377. queue->next_buf_to_init, count);
  2378. if (card->options.performance_stats)
  2379. card->perf_stats.inbound_do_qdio_time +=
  2380. qeth_get_micros() -
  2381. card->perf_stats.inbound_do_qdio_start_time;
  2382. if (rc) {
  2383. dev_warn(&card->gdev->dev,
  2384. "QDIO reported an error, rc=%i\n", rc);
  2385. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2386. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2387. }
  2388. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2389. QDIO_MAX_BUFFERS_PER_Q;
  2390. }
  2391. }
  2392. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2393. static int qeth_handle_send_error(struct qeth_card *card,
  2394. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2395. {
  2396. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2397. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2398. qeth_check_qdio_errors(buffer->buffer, qdio_err, "qouterr");
  2399. if (!qdio_err)
  2400. return QETH_SEND_ERROR_NONE;
  2401. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2402. return QETH_SEND_ERROR_RETRY;
  2403. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2404. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2405. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2406. (u16)qdio_err, (u8)sbalf15);
  2407. return QETH_SEND_ERROR_LINK_FAILURE;
  2408. }
  2409. /*
  2410. * Switched to packing state if the number of used buffers on a queue
  2411. * reaches a certain limit.
  2412. */
  2413. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2414. {
  2415. if (!queue->do_pack) {
  2416. if (atomic_read(&queue->used_buffers)
  2417. >= QETH_HIGH_WATERMARK_PACK){
  2418. /* switch non-PACKING -> PACKING */
  2419. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2420. if (queue->card->options.performance_stats)
  2421. queue->card->perf_stats.sc_dp_p++;
  2422. queue->do_pack = 1;
  2423. }
  2424. }
  2425. }
  2426. /*
  2427. * Switches from packing to non-packing mode. If there is a packing
  2428. * buffer on the queue this buffer will be prepared to be flushed.
  2429. * In that case 1 is returned to inform the caller. If no buffer
  2430. * has to be flushed, zero is returned.
  2431. */
  2432. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2433. {
  2434. struct qeth_qdio_out_buffer *buffer;
  2435. int flush_count = 0;
  2436. if (queue->do_pack) {
  2437. if (atomic_read(&queue->used_buffers)
  2438. <= QETH_LOW_WATERMARK_PACK) {
  2439. /* switch PACKING -> non-PACKING */
  2440. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2441. if (queue->card->options.performance_stats)
  2442. queue->card->perf_stats.sc_p_dp++;
  2443. queue->do_pack = 0;
  2444. /* flush packing buffers */
  2445. buffer = &queue->bufs[queue->next_buf_to_fill];
  2446. if ((atomic_read(&buffer->state) ==
  2447. QETH_QDIO_BUF_EMPTY) &&
  2448. (buffer->next_element_to_fill > 0)) {
  2449. atomic_set(&buffer->state,
  2450. QETH_QDIO_BUF_PRIMED);
  2451. flush_count++;
  2452. queue->next_buf_to_fill =
  2453. (queue->next_buf_to_fill + 1) %
  2454. QDIO_MAX_BUFFERS_PER_Q;
  2455. }
  2456. }
  2457. }
  2458. return flush_count;
  2459. }
  2460. /*
  2461. * Called to flush a packing buffer if no more pci flags are on the queue.
  2462. * Checks if there is a packing buffer and prepares it to be flushed.
  2463. * In that case returns 1, otherwise zero.
  2464. */
  2465. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2466. {
  2467. struct qeth_qdio_out_buffer *buffer;
  2468. buffer = &queue->bufs[queue->next_buf_to_fill];
  2469. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2470. (buffer->next_element_to_fill > 0)) {
  2471. /* it's a packing buffer */
  2472. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2473. queue->next_buf_to_fill =
  2474. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2475. return 1;
  2476. }
  2477. return 0;
  2478. }
  2479. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2480. int count)
  2481. {
  2482. struct qeth_qdio_out_buffer *buf;
  2483. int rc;
  2484. int i;
  2485. unsigned int qdio_flags;
  2486. for (i = index; i < index + count; ++i) {
  2487. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2488. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2489. SBAL_FLAGS_LAST_ENTRY;
  2490. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2491. continue;
  2492. if (!queue->do_pack) {
  2493. if ((atomic_read(&queue->used_buffers) >=
  2494. (QETH_HIGH_WATERMARK_PACK -
  2495. QETH_WATERMARK_PACK_FUZZ)) &&
  2496. !atomic_read(&queue->set_pci_flags_count)) {
  2497. /* it's likely that we'll go to packing
  2498. * mode soon */
  2499. atomic_inc(&queue->set_pci_flags_count);
  2500. buf->buffer->element[0].flags |= 0x40;
  2501. }
  2502. } else {
  2503. if (!atomic_read(&queue->set_pci_flags_count)) {
  2504. /*
  2505. * there's no outstanding PCI any more, so we
  2506. * have to request a PCI to be sure the the PCI
  2507. * will wake at some time in the future then we
  2508. * can flush packed buffers that might still be
  2509. * hanging around, which can happen if no
  2510. * further send was requested by the stack
  2511. */
  2512. atomic_inc(&queue->set_pci_flags_count);
  2513. buf->buffer->element[0].flags |= 0x40;
  2514. }
  2515. }
  2516. }
  2517. queue->card->dev->trans_start = jiffies;
  2518. if (queue->card->options.performance_stats) {
  2519. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2520. queue->card->perf_stats.outbound_do_qdio_start_time =
  2521. qeth_get_micros();
  2522. }
  2523. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2524. if (atomic_read(&queue->set_pci_flags_count))
  2525. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2526. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2527. queue->queue_no, index, count);
  2528. if (queue->card->options.performance_stats)
  2529. queue->card->perf_stats.outbound_do_qdio_time +=
  2530. qeth_get_micros() -
  2531. queue->card->perf_stats.outbound_do_qdio_start_time;
  2532. if (rc) {
  2533. queue->card->stats.tx_errors += count;
  2534. /* ignore temporary SIGA errors without busy condition */
  2535. if (rc == QDIO_ERROR_SIGA_TARGET)
  2536. return;
  2537. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2538. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2539. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2540. /* this must not happen under normal circumstances. if it
  2541. * happens something is really wrong -> recover */
  2542. qeth_schedule_recovery(queue->card);
  2543. return;
  2544. }
  2545. atomic_add(count, &queue->used_buffers);
  2546. if (queue->card->options.performance_stats)
  2547. queue->card->perf_stats.bufs_sent += count;
  2548. }
  2549. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2550. {
  2551. int index;
  2552. int flush_cnt = 0;
  2553. int q_was_packing = 0;
  2554. /*
  2555. * check if weed have to switch to non-packing mode or if
  2556. * we have to get a pci flag out on the queue
  2557. */
  2558. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2559. !atomic_read(&queue->set_pci_flags_count)) {
  2560. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2561. QETH_OUT_Q_UNLOCKED) {
  2562. /*
  2563. * If we get in here, there was no action in
  2564. * do_send_packet. So, we check if there is a
  2565. * packing buffer to be flushed here.
  2566. */
  2567. netif_stop_queue(queue->card->dev);
  2568. index = queue->next_buf_to_fill;
  2569. q_was_packing = queue->do_pack;
  2570. /* queue->do_pack may change */
  2571. barrier();
  2572. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2573. if (!flush_cnt &&
  2574. !atomic_read(&queue->set_pci_flags_count))
  2575. flush_cnt +=
  2576. qeth_flush_buffers_on_no_pci(queue);
  2577. if (queue->card->options.performance_stats &&
  2578. q_was_packing)
  2579. queue->card->perf_stats.bufs_sent_pack +=
  2580. flush_cnt;
  2581. if (flush_cnt)
  2582. qeth_flush_buffers(queue, index, flush_cnt);
  2583. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2584. }
  2585. }
  2586. }
  2587. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2588. unsigned int qdio_error, int __queue, int first_element,
  2589. int count, unsigned long card_ptr)
  2590. {
  2591. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2592. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2593. struct qeth_qdio_out_buffer *buffer;
  2594. int i;
  2595. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2596. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2597. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2598. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2599. netif_stop_queue(card->dev);
  2600. qeth_schedule_recovery(card);
  2601. return;
  2602. }
  2603. if (card->options.performance_stats) {
  2604. card->perf_stats.outbound_handler_cnt++;
  2605. card->perf_stats.outbound_handler_start_time =
  2606. qeth_get_micros();
  2607. }
  2608. for (i = first_element; i < (first_element + count); ++i) {
  2609. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2610. qeth_handle_send_error(card, buffer, qdio_error);
  2611. qeth_clear_output_buffer(queue, buffer);
  2612. }
  2613. atomic_sub(count, &queue->used_buffers);
  2614. /* check if we need to do something on this outbound queue */
  2615. if (card->info.type != QETH_CARD_TYPE_IQD)
  2616. qeth_check_outbound_queue(queue);
  2617. netif_wake_queue(queue->card->dev);
  2618. if (card->options.performance_stats)
  2619. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2620. card->perf_stats.outbound_handler_start_time;
  2621. }
  2622. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2623. int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
  2624. {
  2625. int cast_type = RTN_UNSPEC;
  2626. if (card->info.type == QETH_CARD_TYPE_OSN)
  2627. return cast_type;
  2628. if (skb->dst && skb->dst->neighbour) {
  2629. cast_type = skb->dst->neighbour->type;
  2630. if ((cast_type == RTN_BROADCAST) ||
  2631. (cast_type == RTN_MULTICAST) ||
  2632. (cast_type == RTN_ANYCAST))
  2633. return cast_type;
  2634. else
  2635. return RTN_UNSPEC;
  2636. }
  2637. /* try something else */
  2638. if (skb->protocol == ETH_P_IPV6)
  2639. return (skb_network_header(skb)[24] == 0xff) ?
  2640. RTN_MULTICAST : 0;
  2641. else if (skb->protocol == ETH_P_IP)
  2642. return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
  2643. RTN_MULTICAST : 0;
  2644. /* ... */
  2645. if (!memcmp(skb->data, skb->dev->broadcast, 6))
  2646. return RTN_BROADCAST;
  2647. else {
  2648. u16 hdr_mac;
  2649. hdr_mac = *((u16 *)skb->data);
  2650. /* tr multicast? */
  2651. switch (card->info.link_type) {
  2652. case QETH_LINK_TYPE_HSTR:
  2653. case QETH_LINK_TYPE_LANE_TR:
  2654. if ((hdr_mac == QETH_TR_MAC_NC) ||
  2655. (hdr_mac == QETH_TR_MAC_C))
  2656. return RTN_MULTICAST;
  2657. break;
  2658. /* eth or so multicast? */
  2659. default:
  2660. if ((hdr_mac == QETH_ETH_MAC_V4) ||
  2661. (hdr_mac == QETH_ETH_MAC_V6))
  2662. return RTN_MULTICAST;
  2663. }
  2664. }
  2665. return cast_type;
  2666. }
  2667. EXPORT_SYMBOL_GPL(qeth_get_cast_type);
  2668. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2669. int ipv, int cast_type)
  2670. {
  2671. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2672. return card->qdio.default_out_queue;
  2673. switch (card->qdio.no_out_queues) {
  2674. case 4:
  2675. if (cast_type && card->info.is_multicast_different)
  2676. return card->info.is_multicast_different &
  2677. (card->qdio.no_out_queues - 1);
  2678. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2679. const u8 tos = ip_hdr(skb)->tos;
  2680. if (card->qdio.do_prio_queueing ==
  2681. QETH_PRIO_Q_ING_TOS) {
  2682. if (tos & IP_TOS_NOTIMPORTANT)
  2683. return 3;
  2684. if (tos & IP_TOS_HIGHRELIABILITY)
  2685. return 2;
  2686. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2687. return 1;
  2688. if (tos & IP_TOS_LOWDELAY)
  2689. return 0;
  2690. }
  2691. if (card->qdio.do_prio_queueing ==
  2692. QETH_PRIO_Q_ING_PREC)
  2693. return 3 - (tos >> 6);
  2694. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2695. /* TODO: IPv6!!! */
  2696. }
  2697. return card->qdio.default_out_queue;
  2698. case 1: /* fallthrough for single-out-queue 1920-device */
  2699. default:
  2700. return card->qdio.default_out_queue;
  2701. }
  2702. }
  2703. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2704. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2705. struct sk_buff *skb, int elems)
  2706. {
  2707. int elements_needed = 0;
  2708. if (skb_shinfo(skb)->nr_frags > 0)
  2709. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2710. if (elements_needed == 0)
  2711. elements_needed = 1 + (((((unsigned long) skb->data) %
  2712. PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
  2713. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2714. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2715. "(Number=%d / Length=%d). Discarded.\n",
  2716. (elements_needed+elems), skb->len);
  2717. return 0;
  2718. }
  2719. return elements_needed;
  2720. }
  2721. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2722. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2723. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2724. int offset)
  2725. {
  2726. int length = skb->len;
  2727. int length_here;
  2728. int element;
  2729. char *data;
  2730. int first_lap ;
  2731. element = *next_element_to_fill;
  2732. data = skb->data;
  2733. first_lap = (is_tso == 0 ? 1 : 0);
  2734. if (offset >= 0) {
  2735. data = skb->data + offset;
  2736. length -= offset;
  2737. first_lap = 0;
  2738. }
  2739. while (length > 0) {
  2740. /* length_here is the remaining amount of data in this page */
  2741. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2742. if (length < length_here)
  2743. length_here = length;
  2744. buffer->element[element].addr = data;
  2745. buffer->element[element].length = length_here;
  2746. length -= length_here;
  2747. if (!length) {
  2748. if (first_lap)
  2749. buffer->element[element].flags = 0;
  2750. else
  2751. buffer->element[element].flags =
  2752. SBAL_FLAGS_LAST_FRAG;
  2753. } else {
  2754. if (first_lap)
  2755. buffer->element[element].flags =
  2756. SBAL_FLAGS_FIRST_FRAG;
  2757. else
  2758. buffer->element[element].flags =
  2759. SBAL_FLAGS_MIDDLE_FRAG;
  2760. }
  2761. data += length_here;
  2762. element++;
  2763. first_lap = 0;
  2764. }
  2765. *next_element_to_fill = element;
  2766. }
  2767. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2768. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2769. struct qeth_hdr *hdr, int offset, int hd_len)
  2770. {
  2771. struct qdio_buffer *buffer;
  2772. int flush_cnt = 0, hdr_len, large_send = 0;
  2773. buffer = buf->buffer;
  2774. atomic_inc(&skb->users);
  2775. skb_queue_tail(&buf->skb_list, skb);
  2776. /*check first on TSO ....*/
  2777. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2778. int element = buf->next_element_to_fill;
  2779. hdr_len = sizeof(struct qeth_hdr_tso) +
  2780. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2781. /*fill first buffer entry only with header information */
  2782. buffer->element[element].addr = skb->data;
  2783. buffer->element[element].length = hdr_len;
  2784. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2785. buf->next_element_to_fill++;
  2786. skb->data += hdr_len;
  2787. skb->len -= hdr_len;
  2788. large_send = 1;
  2789. }
  2790. if (offset >= 0) {
  2791. int element = buf->next_element_to_fill;
  2792. buffer->element[element].addr = hdr;
  2793. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2794. hd_len;
  2795. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2796. buf->is_header[element] = 1;
  2797. buf->next_element_to_fill++;
  2798. }
  2799. if (skb_shinfo(skb)->nr_frags == 0)
  2800. __qeth_fill_buffer(skb, buffer, large_send,
  2801. (int *)&buf->next_element_to_fill, offset);
  2802. else
  2803. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2804. (int *)&buf->next_element_to_fill);
  2805. if (!queue->do_pack) {
  2806. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2807. /* set state to PRIMED -> will be flushed */
  2808. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2809. flush_cnt = 1;
  2810. } else {
  2811. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2812. if (queue->card->options.performance_stats)
  2813. queue->card->perf_stats.skbs_sent_pack++;
  2814. if (buf->next_element_to_fill >=
  2815. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2816. /*
  2817. * packed buffer if full -> set state PRIMED
  2818. * -> will be flushed
  2819. */
  2820. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2821. flush_cnt = 1;
  2822. }
  2823. }
  2824. return flush_cnt;
  2825. }
  2826. int qeth_do_send_packet_fast(struct qeth_card *card,
  2827. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2828. struct qeth_hdr *hdr, int elements_needed,
  2829. int offset, int hd_len)
  2830. {
  2831. struct qeth_qdio_out_buffer *buffer;
  2832. int index;
  2833. /* spin until we get the queue ... */
  2834. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2835. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2836. /* ... now we've got the queue */
  2837. index = queue->next_buf_to_fill;
  2838. buffer = &queue->bufs[queue->next_buf_to_fill];
  2839. /*
  2840. * check if buffer is empty to make sure that we do not 'overtake'
  2841. * ourselves and try to fill a buffer that is already primed
  2842. */
  2843. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2844. goto out;
  2845. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2846. QDIO_MAX_BUFFERS_PER_Q;
  2847. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2848. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2849. qeth_flush_buffers(queue, index, 1);
  2850. return 0;
  2851. out:
  2852. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2853. return -EBUSY;
  2854. }
  2855. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2856. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2857. struct sk_buff *skb, struct qeth_hdr *hdr,
  2858. int elements_needed)
  2859. {
  2860. struct qeth_qdio_out_buffer *buffer;
  2861. int start_index;
  2862. int flush_count = 0;
  2863. int do_pack = 0;
  2864. int tmp;
  2865. int rc = 0;
  2866. /* spin until we get the queue ... */
  2867. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2868. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2869. start_index = queue->next_buf_to_fill;
  2870. buffer = &queue->bufs[queue->next_buf_to_fill];
  2871. /*
  2872. * check if buffer is empty to make sure that we do not 'overtake'
  2873. * ourselves and try to fill a buffer that is already primed
  2874. */
  2875. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2876. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2877. return -EBUSY;
  2878. }
  2879. /* check if we need to switch packing state of this queue */
  2880. qeth_switch_to_packing_if_needed(queue);
  2881. if (queue->do_pack) {
  2882. do_pack = 1;
  2883. /* does packet fit in current buffer? */
  2884. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2885. buffer->next_element_to_fill) < elements_needed) {
  2886. /* ... no -> set state PRIMED */
  2887. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2888. flush_count++;
  2889. queue->next_buf_to_fill =
  2890. (queue->next_buf_to_fill + 1) %
  2891. QDIO_MAX_BUFFERS_PER_Q;
  2892. buffer = &queue->bufs[queue->next_buf_to_fill];
  2893. /* we did a step forward, so check buffer state
  2894. * again */
  2895. if (atomic_read(&buffer->state) !=
  2896. QETH_QDIO_BUF_EMPTY) {
  2897. qeth_flush_buffers(queue, start_index,
  2898. flush_count);
  2899. atomic_set(&queue->state,
  2900. QETH_OUT_Q_UNLOCKED);
  2901. return -EBUSY;
  2902. }
  2903. }
  2904. }
  2905. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2906. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2907. QDIO_MAX_BUFFERS_PER_Q;
  2908. flush_count += tmp;
  2909. if (flush_count)
  2910. qeth_flush_buffers(queue, start_index, flush_count);
  2911. else if (!atomic_read(&queue->set_pci_flags_count))
  2912. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2913. /*
  2914. * queue->state will go from LOCKED -> UNLOCKED or from
  2915. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2916. * (switch packing state or flush buffer to get another pci flag out).
  2917. * In that case we will enter this loop
  2918. */
  2919. while (atomic_dec_return(&queue->state)) {
  2920. flush_count = 0;
  2921. start_index = queue->next_buf_to_fill;
  2922. /* check if we can go back to non-packing state */
  2923. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2924. /*
  2925. * check if we need to flush a packing buffer to get a pci
  2926. * flag out on the queue
  2927. */
  2928. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2929. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2930. if (flush_count)
  2931. qeth_flush_buffers(queue, start_index, flush_count);
  2932. }
  2933. /* at this point the queue is UNLOCKED again */
  2934. if (queue->card->options.performance_stats && do_pack)
  2935. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2936. return rc;
  2937. }
  2938. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2939. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2940. struct qeth_reply *reply, unsigned long data)
  2941. {
  2942. struct qeth_ipa_cmd *cmd;
  2943. struct qeth_ipacmd_setadpparms *setparms;
  2944. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  2945. cmd = (struct qeth_ipa_cmd *) data;
  2946. setparms = &(cmd->data.setadapterparms);
  2947. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2948. if (cmd->hdr.return_code) {
  2949. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2950. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2951. }
  2952. card->info.promisc_mode = setparms->data.mode;
  2953. return 0;
  2954. }
  2955. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2956. {
  2957. enum qeth_ipa_promisc_modes mode;
  2958. struct net_device *dev = card->dev;
  2959. struct qeth_cmd_buffer *iob;
  2960. struct qeth_ipa_cmd *cmd;
  2961. QETH_DBF_TEXT(TRACE, 4, "setprom");
  2962. if (((dev->flags & IFF_PROMISC) &&
  2963. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2964. (!(dev->flags & IFF_PROMISC) &&
  2965. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  2966. return;
  2967. mode = SET_PROMISC_MODE_OFF;
  2968. if (dev->flags & IFF_PROMISC)
  2969. mode = SET_PROMISC_MODE_ON;
  2970. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  2971. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  2972. sizeof(struct qeth_ipacmd_setadpparms));
  2973. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  2974. cmd->data.setadapterparms.data.mode = mode;
  2975. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  2976. }
  2977. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  2978. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  2979. {
  2980. struct qeth_card *card;
  2981. char dbf_text[15];
  2982. card = dev->ml_priv;
  2983. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  2984. sprintf(dbf_text, "%8x", new_mtu);
  2985. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  2986. if (new_mtu < 64)
  2987. return -EINVAL;
  2988. if (new_mtu > 65535)
  2989. return -EINVAL;
  2990. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  2991. (!qeth_mtu_is_valid(card, new_mtu)))
  2992. return -EINVAL;
  2993. dev->mtu = new_mtu;
  2994. return 0;
  2995. }
  2996. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  2997. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  2998. {
  2999. struct qeth_card *card;
  3000. card = dev->ml_priv;
  3001. QETH_DBF_TEXT(TRACE, 5, "getstat");
  3002. return &card->stats;
  3003. }
  3004. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3005. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3006. struct qeth_reply *reply, unsigned long data)
  3007. {
  3008. struct qeth_ipa_cmd *cmd;
  3009. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  3010. cmd = (struct qeth_ipa_cmd *) data;
  3011. if (!card->options.layer2 ||
  3012. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3013. memcpy(card->dev->dev_addr,
  3014. &cmd->data.setadapterparms.data.change_addr.addr,
  3015. OSA_ADDR_LEN);
  3016. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3017. }
  3018. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3019. return 0;
  3020. }
  3021. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3022. {
  3023. int rc;
  3024. struct qeth_cmd_buffer *iob;
  3025. struct qeth_ipa_cmd *cmd;
  3026. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  3027. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3028. sizeof(struct qeth_ipacmd_setadpparms));
  3029. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3030. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3031. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3032. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3033. card->dev->dev_addr, OSA_ADDR_LEN);
  3034. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3035. NULL);
  3036. return rc;
  3037. }
  3038. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3039. void qeth_tx_timeout(struct net_device *dev)
  3040. {
  3041. struct qeth_card *card;
  3042. card = dev->ml_priv;
  3043. card->stats.tx_errors++;
  3044. qeth_schedule_recovery(card);
  3045. }
  3046. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3047. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3048. {
  3049. struct qeth_card *card = dev->ml_priv;
  3050. int rc = 0;
  3051. switch (regnum) {
  3052. case MII_BMCR: /* Basic mode control register */
  3053. rc = BMCR_FULLDPLX;
  3054. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3055. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3056. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3057. rc |= BMCR_SPEED100;
  3058. break;
  3059. case MII_BMSR: /* Basic mode status register */
  3060. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3061. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3062. BMSR_100BASE4;
  3063. break;
  3064. case MII_PHYSID1: /* PHYS ID 1 */
  3065. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3066. dev->dev_addr[2];
  3067. rc = (rc >> 5) & 0xFFFF;
  3068. break;
  3069. case MII_PHYSID2: /* PHYS ID 2 */
  3070. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3071. break;
  3072. case MII_ADVERTISE: /* Advertisement control reg */
  3073. rc = ADVERTISE_ALL;
  3074. break;
  3075. case MII_LPA: /* Link partner ability reg */
  3076. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3077. LPA_100BASE4 | LPA_LPACK;
  3078. break;
  3079. case MII_EXPANSION: /* Expansion register */
  3080. break;
  3081. case MII_DCOUNTER: /* disconnect counter */
  3082. break;
  3083. case MII_FCSCOUNTER: /* false carrier counter */
  3084. break;
  3085. case MII_NWAYTEST: /* N-way auto-neg test register */
  3086. break;
  3087. case MII_RERRCOUNTER: /* rx error counter */
  3088. rc = card->stats.rx_errors;
  3089. break;
  3090. case MII_SREVISION: /* silicon revision */
  3091. break;
  3092. case MII_RESV1: /* reserved 1 */
  3093. break;
  3094. case MII_LBRERROR: /* loopback, rx, bypass error */
  3095. break;
  3096. case MII_PHYADDR: /* physical address */
  3097. break;
  3098. case MII_RESV2: /* reserved 2 */
  3099. break;
  3100. case MII_TPISTATUS: /* TPI status for 10mbps */
  3101. break;
  3102. case MII_NCONFIG: /* network interface config */
  3103. break;
  3104. default:
  3105. break;
  3106. }
  3107. return rc;
  3108. }
  3109. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3110. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3111. struct qeth_cmd_buffer *iob, int len,
  3112. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3113. unsigned long),
  3114. void *reply_param)
  3115. {
  3116. u16 s1, s2;
  3117. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3118. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3119. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3120. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3121. /* adjust PDU length fields in IPA_PDU_HEADER */
  3122. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3123. s2 = (u32) len;
  3124. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3125. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3126. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3127. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3128. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3129. reply_cb, reply_param);
  3130. }
  3131. static int qeth_snmp_command_cb(struct qeth_card *card,
  3132. struct qeth_reply *reply, unsigned long sdata)
  3133. {
  3134. struct qeth_ipa_cmd *cmd;
  3135. struct qeth_arp_query_info *qinfo;
  3136. struct qeth_snmp_cmd *snmp;
  3137. unsigned char *data;
  3138. __u16 data_len;
  3139. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3140. cmd = (struct qeth_ipa_cmd *) sdata;
  3141. data = (unsigned char *)((char *)cmd - reply->offset);
  3142. qinfo = (struct qeth_arp_query_info *) reply->param;
  3143. snmp = &cmd->data.setadapterparms.data.snmp;
  3144. if (cmd->hdr.return_code) {
  3145. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3146. return 0;
  3147. }
  3148. if (cmd->data.setadapterparms.hdr.return_code) {
  3149. cmd->hdr.return_code =
  3150. cmd->data.setadapterparms.hdr.return_code;
  3151. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3152. return 0;
  3153. }
  3154. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3155. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3156. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3157. else
  3158. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3159. /* check if there is enough room in userspace */
  3160. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3161. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3162. cmd->hdr.return_code = -ENOMEM;
  3163. return 0;
  3164. }
  3165. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3166. cmd->data.setadapterparms.hdr.used_total);
  3167. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3168. cmd->data.setadapterparms.hdr.seq_no);
  3169. /*copy entries to user buffer*/
  3170. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3171. memcpy(qinfo->udata + qinfo->udata_offset,
  3172. (char *)snmp,
  3173. data_len + offsetof(struct qeth_snmp_cmd, data));
  3174. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3175. } else {
  3176. memcpy(qinfo->udata + qinfo->udata_offset,
  3177. (char *)&snmp->request, data_len);
  3178. }
  3179. qinfo->udata_offset += data_len;
  3180. /* check if all replies received ... */
  3181. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3182. cmd->data.setadapterparms.hdr.used_total);
  3183. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3184. cmd->data.setadapterparms.hdr.seq_no);
  3185. if (cmd->data.setadapterparms.hdr.seq_no <
  3186. cmd->data.setadapterparms.hdr.used_total)
  3187. return 1;
  3188. return 0;
  3189. }
  3190. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3191. {
  3192. struct qeth_cmd_buffer *iob;
  3193. struct qeth_ipa_cmd *cmd;
  3194. struct qeth_snmp_ureq *ureq;
  3195. int req_len;
  3196. struct qeth_arp_query_info qinfo = {0, };
  3197. int rc = 0;
  3198. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3199. if (card->info.guestlan)
  3200. return -EOPNOTSUPP;
  3201. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3202. (!card->options.layer2)) {
  3203. return -EOPNOTSUPP;
  3204. }
  3205. /* skip 4 bytes (data_len struct member) to get req_len */
  3206. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3207. return -EFAULT;
  3208. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3209. if (!ureq) {
  3210. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3211. return -ENOMEM;
  3212. }
  3213. if (copy_from_user(ureq, udata,
  3214. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3215. kfree(ureq);
  3216. return -EFAULT;
  3217. }
  3218. qinfo.udata_len = ureq->hdr.data_len;
  3219. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3220. if (!qinfo.udata) {
  3221. kfree(ureq);
  3222. return -ENOMEM;
  3223. }
  3224. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3225. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3226. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3227. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3228. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3229. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3230. qeth_snmp_command_cb, (void *)&qinfo);
  3231. if (rc)
  3232. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3233. QETH_CARD_IFNAME(card), rc);
  3234. else {
  3235. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3236. rc = -EFAULT;
  3237. }
  3238. kfree(ureq);
  3239. kfree(qinfo.udata);
  3240. return rc;
  3241. }
  3242. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3243. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3244. {
  3245. switch (card->info.type) {
  3246. case QETH_CARD_TYPE_IQD:
  3247. return 2;
  3248. default:
  3249. return 0;
  3250. }
  3251. }
  3252. static int qeth_qdio_establish(struct qeth_card *card)
  3253. {
  3254. struct qdio_initialize init_data;
  3255. char *qib_param_field;
  3256. struct qdio_buffer **in_sbal_ptrs;
  3257. struct qdio_buffer **out_sbal_ptrs;
  3258. int i, j, k;
  3259. int rc = 0;
  3260. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3261. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3262. GFP_KERNEL);
  3263. if (!qib_param_field)
  3264. return -ENOMEM;
  3265. qeth_create_qib_param_field(card, qib_param_field);
  3266. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3267. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3268. GFP_KERNEL);
  3269. if (!in_sbal_ptrs) {
  3270. kfree(qib_param_field);
  3271. return -ENOMEM;
  3272. }
  3273. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3274. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3275. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3276. out_sbal_ptrs =
  3277. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3278. sizeof(void *), GFP_KERNEL);
  3279. if (!out_sbal_ptrs) {
  3280. kfree(in_sbal_ptrs);
  3281. kfree(qib_param_field);
  3282. return -ENOMEM;
  3283. }
  3284. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3285. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3286. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3287. card->qdio.out_qs[i]->bufs[j].buffer);
  3288. }
  3289. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3290. init_data.cdev = CARD_DDEV(card);
  3291. init_data.q_format = qeth_get_qdio_q_format(card);
  3292. init_data.qib_param_field_format = 0;
  3293. init_data.qib_param_field = qib_param_field;
  3294. init_data.no_input_qs = 1;
  3295. init_data.no_output_qs = card->qdio.no_out_queues;
  3296. init_data.input_handler = card->discipline.input_handler;
  3297. init_data.output_handler = card->discipline.output_handler;
  3298. init_data.int_parm = (unsigned long) card;
  3299. init_data.flags = QDIO_INBOUND_0COPY_SBALS |
  3300. QDIO_OUTBOUND_0COPY_SBALS |
  3301. QDIO_USE_OUTBOUND_PCIS;
  3302. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3303. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3304. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3305. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3306. rc = qdio_initialize(&init_data);
  3307. if (rc)
  3308. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3309. }
  3310. kfree(out_sbal_ptrs);
  3311. kfree(in_sbal_ptrs);
  3312. kfree(qib_param_field);
  3313. return rc;
  3314. }
  3315. static void qeth_core_free_card(struct qeth_card *card)
  3316. {
  3317. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3318. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3319. qeth_clean_channel(&card->read);
  3320. qeth_clean_channel(&card->write);
  3321. if (card->dev)
  3322. free_netdev(card->dev);
  3323. kfree(card->ip_tbd_list);
  3324. qeth_free_qdio_buffers(card);
  3325. unregister_service_level(&card->qeth_service_level);
  3326. kfree(card);
  3327. }
  3328. static struct ccw_device_id qeth_ids[] = {
  3329. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3330. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3331. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3332. {},
  3333. };
  3334. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3335. static struct ccw_driver qeth_ccw_driver = {
  3336. .name = "qeth",
  3337. .ids = qeth_ids,
  3338. .probe = ccwgroup_probe_ccwdev,
  3339. .remove = ccwgroup_remove_ccwdev,
  3340. };
  3341. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3342. unsigned long driver_id)
  3343. {
  3344. return ccwgroup_create_from_string(root_dev, driver_id,
  3345. &qeth_ccw_driver, 3, buf);
  3346. }
  3347. int qeth_core_hardsetup_card(struct qeth_card *card)
  3348. {
  3349. struct qdio_ssqd_desc *ssqd;
  3350. int retries = 3;
  3351. int mpno = 0;
  3352. int rc;
  3353. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3354. atomic_set(&card->force_alloc_skb, 0);
  3355. retry:
  3356. if (retries < 3) {
  3357. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3358. dev_name(&card->gdev->dev));
  3359. ccw_device_set_offline(CARD_DDEV(card));
  3360. ccw_device_set_offline(CARD_WDEV(card));
  3361. ccw_device_set_offline(CARD_RDEV(card));
  3362. ccw_device_set_online(CARD_RDEV(card));
  3363. ccw_device_set_online(CARD_WDEV(card));
  3364. ccw_device_set_online(CARD_DDEV(card));
  3365. }
  3366. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3367. if (rc == -ERESTARTSYS) {
  3368. QETH_DBF_TEXT(SETUP, 2, "break1");
  3369. return rc;
  3370. } else if (rc) {
  3371. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3372. if (--retries < 0)
  3373. goto out;
  3374. else
  3375. goto retry;
  3376. }
  3377. rc = qeth_get_unitaddr(card);
  3378. if (rc) {
  3379. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3380. return rc;
  3381. }
  3382. ssqd = kmalloc(sizeof(struct qdio_ssqd_desc), GFP_KERNEL);
  3383. if (!ssqd) {
  3384. rc = -ENOMEM;
  3385. goto out;
  3386. }
  3387. rc = qdio_get_ssqd_desc(CARD_DDEV(card), ssqd);
  3388. if (rc == 0)
  3389. mpno = ssqd->pcnt;
  3390. kfree(ssqd);
  3391. if (mpno)
  3392. mpno = min(mpno - 1, QETH_MAX_PORTNO);
  3393. if (card->info.portno > mpno) {
  3394. QETH_DBF_MESSAGE(2, "Device %s does not offer port number %d"
  3395. "\n.", CARD_BUS_ID(card), card->info.portno);
  3396. rc = -ENODEV;
  3397. goto out;
  3398. }
  3399. qeth_init_tokens(card);
  3400. qeth_init_func_level(card);
  3401. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3402. if (rc == -ERESTARTSYS) {
  3403. QETH_DBF_TEXT(SETUP, 2, "break2");
  3404. return rc;
  3405. } else if (rc) {
  3406. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3407. if (--retries < 0)
  3408. goto out;
  3409. else
  3410. goto retry;
  3411. }
  3412. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3413. if (rc == -ERESTARTSYS) {
  3414. QETH_DBF_TEXT(SETUP, 2, "break3");
  3415. return rc;
  3416. } else if (rc) {
  3417. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3418. if (--retries < 0)
  3419. goto out;
  3420. else
  3421. goto retry;
  3422. }
  3423. rc = qeth_mpc_initialize(card);
  3424. if (rc) {
  3425. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3426. goto out;
  3427. }
  3428. return 0;
  3429. out:
  3430. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3431. "an error on the device\n");
  3432. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3433. dev_name(&card->gdev->dev), rc);
  3434. return rc;
  3435. }
  3436. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3437. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3438. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3439. {
  3440. struct page *page = virt_to_page(element->addr);
  3441. if (*pskb == NULL) {
  3442. /* the upper protocol layers assume that there is data in the
  3443. * skb itself. Copy a small amount (64 bytes) to make them
  3444. * happy. */
  3445. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3446. if (!(*pskb))
  3447. return -ENOMEM;
  3448. skb_reserve(*pskb, ETH_HLEN);
  3449. if (data_len <= 64) {
  3450. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3451. data_len);
  3452. } else {
  3453. get_page(page);
  3454. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3455. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3456. data_len - 64);
  3457. (*pskb)->data_len += data_len - 64;
  3458. (*pskb)->len += data_len - 64;
  3459. (*pskb)->truesize += data_len - 64;
  3460. (*pfrag)++;
  3461. }
  3462. } else {
  3463. get_page(page);
  3464. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3465. (*pskb)->data_len += data_len;
  3466. (*pskb)->len += data_len;
  3467. (*pskb)->truesize += data_len;
  3468. (*pfrag)++;
  3469. }
  3470. return 0;
  3471. }
  3472. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3473. struct qdio_buffer *buffer,
  3474. struct qdio_buffer_element **__element, int *__offset,
  3475. struct qeth_hdr **hdr)
  3476. {
  3477. struct qdio_buffer_element *element = *__element;
  3478. int offset = *__offset;
  3479. struct sk_buff *skb = NULL;
  3480. int skb_len;
  3481. void *data_ptr;
  3482. int data_len;
  3483. int headroom = 0;
  3484. int use_rx_sg = 0;
  3485. int frag = 0;
  3486. /* qeth_hdr must not cross element boundaries */
  3487. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3488. if (qeth_is_last_sbale(element))
  3489. return NULL;
  3490. element++;
  3491. offset = 0;
  3492. if (element->length < sizeof(struct qeth_hdr))
  3493. return NULL;
  3494. }
  3495. *hdr = element->addr + offset;
  3496. offset += sizeof(struct qeth_hdr);
  3497. if (card->options.layer2) {
  3498. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3499. skb_len = (*hdr)->hdr.osn.pdu_length;
  3500. headroom = sizeof(struct qeth_hdr);
  3501. } else {
  3502. skb_len = (*hdr)->hdr.l2.pkt_length;
  3503. }
  3504. } else {
  3505. skb_len = (*hdr)->hdr.l3.length;
  3506. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3507. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3508. headroom = TR_HLEN;
  3509. else
  3510. headroom = ETH_HLEN;
  3511. }
  3512. if (!skb_len)
  3513. return NULL;
  3514. if ((skb_len >= card->options.rx_sg_cb) &&
  3515. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3516. (!atomic_read(&card->force_alloc_skb))) {
  3517. use_rx_sg = 1;
  3518. } else {
  3519. skb = dev_alloc_skb(skb_len + headroom);
  3520. if (!skb)
  3521. goto no_mem;
  3522. if (headroom)
  3523. skb_reserve(skb, headroom);
  3524. }
  3525. data_ptr = element->addr + offset;
  3526. while (skb_len) {
  3527. data_len = min(skb_len, (int)(element->length - offset));
  3528. if (data_len) {
  3529. if (use_rx_sg) {
  3530. if (qeth_create_skb_frag(element, &skb, offset,
  3531. &frag, data_len))
  3532. goto no_mem;
  3533. } else {
  3534. memcpy(skb_put(skb, data_len), data_ptr,
  3535. data_len);
  3536. }
  3537. }
  3538. skb_len -= data_len;
  3539. if (skb_len) {
  3540. if (qeth_is_last_sbale(element)) {
  3541. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3542. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3543. CARD_BUS_ID(card));
  3544. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3545. QETH_DBF_TEXT_(QERR, 2, "%s",
  3546. CARD_BUS_ID(card));
  3547. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3548. dev_kfree_skb_any(skb);
  3549. card->stats.rx_errors++;
  3550. return NULL;
  3551. }
  3552. element++;
  3553. offset = 0;
  3554. data_ptr = element->addr;
  3555. } else {
  3556. offset += data_len;
  3557. }
  3558. }
  3559. *__element = element;
  3560. *__offset = offset;
  3561. if (use_rx_sg && card->options.performance_stats) {
  3562. card->perf_stats.sg_skbs_rx++;
  3563. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3564. }
  3565. return skb;
  3566. no_mem:
  3567. if (net_ratelimit()) {
  3568. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3569. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3570. }
  3571. card->stats.rx_dropped++;
  3572. return NULL;
  3573. }
  3574. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3575. static void qeth_unregister_dbf_views(void)
  3576. {
  3577. int x;
  3578. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3579. debug_unregister(qeth_dbf[x].id);
  3580. qeth_dbf[x].id = NULL;
  3581. }
  3582. }
  3583. void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
  3584. {
  3585. char dbf_txt_buf[32];
  3586. va_list args;
  3587. if (level > (qeth_dbf[dbf_nix].id)->level)
  3588. return;
  3589. va_start(args, fmt);
  3590. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3591. va_end(args);
  3592. debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
  3593. }
  3594. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3595. static int qeth_register_dbf_views(void)
  3596. {
  3597. int ret;
  3598. int x;
  3599. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3600. /* register the areas */
  3601. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3602. qeth_dbf[x].pages,
  3603. qeth_dbf[x].areas,
  3604. qeth_dbf[x].len);
  3605. if (qeth_dbf[x].id == NULL) {
  3606. qeth_unregister_dbf_views();
  3607. return -ENOMEM;
  3608. }
  3609. /* register a view */
  3610. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3611. if (ret) {
  3612. qeth_unregister_dbf_views();
  3613. return ret;
  3614. }
  3615. /* set a passing level */
  3616. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3617. }
  3618. return 0;
  3619. }
  3620. int qeth_core_load_discipline(struct qeth_card *card,
  3621. enum qeth_discipline_id discipline)
  3622. {
  3623. int rc = 0;
  3624. switch (discipline) {
  3625. case QETH_DISCIPLINE_LAYER3:
  3626. card->discipline.ccwgdriver = try_then_request_module(
  3627. symbol_get(qeth_l3_ccwgroup_driver),
  3628. "qeth_l3");
  3629. break;
  3630. case QETH_DISCIPLINE_LAYER2:
  3631. card->discipline.ccwgdriver = try_then_request_module(
  3632. symbol_get(qeth_l2_ccwgroup_driver),
  3633. "qeth_l2");
  3634. break;
  3635. }
  3636. if (!card->discipline.ccwgdriver) {
  3637. dev_err(&card->gdev->dev, "There is no kernel module to "
  3638. "support discipline %d\n", discipline);
  3639. rc = -EINVAL;
  3640. }
  3641. return rc;
  3642. }
  3643. void qeth_core_free_discipline(struct qeth_card *card)
  3644. {
  3645. if (card->options.layer2)
  3646. symbol_put(qeth_l2_ccwgroup_driver);
  3647. else
  3648. symbol_put(qeth_l3_ccwgroup_driver);
  3649. card->discipline.ccwgdriver = NULL;
  3650. }
  3651. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3652. {
  3653. struct qeth_card *card;
  3654. struct device *dev;
  3655. int rc;
  3656. unsigned long flags;
  3657. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3658. dev = &gdev->dev;
  3659. if (!get_device(dev))
  3660. return -ENODEV;
  3661. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3662. card = qeth_alloc_card();
  3663. if (!card) {
  3664. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3665. rc = -ENOMEM;
  3666. goto err_dev;
  3667. }
  3668. card->read.ccwdev = gdev->cdev[0];
  3669. card->write.ccwdev = gdev->cdev[1];
  3670. card->data.ccwdev = gdev->cdev[2];
  3671. dev_set_drvdata(&gdev->dev, card);
  3672. card->gdev = gdev;
  3673. gdev->cdev[0]->handler = qeth_irq;
  3674. gdev->cdev[1]->handler = qeth_irq;
  3675. gdev->cdev[2]->handler = qeth_irq;
  3676. rc = qeth_determine_card_type(card);
  3677. if (rc) {
  3678. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3679. goto err_card;
  3680. }
  3681. rc = qeth_setup_card(card);
  3682. if (rc) {
  3683. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3684. goto err_card;
  3685. }
  3686. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3687. rc = qeth_core_create_osn_attributes(dev);
  3688. if (rc)
  3689. goto err_card;
  3690. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3691. if (rc) {
  3692. qeth_core_remove_osn_attributes(dev);
  3693. goto err_card;
  3694. }
  3695. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3696. if (rc) {
  3697. qeth_core_free_discipline(card);
  3698. qeth_core_remove_osn_attributes(dev);
  3699. goto err_card;
  3700. }
  3701. } else {
  3702. rc = qeth_core_create_device_attributes(dev);
  3703. if (rc)
  3704. goto err_card;
  3705. }
  3706. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3707. list_add_tail(&card->list, &qeth_core_card_list.list);
  3708. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3709. return 0;
  3710. err_card:
  3711. qeth_core_free_card(card);
  3712. err_dev:
  3713. put_device(dev);
  3714. return rc;
  3715. }
  3716. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3717. {
  3718. unsigned long flags;
  3719. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3720. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3721. if (card->discipline.ccwgdriver) {
  3722. card->discipline.ccwgdriver->remove(gdev);
  3723. qeth_core_free_discipline(card);
  3724. }
  3725. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3726. qeth_core_remove_osn_attributes(&gdev->dev);
  3727. } else {
  3728. qeth_core_remove_device_attributes(&gdev->dev);
  3729. }
  3730. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3731. list_del(&card->list);
  3732. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3733. qeth_core_free_card(card);
  3734. dev_set_drvdata(&gdev->dev, NULL);
  3735. put_device(&gdev->dev);
  3736. return;
  3737. }
  3738. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3739. {
  3740. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3741. int rc = 0;
  3742. int def_discipline;
  3743. if (!card->discipline.ccwgdriver) {
  3744. if (card->info.type == QETH_CARD_TYPE_IQD)
  3745. def_discipline = QETH_DISCIPLINE_LAYER3;
  3746. else
  3747. def_discipline = QETH_DISCIPLINE_LAYER2;
  3748. rc = qeth_core_load_discipline(card, def_discipline);
  3749. if (rc)
  3750. goto err;
  3751. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3752. if (rc)
  3753. goto err;
  3754. }
  3755. rc = card->discipline.ccwgdriver->set_online(gdev);
  3756. err:
  3757. return rc;
  3758. }
  3759. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3760. {
  3761. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3762. return card->discipline.ccwgdriver->set_offline(gdev);
  3763. }
  3764. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3765. {
  3766. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3767. if (card->discipline.ccwgdriver &&
  3768. card->discipline.ccwgdriver->shutdown)
  3769. card->discipline.ccwgdriver->shutdown(gdev);
  3770. }
  3771. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3772. .owner = THIS_MODULE,
  3773. .name = "qeth",
  3774. .driver_id = 0xD8C5E3C8,
  3775. .probe = qeth_core_probe_device,
  3776. .remove = qeth_core_remove_device,
  3777. .set_online = qeth_core_set_online,
  3778. .set_offline = qeth_core_set_offline,
  3779. .shutdown = qeth_core_shutdown,
  3780. };
  3781. static ssize_t
  3782. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3783. size_t count)
  3784. {
  3785. int err;
  3786. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3787. qeth_core_ccwgroup_driver.driver_id);
  3788. if (err)
  3789. return err;
  3790. else
  3791. return count;
  3792. }
  3793. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3794. static struct {
  3795. const char str[ETH_GSTRING_LEN];
  3796. } qeth_ethtool_stats_keys[] = {
  3797. /* 0 */{"rx skbs"},
  3798. {"rx buffers"},
  3799. {"tx skbs"},
  3800. {"tx buffers"},
  3801. {"tx skbs no packing"},
  3802. {"tx buffers no packing"},
  3803. {"tx skbs packing"},
  3804. {"tx buffers packing"},
  3805. {"tx sg skbs"},
  3806. {"tx sg frags"},
  3807. /* 10 */{"rx sg skbs"},
  3808. {"rx sg frags"},
  3809. {"rx sg page allocs"},
  3810. {"tx large kbytes"},
  3811. {"tx large count"},
  3812. {"tx pk state ch n->p"},
  3813. {"tx pk state ch p->n"},
  3814. {"tx pk watermark low"},
  3815. {"tx pk watermark high"},
  3816. {"queue 0 buffer usage"},
  3817. /* 20 */{"queue 1 buffer usage"},
  3818. {"queue 2 buffer usage"},
  3819. {"queue 3 buffer usage"},
  3820. {"rx handler time"},
  3821. {"rx handler count"},
  3822. {"rx do_QDIO time"},
  3823. {"rx do_QDIO count"},
  3824. {"tx handler time"},
  3825. {"tx handler count"},
  3826. {"tx time"},
  3827. /* 30 */{"tx count"},
  3828. {"tx do_QDIO time"},
  3829. {"tx do_QDIO count"},
  3830. {"tx csum"},
  3831. };
  3832. int qeth_core_get_stats_count(struct net_device *dev)
  3833. {
  3834. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  3835. }
  3836. EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
  3837. void qeth_core_get_ethtool_stats(struct net_device *dev,
  3838. struct ethtool_stats *stats, u64 *data)
  3839. {
  3840. struct qeth_card *card = dev->ml_priv;
  3841. data[0] = card->stats.rx_packets -
  3842. card->perf_stats.initial_rx_packets;
  3843. data[1] = card->perf_stats.bufs_rec;
  3844. data[2] = card->stats.tx_packets -
  3845. card->perf_stats.initial_tx_packets;
  3846. data[3] = card->perf_stats.bufs_sent;
  3847. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  3848. - card->perf_stats.skbs_sent_pack;
  3849. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  3850. data[6] = card->perf_stats.skbs_sent_pack;
  3851. data[7] = card->perf_stats.bufs_sent_pack;
  3852. data[8] = card->perf_stats.sg_skbs_sent;
  3853. data[9] = card->perf_stats.sg_frags_sent;
  3854. data[10] = card->perf_stats.sg_skbs_rx;
  3855. data[11] = card->perf_stats.sg_frags_rx;
  3856. data[12] = card->perf_stats.sg_alloc_page_rx;
  3857. data[13] = (card->perf_stats.large_send_bytes >> 10);
  3858. data[14] = card->perf_stats.large_send_cnt;
  3859. data[15] = card->perf_stats.sc_dp_p;
  3860. data[16] = card->perf_stats.sc_p_dp;
  3861. data[17] = QETH_LOW_WATERMARK_PACK;
  3862. data[18] = QETH_HIGH_WATERMARK_PACK;
  3863. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  3864. data[20] = (card->qdio.no_out_queues > 1) ?
  3865. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  3866. data[21] = (card->qdio.no_out_queues > 2) ?
  3867. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  3868. data[22] = (card->qdio.no_out_queues > 3) ?
  3869. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  3870. data[23] = card->perf_stats.inbound_time;
  3871. data[24] = card->perf_stats.inbound_cnt;
  3872. data[25] = card->perf_stats.inbound_do_qdio_time;
  3873. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  3874. data[27] = card->perf_stats.outbound_handler_time;
  3875. data[28] = card->perf_stats.outbound_handler_cnt;
  3876. data[29] = card->perf_stats.outbound_time;
  3877. data[30] = card->perf_stats.outbound_cnt;
  3878. data[31] = card->perf_stats.outbound_do_qdio_time;
  3879. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  3880. data[33] = card->perf_stats.tx_csum;
  3881. }
  3882. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  3883. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  3884. {
  3885. switch (stringset) {
  3886. case ETH_SS_STATS:
  3887. memcpy(data, &qeth_ethtool_stats_keys,
  3888. sizeof(qeth_ethtool_stats_keys));
  3889. break;
  3890. default:
  3891. WARN_ON(1);
  3892. break;
  3893. }
  3894. }
  3895. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  3896. void qeth_core_get_drvinfo(struct net_device *dev,
  3897. struct ethtool_drvinfo *info)
  3898. {
  3899. struct qeth_card *card = dev->ml_priv;
  3900. if (card->options.layer2)
  3901. strcpy(info->driver, "qeth_l2");
  3902. else
  3903. strcpy(info->driver, "qeth_l3");
  3904. strcpy(info->version, "1.0");
  3905. strcpy(info->fw_version, card->info.mcl_level);
  3906. sprintf(info->bus_info, "%s/%s/%s",
  3907. CARD_RDEV_ID(card),
  3908. CARD_WDEV_ID(card),
  3909. CARD_DDEV_ID(card));
  3910. }
  3911. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  3912. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  3913. struct ethtool_cmd *ecmd)
  3914. {
  3915. struct qeth_card *card = netdev->ml_priv;
  3916. enum qeth_link_types link_type;
  3917. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  3918. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  3919. else
  3920. link_type = card->info.link_type;
  3921. ecmd->transceiver = XCVR_INTERNAL;
  3922. ecmd->supported = SUPPORTED_Autoneg;
  3923. ecmd->advertising = ADVERTISED_Autoneg;
  3924. ecmd->duplex = DUPLEX_FULL;
  3925. ecmd->autoneg = AUTONEG_ENABLE;
  3926. switch (link_type) {
  3927. case QETH_LINK_TYPE_FAST_ETH:
  3928. case QETH_LINK_TYPE_LANE_ETH100:
  3929. ecmd->supported |= SUPPORTED_10baseT_Half |
  3930. SUPPORTED_10baseT_Full |
  3931. SUPPORTED_100baseT_Half |
  3932. SUPPORTED_100baseT_Full |
  3933. SUPPORTED_TP;
  3934. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3935. ADVERTISED_10baseT_Full |
  3936. ADVERTISED_100baseT_Half |
  3937. ADVERTISED_100baseT_Full |
  3938. ADVERTISED_TP;
  3939. ecmd->speed = SPEED_100;
  3940. ecmd->port = PORT_TP;
  3941. break;
  3942. case QETH_LINK_TYPE_GBIT_ETH:
  3943. case QETH_LINK_TYPE_LANE_ETH1000:
  3944. ecmd->supported |= SUPPORTED_10baseT_Half |
  3945. SUPPORTED_10baseT_Full |
  3946. SUPPORTED_100baseT_Half |
  3947. SUPPORTED_100baseT_Full |
  3948. SUPPORTED_1000baseT_Half |
  3949. SUPPORTED_1000baseT_Full |
  3950. SUPPORTED_FIBRE;
  3951. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3952. ADVERTISED_10baseT_Full |
  3953. ADVERTISED_100baseT_Half |
  3954. ADVERTISED_100baseT_Full |
  3955. ADVERTISED_1000baseT_Half |
  3956. ADVERTISED_1000baseT_Full |
  3957. ADVERTISED_FIBRE;
  3958. ecmd->speed = SPEED_1000;
  3959. ecmd->port = PORT_FIBRE;
  3960. break;
  3961. case QETH_LINK_TYPE_10GBIT_ETH:
  3962. ecmd->supported |= SUPPORTED_10baseT_Half |
  3963. SUPPORTED_10baseT_Full |
  3964. SUPPORTED_100baseT_Half |
  3965. SUPPORTED_100baseT_Full |
  3966. SUPPORTED_1000baseT_Half |
  3967. SUPPORTED_1000baseT_Full |
  3968. SUPPORTED_10000baseT_Full |
  3969. SUPPORTED_FIBRE;
  3970. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3971. ADVERTISED_10baseT_Full |
  3972. ADVERTISED_100baseT_Half |
  3973. ADVERTISED_100baseT_Full |
  3974. ADVERTISED_1000baseT_Half |
  3975. ADVERTISED_1000baseT_Full |
  3976. ADVERTISED_10000baseT_Full |
  3977. ADVERTISED_FIBRE;
  3978. ecmd->speed = SPEED_10000;
  3979. ecmd->port = PORT_FIBRE;
  3980. break;
  3981. default:
  3982. ecmd->supported |= SUPPORTED_10baseT_Half |
  3983. SUPPORTED_10baseT_Full |
  3984. SUPPORTED_TP;
  3985. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3986. ADVERTISED_10baseT_Full |
  3987. ADVERTISED_TP;
  3988. ecmd->speed = SPEED_10;
  3989. ecmd->port = PORT_TP;
  3990. }
  3991. return 0;
  3992. }
  3993. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  3994. static int __init qeth_core_init(void)
  3995. {
  3996. int rc;
  3997. pr_info("loading core functions\n");
  3998. INIT_LIST_HEAD(&qeth_core_card_list.list);
  3999. rwlock_init(&qeth_core_card_list.rwlock);
  4000. rc = qeth_register_dbf_views();
  4001. if (rc)
  4002. goto out_err;
  4003. rc = ccw_driver_register(&qeth_ccw_driver);
  4004. if (rc)
  4005. goto ccw_err;
  4006. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4007. if (rc)
  4008. goto ccwgroup_err;
  4009. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4010. &driver_attr_group);
  4011. if (rc)
  4012. goto driver_err;
  4013. qeth_core_root_dev = root_device_register("qeth");
  4014. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4015. if (rc)
  4016. goto register_err;
  4017. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4018. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4019. if (!qeth_core_header_cache) {
  4020. rc = -ENOMEM;
  4021. goto slab_err;
  4022. }
  4023. return 0;
  4024. slab_err:
  4025. root_device_unregister(qeth_core_root_dev);
  4026. register_err:
  4027. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4028. &driver_attr_group);
  4029. driver_err:
  4030. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4031. ccwgroup_err:
  4032. ccw_driver_unregister(&qeth_ccw_driver);
  4033. ccw_err:
  4034. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4035. qeth_unregister_dbf_views();
  4036. out_err:
  4037. pr_err("Initializing the qeth device driver failed\n");
  4038. return rc;
  4039. }
  4040. static void __exit qeth_core_exit(void)
  4041. {
  4042. root_device_unregister(qeth_core_root_dev);
  4043. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4044. &driver_attr_group);
  4045. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4046. ccw_driver_unregister(&qeth_ccw_driver);
  4047. kmem_cache_destroy(qeth_core_header_cache);
  4048. qeth_unregister_dbf_views();
  4049. pr_info("core functions removed\n");
  4050. }
  4051. module_init(qeth_core_init);
  4052. module_exit(qeth_core_exit);
  4053. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4054. MODULE_DESCRIPTION("qeth core functions");
  4055. MODULE_LICENSE("GPL");