iwl-4965.c 67 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * Intel Linux Wireless <ilw@linux.intel.com>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. *****************************************************************************/
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/init.h>
  29. #include <linux/pci.h>
  30. #include <linux/dma-mapping.h>
  31. #include <linux/delay.h>
  32. #include <linux/skbuff.h>
  33. #include <linux/netdevice.h>
  34. #include <linux/wireless.h>
  35. #include <net/mac80211.h>
  36. #include <linux/etherdevice.h>
  37. #include <asm/unaligned.h>
  38. #include "iwl-eeprom.h"
  39. #include "iwl-dev.h"
  40. #include "iwl-core.h"
  41. #include "iwl-io.h"
  42. #include "iwl-helpers.h"
  43. #include "iwl-calib.h"
  44. #include "iwl-sta.h"
  45. static int iwl4965_send_tx_power(struct iwl_priv *priv);
  46. static int iwl4965_hw_get_temperature(const struct iwl_priv *priv);
  47. /* Highest firmware API version supported */
  48. #define IWL4965_UCODE_API_MAX 2
  49. /* Lowest firmware API version supported */
  50. #define IWL4965_UCODE_API_MIN 2
  51. #define IWL4965_FW_PRE "iwlwifi-4965-"
  52. #define _IWL4965_MODULE_FIRMWARE(api) IWL4965_FW_PRE #api ".ucode"
  53. #define IWL4965_MODULE_FIRMWARE(api) _IWL4965_MODULE_FIRMWARE(api)
  54. /* module parameters */
  55. static struct iwl_mod_params iwl4965_mod_params = {
  56. .num_of_queues = IWL49_NUM_QUEUES,
  57. .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES,
  58. .amsdu_size_8K = 1,
  59. .restart_fw = 1,
  60. /* the rest are 0 by default */
  61. };
  62. /* check contents of special bootstrap uCode SRAM */
  63. static int iwl4965_verify_bsm(struct iwl_priv *priv)
  64. {
  65. __le32 *image = priv->ucode_boot.v_addr;
  66. u32 len = priv->ucode_boot.len;
  67. u32 reg;
  68. u32 val;
  69. IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
  70. /* verify BSM SRAM contents */
  71. val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
  72. for (reg = BSM_SRAM_LOWER_BOUND;
  73. reg < BSM_SRAM_LOWER_BOUND + len;
  74. reg += sizeof(u32), image++) {
  75. val = iwl_read_prph(priv, reg);
  76. if (val != le32_to_cpu(*image)) {
  77. IWL_ERR(priv, "BSM uCode verification failed at "
  78. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  79. BSM_SRAM_LOWER_BOUND,
  80. reg - BSM_SRAM_LOWER_BOUND, len,
  81. val, le32_to_cpu(*image));
  82. return -EIO;
  83. }
  84. }
  85. IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
  86. return 0;
  87. }
  88. /**
  89. * iwl4965_load_bsm - Load bootstrap instructions
  90. *
  91. * BSM operation:
  92. *
  93. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  94. * in special SRAM that does not power down during RFKILL. When powering back
  95. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  96. * the bootstrap program into the on-board processor, and starts it.
  97. *
  98. * The bootstrap program loads (via DMA) instructions and data for a new
  99. * program from host DRAM locations indicated by the host driver in the
  100. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  101. * automatically.
  102. *
  103. * When initializing the NIC, the host driver points the BSM to the
  104. * "initialize" uCode image. This uCode sets up some internal data, then
  105. * notifies host via "initialize alive" that it is complete.
  106. *
  107. * The host then replaces the BSM_DRAM_* pointer values to point to the
  108. * normal runtime uCode instructions and a backup uCode data cache buffer
  109. * (filled initially with starting data values for the on-board processor),
  110. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  111. * which begins normal operation.
  112. *
  113. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  114. * the backup data cache in DRAM before SRAM is powered down.
  115. *
  116. * When powering back up, the BSM loads the bootstrap program. This reloads
  117. * the runtime uCode instructions and the backup data cache into SRAM,
  118. * and re-launches the runtime uCode from where it left off.
  119. */
  120. static int iwl4965_load_bsm(struct iwl_priv *priv)
  121. {
  122. __le32 *image = priv->ucode_boot.v_addr;
  123. u32 len = priv->ucode_boot.len;
  124. dma_addr_t pinst;
  125. dma_addr_t pdata;
  126. u32 inst_len;
  127. u32 data_len;
  128. int i;
  129. u32 done;
  130. u32 reg_offset;
  131. int ret;
  132. IWL_DEBUG_INFO(priv, "Begin load bsm\n");
  133. priv->ucode_type = UCODE_RT;
  134. /* make sure bootstrap program is no larger than BSM's SRAM size */
  135. if (len > IWL49_MAX_BSM_SIZE)
  136. return -EINVAL;
  137. /* Tell bootstrap uCode where to find the "Initialize" uCode
  138. * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
  139. * NOTE: iwl_init_alive_start() will replace these values,
  140. * after the "initialize" uCode has run, to point to
  141. * runtime/protocol instructions and backup data cache.
  142. */
  143. pinst = priv->ucode_init.p_addr >> 4;
  144. pdata = priv->ucode_init_data.p_addr >> 4;
  145. inst_len = priv->ucode_init.len;
  146. data_len = priv->ucode_init_data.len;
  147. ret = iwl_grab_nic_access(priv);
  148. if (ret)
  149. return ret;
  150. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  151. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  152. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  153. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  154. /* Fill BSM memory with bootstrap instructions */
  155. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  156. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  157. reg_offset += sizeof(u32), image++)
  158. _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
  159. ret = iwl4965_verify_bsm(priv);
  160. if (ret) {
  161. iwl_release_nic_access(priv);
  162. return ret;
  163. }
  164. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  165. iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  166. iwl_write_prph(priv, BSM_WR_MEM_DST_REG, IWL49_RTC_INST_LOWER_BOUND);
  167. iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  168. /* Load bootstrap code into instruction SRAM now,
  169. * to prepare to load "initialize" uCode */
  170. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
  171. /* Wait for load of bootstrap uCode to finish */
  172. for (i = 0; i < 100; i++) {
  173. done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
  174. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  175. break;
  176. udelay(10);
  177. }
  178. if (i < 100)
  179. IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
  180. else {
  181. IWL_ERR(priv, "BSM write did not complete!\n");
  182. return -EIO;
  183. }
  184. /* Enable future boot loads whenever power management unit triggers it
  185. * (e.g. when powering back up after power-save shutdown) */
  186. iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
  187. iwl_release_nic_access(priv);
  188. return 0;
  189. }
  190. /**
  191. * iwl4965_set_ucode_ptrs - Set uCode address location
  192. *
  193. * Tell initialization uCode where to find runtime uCode.
  194. *
  195. * BSM registers initially contain pointers to initialization uCode.
  196. * We need to replace them to load runtime uCode inst and data,
  197. * and to save runtime data when powering down.
  198. */
  199. static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
  200. {
  201. dma_addr_t pinst;
  202. dma_addr_t pdata;
  203. unsigned long flags;
  204. int ret = 0;
  205. /* bits 35:4 for 4965 */
  206. pinst = priv->ucode_code.p_addr >> 4;
  207. pdata = priv->ucode_data_backup.p_addr >> 4;
  208. spin_lock_irqsave(&priv->lock, flags);
  209. ret = iwl_grab_nic_access(priv);
  210. if (ret) {
  211. spin_unlock_irqrestore(&priv->lock, flags);
  212. return ret;
  213. }
  214. /* Tell bootstrap uCode where to find image to load */
  215. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  216. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  217. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  218. priv->ucode_data.len);
  219. /* Inst byte count must be last to set up, bit 31 signals uCode
  220. * that all new ptr/size info is in place */
  221. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  222. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  223. iwl_release_nic_access(priv);
  224. spin_unlock_irqrestore(&priv->lock, flags);
  225. IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
  226. return ret;
  227. }
  228. /**
  229. * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
  230. *
  231. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  232. *
  233. * The 4965 "initialize" ALIVE reply contains calibration data for:
  234. * Voltage, temperature, and MIMO tx gain correction, now stored in priv
  235. * (3945 does not contain this data).
  236. *
  237. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  238. */
  239. static void iwl4965_init_alive_start(struct iwl_priv *priv)
  240. {
  241. /* Check alive response for "valid" sign from uCode */
  242. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  243. /* We had an error bringing up the hardware, so take it
  244. * all the way back down so we can try again */
  245. IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
  246. goto restart;
  247. }
  248. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  249. * This is a paranoid check, because we would not have gotten the
  250. * "initialize" alive if code weren't properly loaded. */
  251. if (iwl_verify_ucode(priv)) {
  252. /* Runtime instruction load was bad;
  253. * take it all the way back down so we can try again */
  254. IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
  255. goto restart;
  256. }
  257. /* Calculate temperature */
  258. priv->temperature = iwl4965_hw_get_temperature(priv);
  259. /* Send pointers to protocol/runtime uCode image ... init code will
  260. * load and launch runtime uCode, which will send us another "Alive"
  261. * notification. */
  262. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  263. if (iwl4965_set_ucode_ptrs(priv)) {
  264. /* Runtime instruction load won't happen;
  265. * take it all the way back down so we can try again */
  266. IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
  267. goto restart;
  268. }
  269. return;
  270. restart:
  271. queue_work(priv->workqueue, &priv->restart);
  272. }
  273. static int is_fat_channel(__le32 rxon_flags)
  274. {
  275. return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
  276. (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
  277. }
  278. /*
  279. * EEPROM handlers
  280. */
  281. static u16 iwl4965_eeprom_calib_version(struct iwl_priv *priv)
  282. {
  283. return iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
  284. }
  285. /*
  286. * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
  287. * must be called under priv->lock and mac access
  288. */
  289. static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
  290. {
  291. iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
  292. }
  293. static int iwl4965_apm_init(struct iwl_priv *priv)
  294. {
  295. int ret = 0;
  296. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  297. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  298. /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
  299. iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  300. CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
  301. /* set "initialization complete" bit to move adapter
  302. * D0U* --> D0A* state */
  303. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  304. /* wait for clock stabilization */
  305. ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
  306. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  307. if (ret < 0) {
  308. IWL_DEBUG_INFO(priv, "Failed to init the card\n");
  309. goto out;
  310. }
  311. ret = iwl_grab_nic_access(priv);
  312. if (ret)
  313. goto out;
  314. /* enable DMA */
  315. iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
  316. APMG_CLK_VAL_BSM_CLK_RQT);
  317. udelay(20);
  318. /* disable L1-Active */
  319. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  320. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  321. iwl_release_nic_access(priv);
  322. out:
  323. return ret;
  324. }
  325. static void iwl4965_nic_config(struct iwl_priv *priv)
  326. {
  327. unsigned long flags;
  328. u16 radio_cfg;
  329. u16 lctl;
  330. spin_lock_irqsave(&priv->lock, flags);
  331. lctl = iwl_pcie_link_ctl(priv);
  332. /* HW bug W/A - negligible power consumption */
  333. /* L1-ASPM is enabled by BIOS */
  334. if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
  335. /* L1-ASPM enabled: disable L0S */
  336. iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
  337. else
  338. /* L1-ASPM disabled: enable L0S */
  339. iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
  340. radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
  341. /* write radio config values to register */
  342. if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
  343. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  344. EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
  345. EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
  346. EEPROM_RF_CFG_DASH_MSK(radio_cfg));
  347. /* set CSR_HW_CONFIG_REG for uCode use */
  348. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  349. CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  350. CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
  351. priv->calib_info = (struct iwl_eeprom_calib_info *)
  352. iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
  353. spin_unlock_irqrestore(&priv->lock, flags);
  354. }
  355. static int iwl4965_apm_stop_master(struct iwl_priv *priv)
  356. {
  357. unsigned long flags;
  358. spin_lock_irqsave(&priv->lock, flags);
  359. /* set stop master bit */
  360. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  361. iwl_poll_direct_bit(priv, CSR_RESET,
  362. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  363. spin_unlock_irqrestore(&priv->lock, flags);
  364. IWL_DEBUG_INFO(priv, "stop master\n");
  365. return 0;
  366. }
  367. static void iwl4965_apm_stop(struct iwl_priv *priv)
  368. {
  369. unsigned long flags;
  370. iwl4965_apm_stop_master(priv);
  371. spin_lock_irqsave(&priv->lock, flags);
  372. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  373. udelay(10);
  374. /* clear "init complete" move adapter D0A* --> D0U state */
  375. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  376. spin_unlock_irqrestore(&priv->lock, flags);
  377. }
  378. static int iwl4965_apm_reset(struct iwl_priv *priv)
  379. {
  380. int ret = 0;
  381. unsigned long flags;
  382. iwl4965_apm_stop_master(priv);
  383. spin_lock_irqsave(&priv->lock, flags);
  384. iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  385. udelay(10);
  386. /* FIXME: put here L1A -L0S w/a */
  387. iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  388. ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
  389. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  390. if (ret < 0)
  391. goto out;
  392. udelay(10);
  393. ret = iwl_grab_nic_access(priv);
  394. if (ret)
  395. goto out;
  396. /* Enable DMA and BSM Clock */
  397. iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
  398. APMG_CLK_VAL_BSM_CLK_RQT);
  399. udelay(10);
  400. /* disable L1A */
  401. iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  402. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  403. iwl_release_nic_access(priv);
  404. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  405. wake_up_interruptible(&priv->wait_command_queue);
  406. out:
  407. spin_unlock_irqrestore(&priv->lock, flags);
  408. return ret;
  409. }
  410. /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
  411. * Called after every association, but this runs only once!
  412. * ... once chain noise is calibrated the first time, it's good forever. */
  413. static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
  414. {
  415. struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
  416. if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
  417. struct iwl_calib_diff_gain_cmd cmd;
  418. memset(&cmd, 0, sizeof(cmd));
  419. cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
  420. cmd.diff_gain_a = 0;
  421. cmd.diff_gain_b = 0;
  422. cmd.diff_gain_c = 0;
  423. if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  424. sizeof(cmd), &cmd))
  425. IWL_ERR(priv,
  426. "Could not send REPLY_PHY_CALIBRATION_CMD\n");
  427. data->state = IWL_CHAIN_NOISE_ACCUMULATE;
  428. IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
  429. }
  430. }
  431. static void iwl4965_gain_computation(struct iwl_priv *priv,
  432. u32 *average_noise,
  433. u16 min_average_noise_antenna_i,
  434. u32 min_average_noise)
  435. {
  436. int i, ret;
  437. struct iwl_chain_noise_data *data = &priv->chain_noise_data;
  438. data->delta_gain_code[min_average_noise_antenna_i] = 0;
  439. for (i = 0; i < NUM_RX_CHAINS; i++) {
  440. s32 delta_g = 0;
  441. if (!(data->disconn_array[i]) &&
  442. (data->delta_gain_code[i] ==
  443. CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
  444. delta_g = average_noise[i] - min_average_noise;
  445. data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
  446. data->delta_gain_code[i] =
  447. min(data->delta_gain_code[i],
  448. (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
  449. data->delta_gain_code[i] =
  450. (data->delta_gain_code[i] | (1 << 2));
  451. } else {
  452. data->delta_gain_code[i] = 0;
  453. }
  454. }
  455. IWL_DEBUG_CALIB(priv, "delta_gain_codes: a %d b %d c %d\n",
  456. data->delta_gain_code[0],
  457. data->delta_gain_code[1],
  458. data->delta_gain_code[2]);
  459. /* Differential gain gets sent to uCode only once */
  460. if (!data->radio_write) {
  461. struct iwl_calib_diff_gain_cmd cmd;
  462. data->radio_write = 1;
  463. memset(&cmd, 0, sizeof(cmd));
  464. cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
  465. cmd.diff_gain_a = data->delta_gain_code[0];
  466. cmd.diff_gain_b = data->delta_gain_code[1];
  467. cmd.diff_gain_c = data->delta_gain_code[2];
  468. ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  469. sizeof(cmd), &cmd);
  470. if (ret)
  471. IWL_DEBUG_CALIB(priv, "fail sending cmd "
  472. "REPLY_PHY_CALIBRATION_CMD \n");
  473. /* TODO we might want recalculate
  474. * rx_chain in rxon cmd */
  475. /* Mark so we run this algo only once! */
  476. data->state = IWL_CHAIN_NOISE_CALIBRATED;
  477. }
  478. data->chain_noise_a = 0;
  479. data->chain_noise_b = 0;
  480. data->chain_noise_c = 0;
  481. data->chain_signal_a = 0;
  482. data->chain_signal_b = 0;
  483. data->chain_signal_c = 0;
  484. data->beacon_count = 0;
  485. }
  486. static void iwl4965_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
  487. __le32 *tx_flags)
  488. {
  489. if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  490. *tx_flags |= TX_CMD_FLG_RTS_MSK;
  491. *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  492. } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  493. *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  494. *tx_flags |= TX_CMD_FLG_CTS_MSK;
  495. }
  496. }
  497. static void iwl4965_bg_txpower_work(struct work_struct *work)
  498. {
  499. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  500. txpower_work);
  501. /* If a scan happened to start before we got here
  502. * then just return; the statistics notification will
  503. * kick off another scheduled work to compensate for
  504. * any temperature delta we missed here. */
  505. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  506. test_bit(STATUS_SCANNING, &priv->status))
  507. return;
  508. mutex_lock(&priv->mutex);
  509. /* Regardless of if we are associated, we must reconfigure the
  510. * TX power since frames can be sent on non-radar channels while
  511. * not associated */
  512. iwl4965_send_tx_power(priv);
  513. /* Update last_temperature to keep is_calib_needed from running
  514. * when it isn't needed... */
  515. priv->last_temperature = priv->temperature;
  516. mutex_unlock(&priv->mutex);
  517. }
  518. /*
  519. * Acquire priv->lock before calling this function !
  520. */
  521. static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
  522. {
  523. iwl_write_direct32(priv, HBUS_TARG_WRPTR,
  524. (index & 0xff) | (txq_id << 8));
  525. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
  526. }
  527. /**
  528. * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
  529. * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
  530. * @scd_retry: (1) Indicates queue will be used in aggregation mode
  531. *
  532. * NOTE: Acquire priv->lock before calling this function !
  533. */
  534. static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
  535. struct iwl_tx_queue *txq,
  536. int tx_fifo_id, int scd_retry)
  537. {
  538. int txq_id = txq->q.id;
  539. /* Find out whether to activate Tx queue */
  540. int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
  541. /* Set up and activate */
  542. iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  543. (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
  544. (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
  545. (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
  546. (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
  547. IWL49_SCD_QUEUE_STTS_REG_MSK);
  548. txq->sched_retry = scd_retry;
  549. IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
  550. active ? "Activate" : "Deactivate",
  551. scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
  552. }
  553. static const u16 default_queue_to_tx_fifo[] = {
  554. IWL_TX_FIFO_AC3,
  555. IWL_TX_FIFO_AC2,
  556. IWL_TX_FIFO_AC1,
  557. IWL_TX_FIFO_AC0,
  558. IWL49_CMD_FIFO_NUM,
  559. IWL_TX_FIFO_HCCA_1,
  560. IWL_TX_FIFO_HCCA_2
  561. };
  562. static int iwl4965_alive_notify(struct iwl_priv *priv)
  563. {
  564. u32 a;
  565. unsigned long flags;
  566. int ret;
  567. int i, chan;
  568. u32 reg_val;
  569. spin_lock_irqsave(&priv->lock, flags);
  570. ret = iwl_grab_nic_access(priv);
  571. if (ret) {
  572. spin_unlock_irqrestore(&priv->lock, flags);
  573. return ret;
  574. }
  575. /* Clear 4965's internal Tx Scheduler data base */
  576. priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
  577. a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
  578. for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
  579. iwl_write_targ_mem(priv, a, 0);
  580. for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
  581. iwl_write_targ_mem(priv, a, 0);
  582. for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
  583. iwl_write_targ_mem(priv, a, 0);
  584. /* Tel 4965 where to find Tx byte count tables */
  585. iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
  586. priv->scd_bc_tbls.dma >> 10);
  587. /* Enable DMA channel */
  588. for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
  589. iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
  590. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
  591. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
  592. /* Update FH chicken bits */
  593. reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
  594. iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
  595. reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
  596. /* Disable chain mode for all queues */
  597. iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
  598. /* Initialize each Tx queue (including the command queue) */
  599. for (i = 0; i < priv->hw_params.max_txq_num; i++) {
  600. /* TFD circular buffer read/write indexes */
  601. iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
  602. iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
  603. /* Max Tx Window size for Scheduler-ACK mode */
  604. iwl_write_targ_mem(priv, priv->scd_base_addr +
  605. IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
  606. (SCD_WIN_SIZE <<
  607. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  608. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  609. /* Frame limit */
  610. iwl_write_targ_mem(priv, priv->scd_base_addr +
  611. IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
  612. sizeof(u32),
  613. (SCD_FRAME_LIMIT <<
  614. IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
  615. IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  616. }
  617. iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
  618. (1 << priv->hw_params.max_txq_num) - 1);
  619. /* Activate all Tx DMA/FIFO channels */
  620. priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 6));
  621. iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
  622. /* Map each Tx/cmd queue to its corresponding fifo */
  623. for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
  624. int ac = default_queue_to_tx_fifo[i];
  625. iwl_txq_ctx_activate(priv, i);
  626. iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
  627. }
  628. iwl_release_nic_access(priv);
  629. spin_unlock_irqrestore(&priv->lock, flags);
  630. return ret;
  631. }
  632. static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
  633. .min_nrg_cck = 97,
  634. .max_nrg_cck = 0,
  635. .auto_corr_min_ofdm = 85,
  636. .auto_corr_min_ofdm_mrc = 170,
  637. .auto_corr_min_ofdm_x1 = 105,
  638. .auto_corr_min_ofdm_mrc_x1 = 220,
  639. .auto_corr_max_ofdm = 120,
  640. .auto_corr_max_ofdm_mrc = 210,
  641. .auto_corr_max_ofdm_x1 = 140,
  642. .auto_corr_max_ofdm_mrc_x1 = 270,
  643. .auto_corr_min_cck = 125,
  644. .auto_corr_max_cck = 200,
  645. .auto_corr_min_cck_mrc = 200,
  646. .auto_corr_max_cck_mrc = 400,
  647. .nrg_th_cck = 100,
  648. .nrg_th_ofdm = 100,
  649. };
  650. /**
  651. * iwl4965_hw_set_hw_params
  652. *
  653. * Called when initializing driver
  654. */
  655. static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
  656. {
  657. if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
  658. (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
  659. IWL_ERR(priv,
  660. "invalid queues_num, should be between %d and %d\n",
  661. IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
  662. return -EINVAL;
  663. }
  664. priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
  665. priv->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
  666. priv->hw_params.scd_bc_tbls_size =
  667. IWL49_NUM_QUEUES * sizeof(struct iwl4965_scd_bc_tbl);
  668. priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
  669. priv->hw_params.max_stations = IWL4965_STATION_COUNT;
  670. priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
  671. priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
  672. priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
  673. priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
  674. priv->hw_params.fat_channel = BIT(IEEE80211_BAND_5GHZ);
  675. priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
  676. priv->hw_params.tx_chains_num = 2;
  677. priv->hw_params.rx_chains_num = 2;
  678. priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
  679. priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
  680. priv->hw_params.ct_kill_threshold = CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
  681. priv->hw_params.sens = &iwl4965_sensitivity;
  682. return 0;
  683. }
  684. static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
  685. {
  686. s32 sign = 1;
  687. if (num < 0) {
  688. sign = -sign;
  689. num = -num;
  690. }
  691. if (denom < 0) {
  692. sign = -sign;
  693. denom = -denom;
  694. }
  695. *res = 1;
  696. *res = ((num * 2 + denom) / (denom * 2)) * sign;
  697. return 1;
  698. }
  699. /**
  700. * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
  701. *
  702. * Determines power supply voltage compensation for txpower calculations.
  703. * Returns number of 1/2-dB steps to subtract from gain table index,
  704. * to compensate for difference between power supply voltage during
  705. * factory measurements, vs. current power supply voltage.
  706. *
  707. * Voltage indication is higher for lower voltage.
  708. * Lower voltage requires more gain (lower gain table index).
  709. */
  710. static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
  711. s32 current_voltage)
  712. {
  713. s32 comp = 0;
  714. if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
  715. (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
  716. return 0;
  717. iwl4965_math_div_round(current_voltage - eeprom_voltage,
  718. TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
  719. if (current_voltage > eeprom_voltage)
  720. comp *= 2;
  721. if ((comp < -2) || (comp > 2))
  722. comp = 0;
  723. return comp;
  724. }
  725. static s32 iwl4965_get_tx_atten_grp(u16 channel)
  726. {
  727. if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
  728. channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
  729. return CALIB_CH_GROUP_5;
  730. if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
  731. channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
  732. return CALIB_CH_GROUP_1;
  733. if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
  734. channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
  735. return CALIB_CH_GROUP_2;
  736. if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
  737. channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
  738. return CALIB_CH_GROUP_3;
  739. if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
  740. channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
  741. return CALIB_CH_GROUP_4;
  742. return -1;
  743. }
  744. static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
  745. {
  746. s32 b = -1;
  747. for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
  748. if (priv->calib_info->band_info[b].ch_from == 0)
  749. continue;
  750. if ((channel >= priv->calib_info->band_info[b].ch_from)
  751. && (channel <= priv->calib_info->band_info[b].ch_to))
  752. break;
  753. }
  754. return b;
  755. }
  756. static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
  757. {
  758. s32 val;
  759. if (x2 == x1)
  760. return y1;
  761. else {
  762. iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
  763. return val + y2;
  764. }
  765. }
  766. /**
  767. * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
  768. *
  769. * Interpolates factory measurements from the two sample channels within a
  770. * sub-band, to apply to channel of interest. Interpolation is proportional to
  771. * differences in channel frequencies, which is proportional to differences
  772. * in channel number.
  773. */
  774. static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
  775. struct iwl_eeprom_calib_ch_info *chan_info)
  776. {
  777. s32 s = -1;
  778. u32 c;
  779. u32 m;
  780. const struct iwl_eeprom_calib_measure *m1;
  781. const struct iwl_eeprom_calib_measure *m2;
  782. struct iwl_eeprom_calib_measure *omeas;
  783. u32 ch_i1;
  784. u32 ch_i2;
  785. s = iwl4965_get_sub_band(priv, channel);
  786. if (s >= EEPROM_TX_POWER_BANDS) {
  787. IWL_ERR(priv, "Tx Power can not find channel %d\n", channel);
  788. return -1;
  789. }
  790. ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
  791. ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
  792. chan_info->ch_num = (u8) channel;
  793. IWL_DEBUG_TXPOWER(priv, "channel %d subband %d factory cal ch %d & %d\n",
  794. channel, s, ch_i1, ch_i2);
  795. for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
  796. for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
  797. m1 = &(priv->calib_info->band_info[s].ch1.
  798. measurements[c][m]);
  799. m2 = &(priv->calib_info->band_info[s].ch2.
  800. measurements[c][m]);
  801. omeas = &(chan_info->measurements[c][m]);
  802. omeas->actual_pow =
  803. (u8) iwl4965_interpolate_value(channel, ch_i1,
  804. m1->actual_pow,
  805. ch_i2,
  806. m2->actual_pow);
  807. omeas->gain_idx =
  808. (u8) iwl4965_interpolate_value(channel, ch_i1,
  809. m1->gain_idx, ch_i2,
  810. m2->gain_idx);
  811. omeas->temperature =
  812. (u8) iwl4965_interpolate_value(channel, ch_i1,
  813. m1->temperature,
  814. ch_i2,
  815. m2->temperature);
  816. omeas->pa_det =
  817. (s8) iwl4965_interpolate_value(channel, ch_i1,
  818. m1->pa_det, ch_i2,
  819. m2->pa_det);
  820. IWL_DEBUG_TXPOWER(priv,
  821. "chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
  822. m1->actual_pow, m2->actual_pow, omeas->actual_pow);
  823. IWL_DEBUG_TXPOWER(priv,
  824. "chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
  825. m1->gain_idx, m2->gain_idx, omeas->gain_idx);
  826. IWL_DEBUG_TXPOWER(priv,
  827. "chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
  828. m1->pa_det, m2->pa_det, omeas->pa_det);
  829. IWL_DEBUG_TXPOWER(priv,
  830. "chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
  831. m1->temperature, m2->temperature,
  832. omeas->temperature);
  833. }
  834. }
  835. return 0;
  836. }
  837. /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
  838. * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
  839. static s32 back_off_table[] = {
  840. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
  841. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
  842. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
  843. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
  844. 10 /* CCK */
  845. };
  846. /* Thermal compensation values for txpower for various frequency ranges ...
  847. * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
  848. static struct iwl4965_txpower_comp_entry {
  849. s32 degrees_per_05db_a;
  850. s32 degrees_per_05db_a_denom;
  851. } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
  852. {9, 2}, /* group 0 5.2, ch 34-43 */
  853. {4, 1}, /* group 1 5.2, ch 44-70 */
  854. {4, 1}, /* group 2 5.2, ch 71-124 */
  855. {4, 1}, /* group 3 5.2, ch 125-200 */
  856. {3, 1} /* group 4 2.4, ch all */
  857. };
  858. static s32 get_min_power_index(s32 rate_power_index, u32 band)
  859. {
  860. if (!band) {
  861. if ((rate_power_index & 7) <= 4)
  862. return MIN_TX_GAIN_INDEX_52GHZ_EXT;
  863. }
  864. return MIN_TX_GAIN_INDEX;
  865. }
  866. struct gain_entry {
  867. u8 dsp;
  868. u8 radio;
  869. };
  870. static const struct gain_entry gain_table[2][108] = {
  871. /* 5.2GHz power gain index table */
  872. {
  873. {123, 0x3F}, /* highest txpower */
  874. {117, 0x3F},
  875. {110, 0x3F},
  876. {104, 0x3F},
  877. {98, 0x3F},
  878. {110, 0x3E},
  879. {104, 0x3E},
  880. {98, 0x3E},
  881. {110, 0x3D},
  882. {104, 0x3D},
  883. {98, 0x3D},
  884. {110, 0x3C},
  885. {104, 0x3C},
  886. {98, 0x3C},
  887. {110, 0x3B},
  888. {104, 0x3B},
  889. {98, 0x3B},
  890. {110, 0x3A},
  891. {104, 0x3A},
  892. {98, 0x3A},
  893. {110, 0x39},
  894. {104, 0x39},
  895. {98, 0x39},
  896. {110, 0x38},
  897. {104, 0x38},
  898. {98, 0x38},
  899. {110, 0x37},
  900. {104, 0x37},
  901. {98, 0x37},
  902. {110, 0x36},
  903. {104, 0x36},
  904. {98, 0x36},
  905. {110, 0x35},
  906. {104, 0x35},
  907. {98, 0x35},
  908. {110, 0x34},
  909. {104, 0x34},
  910. {98, 0x34},
  911. {110, 0x33},
  912. {104, 0x33},
  913. {98, 0x33},
  914. {110, 0x32},
  915. {104, 0x32},
  916. {98, 0x32},
  917. {110, 0x31},
  918. {104, 0x31},
  919. {98, 0x31},
  920. {110, 0x30},
  921. {104, 0x30},
  922. {98, 0x30},
  923. {110, 0x25},
  924. {104, 0x25},
  925. {98, 0x25},
  926. {110, 0x24},
  927. {104, 0x24},
  928. {98, 0x24},
  929. {110, 0x23},
  930. {104, 0x23},
  931. {98, 0x23},
  932. {110, 0x22},
  933. {104, 0x18},
  934. {98, 0x18},
  935. {110, 0x17},
  936. {104, 0x17},
  937. {98, 0x17},
  938. {110, 0x16},
  939. {104, 0x16},
  940. {98, 0x16},
  941. {110, 0x15},
  942. {104, 0x15},
  943. {98, 0x15},
  944. {110, 0x14},
  945. {104, 0x14},
  946. {98, 0x14},
  947. {110, 0x13},
  948. {104, 0x13},
  949. {98, 0x13},
  950. {110, 0x12},
  951. {104, 0x08},
  952. {98, 0x08},
  953. {110, 0x07},
  954. {104, 0x07},
  955. {98, 0x07},
  956. {110, 0x06},
  957. {104, 0x06},
  958. {98, 0x06},
  959. {110, 0x05},
  960. {104, 0x05},
  961. {98, 0x05},
  962. {110, 0x04},
  963. {104, 0x04},
  964. {98, 0x04},
  965. {110, 0x03},
  966. {104, 0x03},
  967. {98, 0x03},
  968. {110, 0x02},
  969. {104, 0x02},
  970. {98, 0x02},
  971. {110, 0x01},
  972. {104, 0x01},
  973. {98, 0x01},
  974. {110, 0x00},
  975. {104, 0x00},
  976. {98, 0x00},
  977. {93, 0x00},
  978. {88, 0x00},
  979. {83, 0x00},
  980. {78, 0x00},
  981. },
  982. /* 2.4GHz power gain index table */
  983. {
  984. {110, 0x3f}, /* highest txpower */
  985. {104, 0x3f},
  986. {98, 0x3f},
  987. {110, 0x3e},
  988. {104, 0x3e},
  989. {98, 0x3e},
  990. {110, 0x3d},
  991. {104, 0x3d},
  992. {98, 0x3d},
  993. {110, 0x3c},
  994. {104, 0x3c},
  995. {98, 0x3c},
  996. {110, 0x3b},
  997. {104, 0x3b},
  998. {98, 0x3b},
  999. {110, 0x3a},
  1000. {104, 0x3a},
  1001. {98, 0x3a},
  1002. {110, 0x39},
  1003. {104, 0x39},
  1004. {98, 0x39},
  1005. {110, 0x38},
  1006. {104, 0x38},
  1007. {98, 0x38},
  1008. {110, 0x37},
  1009. {104, 0x37},
  1010. {98, 0x37},
  1011. {110, 0x36},
  1012. {104, 0x36},
  1013. {98, 0x36},
  1014. {110, 0x35},
  1015. {104, 0x35},
  1016. {98, 0x35},
  1017. {110, 0x34},
  1018. {104, 0x34},
  1019. {98, 0x34},
  1020. {110, 0x33},
  1021. {104, 0x33},
  1022. {98, 0x33},
  1023. {110, 0x32},
  1024. {104, 0x32},
  1025. {98, 0x32},
  1026. {110, 0x31},
  1027. {104, 0x31},
  1028. {98, 0x31},
  1029. {110, 0x30},
  1030. {104, 0x30},
  1031. {98, 0x30},
  1032. {110, 0x6},
  1033. {104, 0x6},
  1034. {98, 0x6},
  1035. {110, 0x5},
  1036. {104, 0x5},
  1037. {98, 0x5},
  1038. {110, 0x4},
  1039. {104, 0x4},
  1040. {98, 0x4},
  1041. {110, 0x3},
  1042. {104, 0x3},
  1043. {98, 0x3},
  1044. {110, 0x2},
  1045. {104, 0x2},
  1046. {98, 0x2},
  1047. {110, 0x1},
  1048. {104, 0x1},
  1049. {98, 0x1},
  1050. {110, 0x0},
  1051. {104, 0x0},
  1052. {98, 0x0},
  1053. {97, 0},
  1054. {96, 0},
  1055. {95, 0},
  1056. {94, 0},
  1057. {93, 0},
  1058. {92, 0},
  1059. {91, 0},
  1060. {90, 0},
  1061. {89, 0},
  1062. {88, 0},
  1063. {87, 0},
  1064. {86, 0},
  1065. {85, 0},
  1066. {84, 0},
  1067. {83, 0},
  1068. {82, 0},
  1069. {81, 0},
  1070. {80, 0},
  1071. {79, 0},
  1072. {78, 0},
  1073. {77, 0},
  1074. {76, 0},
  1075. {75, 0},
  1076. {74, 0},
  1077. {73, 0},
  1078. {72, 0},
  1079. {71, 0},
  1080. {70, 0},
  1081. {69, 0},
  1082. {68, 0},
  1083. {67, 0},
  1084. {66, 0},
  1085. {65, 0},
  1086. {64, 0},
  1087. {63, 0},
  1088. {62, 0},
  1089. {61, 0},
  1090. {60, 0},
  1091. {59, 0},
  1092. }
  1093. };
  1094. static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
  1095. u8 is_fat, u8 ctrl_chan_high,
  1096. struct iwl4965_tx_power_db *tx_power_tbl)
  1097. {
  1098. u8 saturation_power;
  1099. s32 target_power;
  1100. s32 user_target_power;
  1101. s32 power_limit;
  1102. s32 current_temp;
  1103. s32 reg_limit;
  1104. s32 current_regulatory;
  1105. s32 txatten_grp = CALIB_CH_GROUP_MAX;
  1106. int i;
  1107. int c;
  1108. const struct iwl_channel_info *ch_info = NULL;
  1109. struct iwl_eeprom_calib_ch_info ch_eeprom_info;
  1110. const struct iwl_eeprom_calib_measure *measurement;
  1111. s16 voltage;
  1112. s32 init_voltage;
  1113. s32 voltage_compensation;
  1114. s32 degrees_per_05db_num;
  1115. s32 degrees_per_05db_denom;
  1116. s32 factory_temp;
  1117. s32 temperature_comp[2];
  1118. s32 factory_gain_index[2];
  1119. s32 factory_actual_pwr[2];
  1120. s32 power_index;
  1121. /* tx_power_user_lmt is in dBm, convert to half-dBm (half-dB units
  1122. * are used for indexing into txpower table) */
  1123. user_target_power = 2 * priv->tx_power_user_lmt;
  1124. /* Get current (RXON) channel, band, width */
  1125. IWL_DEBUG_TXPOWER(priv, "chan %d band %d is_fat %d\n", channel, band,
  1126. is_fat);
  1127. ch_info = iwl_get_channel_info(priv, priv->band, channel);
  1128. if (!is_channel_valid(ch_info))
  1129. return -EINVAL;
  1130. /* get txatten group, used to select 1) thermal txpower adjustment
  1131. * and 2) mimo txpower balance between Tx chains. */
  1132. txatten_grp = iwl4965_get_tx_atten_grp(channel);
  1133. if (txatten_grp < 0) {
  1134. IWL_ERR(priv, "Can't find txatten group for channel %d.\n",
  1135. channel);
  1136. return -EINVAL;
  1137. }
  1138. IWL_DEBUG_TXPOWER(priv, "channel %d belongs to txatten group %d\n",
  1139. channel, txatten_grp);
  1140. if (is_fat) {
  1141. if (ctrl_chan_high)
  1142. channel -= 2;
  1143. else
  1144. channel += 2;
  1145. }
  1146. /* hardware txpower limits ...
  1147. * saturation (clipping distortion) txpowers are in half-dBm */
  1148. if (band)
  1149. saturation_power = priv->calib_info->saturation_power24;
  1150. else
  1151. saturation_power = priv->calib_info->saturation_power52;
  1152. if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
  1153. saturation_power > IWL_TX_POWER_SATURATION_MAX) {
  1154. if (band)
  1155. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
  1156. else
  1157. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
  1158. }
  1159. /* regulatory txpower limits ... reg_limit values are in half-dBm,
  1160. * max_power_avg values are in dBm, convert * 2 */
  1161. if (is_fat)
  1162. reg_limit = ch_info->fat_max_power_avg * 2;
  1163. else
  1164. reg_limit = ch_info->max_power_avg * 2;
  1165. if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
  1166. (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
  1167. if (band)
  1168. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
  1169. else
  1170. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
  1171. }
  1172. /* Interpolate txpower calibration values for this channel,
  1173. * based on factory calibration tests on spaced channels. */
  1174. iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
  1175. /* calculate tx gain adjustment based on power supply voltage */
  1176. voltage = priv->calib_info->voltage;
  1177. init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
  1178. voltage_compensation =
  1179. iwl4965_get_voltage_compensation(voltage, init_voltage);
  1180. IWL_DEBUG_TXPOWER(priv, "curr volt %d eeprom volt %d volt comp %d\n",
  1181. init_voltage,
  1182. voltage, voltage_compensation);
  1183. /* get current temperature (Celsius) */
  1184. current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
  1185. current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
  1186. current_temp = KELVIN_TO_CELSIUS(current_temp);
  1187. /* select thermal txpower adjustment params, based on channel group
  1188. * (same frequency group used for mimo txatten adjustment) */
  1189. degrees_per_05db_num =
  1190. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
  1191. degrees_per_05db_denom =
  1192. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
  1193. /* get per-chain txpower values from factory measurements */
  1194. for (c = 0; c < 2; c++) {
  1195. measurement = &ch_eeprom_info.measurements[c][1];
  1196. /* txgain adjustment (in half-dB steps) based on difference
  1197. * between factory and current temperature */
  1198. factory_temp = measurement->temperature;
  1199. iwl4965_math_div_round((current_temp - factory_temp) *
  1200. degrees_per_05db_denom,
  1201. degrees_per_05db_num,
  1202. &temperature_comp[c]);
  1203. factory_gain_index[c] = measurement->gain_idx;
  1204. factory_actual_pwr[c] = measurement->actual_pow;
  1205. IWL_DEBUG_TXPOWER(priv, "chain = %d\n", c);
  1206. IWL_DEBUG_TXPOWER(priv, "fctry tmp %d, "
  1207. "curr tmp %d, comp %d steps\n",
  1208. factory_temp, current_temp,
  1209. temperature_comp[c]);
  1210. IWL_DEBUG_TXPOWER(priv, "fctry idx %d, fctry pwr %d\n",
  1211. factory_gain_index[c],
  1212. factory_actual_pwr[c]);
  1213. }
  1214. /* for each of 33 bit-rates (including 1 for CCK) */
  1215. for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
  1216. u8 is_mimo_rate;
  1217. union iwl4965_tx_power_dual_stream tx_power;
  1218. /* for mimo, reduce each chain's txpower by half
  1219. * (3dB, 6 steps), so total output power is regulatory
  1220. * compliant. */
  1221. if (i & 0x8) {
  1222. current_regulatory = reg_limit -
  1223. IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
  1224. is_mimo_rate = 1;
  1225. } else {
  1226. current_regulatory = reg_limit;
  1227. is_mimo_rate = 0;
  1228. }
  1229. /* find txpower limit, either hardware or regulatory */
  1230. power_limit = saturation_power - back_off_table[i];
  1231. if (power_limit > current_regulatory)
  1232. power_limit = current_regulatory;
  1233. /* reduce user's txpower request if necessary
  1234. * for this rate on this channel */
  1235. target_power = user_target_power;
  1236. if (target_power > power_limit)
  1237. target_power = power_limit;
  1238. IWL_DEBUG_TXPOWER(priv, "rate %d sat %d reg %d usr %d tgt %d\n",
  1239. i, saturation_power - back_off_table[i],
  1240. current_regulatory, user_target_power,
  1241. target_power);
  1242. /* for each of 2 Tx chains (radio transmitters) */
  1243. for (c = 0; c < 2; c++) {
  1244. s32 atten_value;
  1245. if (is_mimo_rate)
  1246. atten_value =
  1247. (s32)le32_to_cpu(priv->card_alive_init.
  1248. tx_atten[txatten_grp][c]);
  1249. else
  1250. atten_value = 0;
  1251. /* calculate index; higher index means lower txpower */
  1252. power_index = (u8) (factory_gain_index[c] -
  1253. (target_power -
  1254. factory_actual_pwr[c]) -
  1255. temperature_comp[c] -
  1256. voltage_compensation +
  1257. atten_value);
  1258. /* IWL_DEBUG_TXPOWER(priv, "calculated txpower index %d\n",
  1259. power_index); */
  1260. if (power_index < get_min_power_index(i, band))
  1261. power_index = get_min_power_index(i, band);
  1262. /* adjust 5 GHz index to support negative indexes */
  1263. if (!band)
  1264. power_index += 9;
  1265. /* CCK, rate 32, reduce txpower for CCK */
  1266. if (i == POWER_TABLE_CCK_ENTRY)
  1267. power_index +=
  1268. IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
  1269. /* stay within the table! */
  1270. if (power_index > 107) {
  1271. IWL_WARN(priv, "txpower index %d > 107\n",
  1272. power_index);
  1273. power_index = 107;
  1274. }
  1275. if (power_index < 0) {
  1276. IWL_WARN(priv, "txpower index %d < 0\n",
  1277. power_index);
  1278. power_index = 0;
  1279. }
  1280. /* fill txpower command for this rate/chain */
  1281. tx_power.s.radio_tx_gain[c] =
  1282. gain_table[band][power_index].radio;
  1283. tx_power.s.dsp_predis_atten[c] =
  1284. gain_table[band][power_index].dsp;
  1285. IWL_DEBUG_TXPOWER(priv, "chain %d mimo %d index %d "
  1286. "gain 0x%02x dsp %d\n",
  1287. c, atten_value, power_index,
  1288. tx_power.s.radio_tx_gain[c],
  1289. tx_power.s.dsp_predis_atten[c]);
  1290. } /* for each chain */
  1291. tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
  1292. } /* for each rate */
  1293. return 0;
  1294. }
  1295. /**
  1296. * iwl4965_send_tx_power - Configure the TXPOWER level user limit
  1297. *
  1298. * Uses the active RXON for channel, band, and characteristics (fat, high)
  1299. * The power limit is taken from priv->tx_power_user_lmt.
  1300. */
  1301. static int iwl4965_send_tx_power(struct iwl_priv *priv)
  1302. {
  1303. struct iwl4965_txpowertable_cmd cmd = { 0 };
  1304. int ret;
  1305. u8 band = 0;
  1306. u8 is_fat = 0;
  1307. u8 ctrl_chan_high = 0;
  1308. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1309. /* If this gets hit a lot, switch it to a BUG() and catch
  1310. * the stack trace to find out who is calling this during
  1311. * a scan. */
  1312. IWL_WARN(priv, "TX Power requested while scanning!\n");
  1313. return -EAGAIN;
  1314. }
  1315. band = priv->band == IEEE80211_BAND_2GHZ;
  1316. is_fat = is_fat_channel(priv->active_rxon.flags);
  1317. if (is_fat &&
  1318. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  1319. ctrl_chan_high = 1;
  1320. cmd.band = band;
  1321. cmd.channel = priv->active_rxon.channel;
  1322. ret = iwl4965_fill_txpower_tbl(priv, band,
  1323. le16_to_cpu(priv->active_rxon.channel),
  1324. is_fat, ctrl_chan_high, &cmd.tx_power);
  1325. if (ret)
  1326. goto out;
  1327. ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
  1328. out:
  1329. return ret;
  1330. }
  1331. static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
  1332. {
  1333. int ret = 0;
  1334. struct iwl4965_rxon_assoc_cmd rxon_assoc;
  1335. const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
  1336. const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
  1337. if ((rxon1->flags == rxon2->flags) &&
  1338. (rxon1->filter_flags == rxon2->filter_flags) &&
  1339. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  1340. (rxon1->ofdm_ht_single_stream_basic_rates ==
  1341. rxon2->ofdm_ht_single_stream_basic_rates) &&
  1342. (rxon1->ofdm_ht_dual_stream_basic_rates ==
  1343. rxon2->ofdm_ht_dual_stream_basic_rates) &&
  1344. (rxon1->rx_chain == rxon2->rx_chain) &&
  1345. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  1346. IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
  1347. return 0;
  1348. }
  1349. rxon_assoc.flags = priv->staging_rxon.flags;
  1350. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  1351. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  1352. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  1353. rxon_assoc.reserved = 0;
  1354. rxon_assoc.ofdm_ht_single_stream_basic_rates =
  1355. priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
  1356. rxon_assoc.ofdm_ht_dual_stream_basic_rates =
  1357. priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
  1358. rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
  1359. ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
  1360. sizeof(rxon_assoc), &rxon_assoc, NULL);
  1361. if (ret)
  1362. return ret;
  1363. return ret;
  1364. }
  1365. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  1366. static int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
  1367. {
  1368. int rc;
  1369. u8 band = 0;
  1370. u8 is_fat = 0;
  1371. u8 ctrl_chan_high = 0;
  1372. struct iwl4965_channel_switch_cmd cmd = { 0 };
  1373. const struct iwl_channel_info *ch_info;
  1374. band = priv->band == IEEE80211_BAND_2GHZ;
  1375. ch_info = iwl_get_channel_info(priv, priv->band, channel);
  1376. is_fat = is_fat_channel(priv->staging_rxon.flags);
  1377. if (is_fat &&
  1378. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  1379. ctrl_chan_high = 1;
  1380. cmd.band = band;
  1381. cmd.expect_beacon = 0;
  1382. cmd.channel = cpu_to_le16(channel);
  1383. cmd.rxon_flags = priv->active_rxon.flags;
  1384. cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
  1385. cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
  1386. if (ch_info)
  1387. cmd.expect_beacon = is_channel_radar(ch_info);
  1388. else
  1389. cmd.expect_beacon = 1;
  1390. rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
  1391. ctrl_chan_high, &cmd.tx_power);
  1392. if (rc) {
  1393. IWL_DEBUG_11H(priv, "error:%d fill txpower_tbl\n", rc);
  1394. return rc;
  1395. }
  1396. rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
  1397. return rc;
  1398. }
  1399. #endif
  1400. /**
  1401. * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
  1402. */
  1403. static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
  1404. struct iwl_tx_queue *txq,
  1405. u16 byte_cnt)
  1406. {
  1407. struct iwl4965_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
  1408. int txq_id = txq->q.id;
  1409. int write_ptr = txq->q.write_ptr;
  1410. int len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  1411. __le16 bc_ent;
  1412. WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
  1413. bc_ent = cpu_to_le16(len & 0xFFF);
  1414. /* Set up byte count within first 256 entries */
  1415. scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
  1416. /* If within first 64 entries, duplicate at end */
  1417. if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
  1418. scd_bc_tbl[txq_id].
  1419. tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
  1420. }
  1421. /**
  1422. * sign_extend - Sign extend a value using specified bit as sign-bit
  1423. *
  1424. * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
  1425. * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
  1426. *
  1427. * @param oper value to sign extend
  1428. * @param index 0 based bit index (0<=index<32) to sign bit
  1429. */
  1430. static s32 sign_extend(u32 oper, int index)
  1431. {
  1432. u8 shift = 31 - index;
  1433. return (s32)(oper << shift) >> shift;
  1434. }
  1435. /**
  1436. * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin)
  1437. * @statistics: Provides the temperature reading from the uCode
  1438. *
  1439. * A return of <0 indicates bogus data in the statistics
  1440. */
  1441. static int iwl4965_hw_get_temperature(const struct iwl_priv *priv)
  1442. {
  1443. s32 temperature;
  1444. s32 vt;
  1445. s32 R1, R2, R3;
  1446. u32 R4;
  1447. if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
  1448. (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
  1449. IWL_DEBUG_TEMP(priv, "Running FAT temperature calibration\n");
  1450. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  1451. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  1452. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  1453. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
  1454. } else {
  1455. IWL_DEBUG_TEMP(priv, "Running temperature calibration\n");
  1456. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  1457. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  1458. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  1459. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
  1460. }
  1461. /*
  1462. * Temperature is only 23 bits, so sign extend out to 32.
  1463. *
  1464. * NOTE If we haven't received a statistics notification yet
  1465. * with an updated temperature, use R4 provided to us in the
  1466. * "initialize" ALIVE response.
  1467. */
  1468. if (!test_bit(STATUS_TEMPERATURE, &priv->status))
  1469. vt = sign_extend(R4, 23);
  1470. else
  1471. vt = sign_extend(
  1472. le32_to_cpu(priv->statistics.general.temperature), 23);
  1473. IWL_DEBUG_TEMP(priv, "Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt);
  1474. if (R3 == R1) {
  1475. IWL_ERR(priv, "Calibration conflict R1 == R3\n");
  1476. return -1;
  1477. }
  1478. /* Calculate temperature in degrees Kelvin, adjust by 97%.
  1479. * Add offset to center the adjustment around 0 degrees Centigrade. */
  1480. temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
  1481. temperature /= (R3 - R1);
  1482. temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET;
  1483. IWL_DEBUG_TEMP(priv, "Calibrated temperature: %dK, %dC\n",
  1484. temperature, KELVIN_TO_CELSIUS(temperature));
  1485. return temperature;
  1486. }
  1487. /* Adjust Txpower only if temperature variance is greater than threshold. */
  1488. #define IWL_TEMPERATURE_THRESHOLD 3
  1489. /**
  1490. * iwl4965_is_temp_calib_needed - determines if new calibration is needed
  1491. *
  1492. * If the temperature changed has changed sufficiently, then a recalibration
  1493. * is needed.
  1494. *
  1495. * Assumes caller will replace priv->last_temperature once calibration
  1496. * executed.
  1497. */
  1498. static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
  1499. {
  1500. int temp_diff;
  1501. if (!test_bit(STATUS_STATISTICS, &priv->status)) {
  1502. IWL_DEBUG_TEMP(priv, "Temperature not updated -- no statistics.\n");
  1503. return 0;
  1504. }
  1505. temp_diff = priv->temperature - priv->last_temperature;
  1506. /* get absolute value */
  1507. if (temp_diff < 0) {
  1508. IWL_DEBUG_POWER(priv, "Getting cooler, delta %d, \n", temp_diff);
  1509. temp_diff = -temp_diff;
  1510. } else if (temp_diff == 0)
  1511. IWL_DEBUG_POWER(priv, "Same temp, \n");
  1512. else
  1513. IWL_DEBUG_POWER(priv, "Getting warmer, delta %d, \n", temp_diff);
  1514. if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
  1515. IWL_DEBUG_POWER(priv, "Thermal txpower calib not needed\n");
  1516. return 0;
  1517. }
  1518. IWL_DEBUG_POWER(priv, "Thermal txpower calib needed\n");
  1519. return 1;
  1520. }
  1521. static void iwl4965_temperature_calib(struct iwl_priv *priv)
  1522. {
  1523. s32 temp;
  1524. temp = iwl4965_hw_get_temperature(priv);
  1525. if (temp < 0)
  1526. return;
  1527. if (priv->temperature != temp) {
  1528. if (priv->temperature)
  1529. IWL_DEBUG_TEMP(priv, "Temperature changed "
  1530. "from %dC to %dC\n",
  1531. KELVIN_TO_CELSIUS(priv->temperature),
  1532. KELVIN_TO_CELSIUS(temp));
  1533. else
  1534. IWL_DEBUG_TEMP(priv, "Temperature "
  1535. "initialized to %dC\n",
  1536. KELVIN_TO_CELSIUS(temp));
  1537. }
  1538. priv->temperature = temp;
  1539. set_bit(STATUS_TEMPERATURE, &priv->status);
  1540. if (!priv->disable_tx_power_cal &&
  1541. unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  1542. iwl4965_is_temp_calib_needed(priv))
  1543. queue_work(priv->workqueue, &priv->txpower_work);
  1544. }
  1545. /**
  1546. * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
  1547. */
  1548. static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
  1549. u16 txq_id)
  1550. {
  1551. /* Simply stop the queue, but don't change any configuration;
  1552. * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
  1553. iwl_write_prph(priv,
  1554. IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  1555. (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
  1556. (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
  1557. }
  1558. /**
  1559. * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
  1560. * priv->lock must be held by the caller
  1561. */
  1562. static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
  1563. u16 ssn_idx, u8 tx_fifo)
  1564. {
  1565. int ret = 0;
  1566. if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
  1567. (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
  1568. IWL_WARN(priv,
  1569. "queue number out of range: %d, must be %d to %d\n",
  1570. txq_id, IWL49_FIRST_AMPDU_QUEUE,
  1571. IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
  1572. return -EINVAL;
  1573. }
  1574. ret = iwl_grab_nic_access(priv);
  1575. if (ret)
  1576. return ret;
  1577. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  1578. iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  1579. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  1580. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  1581. /* supposes that ssn_idx is valid (!= 0xFFF) */
  1582. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  1583. iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  1584. iwl_txq_ctx_deactivate(priv, txq_id);
  1585. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
  1586. iwl_release_nic_access(priv);
  1587. return 0;
  1588. }
  1589. /**
  1590. * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
  1591. */
  1592. static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
  1593. u16 txq_id)
  1594. {
  1595. u32 tbl_dw_addr;
  1596. u32 tbl_dw;
  1597. u16 scd_q2ratid;
  1598. scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
  1599. tbl_dw_addr = priv->scd_base_addr +
  1600. IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
  1601. tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
  1602. if (txq_id & 0x1)
  1603. tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
  1604. else
  1605. tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
  1606. iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
  1607. return 0;
  1608. }
  1609. /**
  1610. * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
  1611. *
  1612. * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
  1613. * i.e. it must be one of the higher queues used for aggregation
  1614. */
  1615. static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
  1616. int tx_fifo, int sta_id, int tid, u16 ssn_idx)
  1617. {
  1618. unsigned long flags;
  1619. int ret;
  1620. u16 ra_tid;
  1621. if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
  1622. (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
  1623. IWL_WARN(priv,
  1624. "queue number out of range: %d, must be %d to %d\n",
  1625. txq_id, IWL49_FIRST_AMPDU_QUEUE,
  1626. IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
  1627. return -EINVAL;
  1628. }
  1629. ra_tid = BUILD_RAxTID(sta_id, tid);
  1630. /* Modify device's station table to Tx this TID */
  1631. iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
  1632. spin_lock_irqsave(&priv->lock, flags);
  1633. ret = iwl_grab_nic_access(priv);
  1634. if (ret) {
  1635. spin_unlock_irqrestore(&priv->lock, flags);
  1636. return ret;
  1637. }
  1638. /* Stop this Tx queue before configuring it */
  1639. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  1640. /* Map receiver-address / traffic-ID to this queue */
  1641. iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
  1642. /* Set this queue as a chain-building queue */
  1643. iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  1644. /* Place first TFD at index corresponding to start sequence number.
  1645. * Assumes that ssn_idx is valid (!= 0xFFF) */
  1646. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  1647. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  1648. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  1649. /* Set up Tx window size and frame limit for this queue */
  1650. iwl_write_targ_mem(priv,
  1651. priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
  1652. (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  1653. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  1654. iwl_write_targ_mem(priv, priv->scd_base_addr +
  1655. IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
  1656. (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
  1657. & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  1658. iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
  1659. /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
  1660. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
  1661. iwl_release_nic_access(priv);
  1662. spin_unlock_irqrestore(&priv->lock, flags);
  1663. return 0;
  1664. }
  1665. static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
  1666. {
  1667. switch (cmd_id) {
  1668. case REPLY_RXON:
  1669. return (u16) sizeof(struct iwl4965_rxon_cmd);
  1670. default:
  1671. return len;
  1672. }
  1673. }
  1674. static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
  1675. {
  1676. struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
  1677. addsta->mode = cmd->mode;
  1678. memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
  1679. memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
  1680. addsta->station_flags = cmd->station_flags;
  1681. addsta->station_flags_msk = cmd->station_flags_msk;
  1682. addsta->tid_disable_tx = cmd->tid_disable_tx;
  1683. addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
  1684. addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
  1685. addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
  1686. addsta->reserved1 = cpu_to_le16(0);
  1687. addsta->reserved2 = cpu_to_le32(0);
  1688. return (u16)sizeof(struct iwl4965_addsta_cmd);
  1689. }
  1690. static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
  1691. {
  1692. return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
  1693. }
  1694. /**
  1695. * iwl4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
  1696. */
  1697. static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
  1698. struct iwl_ht_agg *agg,
  1699. struct iwl4965_tx_resp *tx_resp,
  1700. int txq_id, u16 start_idx)
  1701. {
  1702. u16 status;
  1703. struct agg_tx_status *frame_status = tx_resp->u.agg_status;
  1704. struct ieee80211_tx_info *info = NULL;
  1705. struct ieee80211_hdr *hdr = NULL;
  1706. u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
  1707. int i, sh, idx;
  1708. u16 seq;
  1709. if (agg->wait_for_ba)
  1710. IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
  1711. agg->frame_count = tx_resp->frame_count;
  1712. agg->start_idx = start_idx;
  1713. agg->rate_n_flags = rate_n_flags;
  1714. agg->bitmap = 0;
  1715. /* num frames attempted by Tx command */
  1716. if (agg->frame_count == 1) {
  1717. /* Only one frame was attempted; no block-ack will arrive */
  1718. status = le16_to_cpu(frame_status[0].status);
  1719. idx = start_idx;
  1720. /* FIXME: code repetition */
  1721. IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
  1722. agg->frame_count, agg->start_idx, idx);
  1723. info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
  1724. info->status.rates[0].count = tx_resp->failure_frame + 1;
  1725. info->flags &= ~IEEE80211_TX_CTL_AMPDU;
  1726. info->flags |= iwl_is_tx_success(status) ?
  1727. IEEE80211_TX_STAT_ACK : 0;
  1728. iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
  1729. /* FIXME: code repetition end */
  1730. IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
  1731. status & 0xff, tx_resp->failure_frame);
  1732. IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
  1733. agg->wait_for_ba = 0;
  1734. } else {
  1735. /* Two or more frames were attempted; expect block-ack */
  1736. u64 bitmap = 0;
  1737. int start = agg->start_idx;
  1738. /* Construct bit-map of pending frames within Tx window */
  1739. for (i = 0; i < agg->frame_count; i++) {
  1740. u16 sc;
  1741. status = le16_to_cpu(frame_status[i].status);
  1742. seq = le16_to_cpu(frame_status[i].sequence);
  1743. idx = SEQ_TO_INDEX(seq);
  1744. txq_id = SEQ_TO_QUEUE(seq);
  1745. if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
  1746. AGG_TX_STATE_ABORT_MSK))
  1747. continue;
  1748. IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
  1749. agg->frame_count, txq_id, idx);
  1750. hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
  1751. sc = le16_to_cpu(hdr->seq_ctrl);
  1752. if (idx != (SEQ_TO_SN(sc) & 0xff)) {
  1753. IWL_ERR(priv,
  1754. "BUG_ON idx doesn't match seq control"
  1755. " idx=%d, seq_idx=%d, seq=%d\n",
  1756. idx, SEQ_TO_SN(sc), hdr->seq_ctrl);
  1757. return -1;
  1758. }
  1759. IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
  1760. i, idx, SEQ_TO_SN(sc));
  1761. sh = idx - start;
  1762. if (sh > 64) {
  1763. sh = (start - idx) + 0xff;
  1764. bitmap = bitmap << sh;
  1765. sh = 0;
  1766. start = idx;
  1767. } else if (sh < -64)
  1768. sh = 0xff - (start - idx);
  1769. else if (sh < 0) {
  1770. sh = start - idx;
  1771. start = idx;
  1772. bitmap = bitmap << sh;
  1773. sh = 0;
  1774. }
  1775. bitmap |= 1ULL << sh;
  1776. IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
  1777. start, (unsigned long long)bitmap);
  1778. }
  1779. agg->bitmap = bitmap;
  1780. agg->start_idx = start;
  1781. IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
  1782. agg->frame_count, agg->start_idx,
  1783. (unsigned long long)agg->bitmap);
  1784. if (bitmap)
  1785. agg->wait_for_ba = 1;
  1786. }
  1787. return 0;
  1788. }
  1789. /**
  1790. * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
  1791. */
  1792. static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
  1793. struct iwl_rx_mem_buffer *rxb)
  1794. {
  1795. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  1796. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  1797. int txq_id = SEQ_TO_QUEUE(sequence);
  1798. int index = SEQ_TO_INDEX(sequence);
  1799. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  1800. struct ieee80211_hdr *hdr;
  1801. struct ieee80211_tx_info *info;
  1802. struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
  1803. u32 status = le32_to_cpu(tx_resp->u.status);
  1804. int tid = MAX_TID_COUNT;
  1805. int sta_id;
  1806. int freed;
  1807. u8 *qc = NULL;
  1808. if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
  1809. IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
  1810. "is out of range [0-%d] %d %d\n", txq_id,
  1811. index, txq->q.n_bd, txq->q.write_ptr,
  1812. txq->q.read_ptr);
  1813. return;
  1814. }
  1815. info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
  1816. memset(&info->status, 0, sizeof(info->status));
  1817. hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
  1818. if (ieee80211_is_data_qos(hdr->frame_control)) {
  1819. qc = ieee80211_get_qos_ctl(hdr);
  1820. tid = qc[0] & 0xf;
  1821. }
  1822. sta_id = iwl_get_ra_sta_id(priv, hdr);
  1823. if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
  1824. IWL_ERR(priv, "Station not known\n");
  1825. return;
  1826. }
  1827. if (txq->sched_retry) {
  1828. const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
  1829. struct iwl_ht_agg *agg = NULL;
  1830. WARN_ON(!qc);
  1831. agg = &priv->stations[sta_id].tid[tid].agg;
  1832. iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
  1833. /* check if BAR is needed */
  1834. if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
  1835. info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
  1836. if (txq->q.read_ptr != (scd_ssn & 0xff)) {
  1837. index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
  1838. IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim scd_ssn "
  1839. "%d index %d\n", scd_ssn , index);
  1840. freed = iwl_tx_queue_reclaim(priv, txq_id, index);
  1841. priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
  1842. if (priv->mac80211_registered &&
  1843. (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
  1844. (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
  1845. if (agg->state == IWL_AGG_OFF)
  1846. iwl_wake_queue(priv, txq_id);
  1847. else
  1848. iwl_wake_queue(priv, txq->swq_id);
  1849. }
  1850. }
  1851. } else {
  1852. info->status.rates[0].count = tx_resp->failure_frame + 1;
  1853. info->flags |= iwl_is_tx_success(status) ?
  1854. IEEE80211_TX_STAT_ACK : 0;
  1855. iwl_hwrate_to_tx_control(priv,
  1856. le32_to_cpu(tx_resp->rate_n_flags),
  1857. info);
  1858. IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) "
  1859. "rate_n_flags 0x%x retries %d\n",
  1860. txq_id,
  1861. iwl_get_tx_fail_reason(status), status,
  1862. le32_to_cpu(tx_resp->rate_n_flags),
  1863. tx_resp->failure_frame);
  1864. freed = iwl_tx_queue_reclaim(priv, txq_id, index);
  1865. if (qc && likely(sta_id != IWL_INVALID_STATION))
  1866. priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
  1867. if (priv->mac80211_registered &&
  1868. (iwl_queue_space(&txq->q) > txq->q.low_mark))
  1869. iwl_wake_queue(priv, txq_id);
  1870. }
  1871. if (qc && likely(sta_id != IWL_INVALID_STATION))
  1872. iwl_txq_check_empty(priv, sta_id, tid, txq_id);
  1873. if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
  1874. IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
  1875. }
  1876. static int iwl4965_calc_rssi(struct iwl_priv *priv,
  1877. struct iwl_rx_phy_res *rx_resp)
  1878. {
  1879. /* data from PHY/DSP regarding signal strength, etc.,
  1880. * contents are always there, not configurable by host. */
  1881. struct iwl4965_rx_non_cfg_phy *ncphy =
  1882. (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
  1883. u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL49_AGC_DB_MASK)
  1884. >> IWL49_AGC_DB_POS;
  1885. u32 valid_antennae =
  1886. (le16_to_cpu(rx_resp->phy_flags) & IWL49_RX_PHY_FLAGS_ANTENNAE_MASK)
  1887. >> IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
  1888. u8 max_rssi = 0;
  1889. u32 i;
  1890. /* Find max rssi among 3 possible receivers.
  1891. * These values are measured by the digital signal processor (DSP).
  1892. * They should stay fairly constant even as the signal strength varies,
  1893. * if the radio's automatic gain control (AGC) is working right.
  1894. * AGC value (see below) will provide the "interesting" info. */
  1895. for (i = 0; i < 3; i++)
  1896. if (valid_antennae & (1 << i))
  1897. max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
  1898. IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
  1899. ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
  1900. max_rssi, agc);
  1901. /* dBm = max_rssi dB - agc dB - constant.
  1902. * Higher AGC (higher radio gain) means lower signal. */
  1903. return max_rssi - agc - IWL49_RSSI_OFFSET;
  1904. }
  1905. /* Set up 4965-specific Rx frame reply handlers */
  1906. static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
  1907. {
  1908. /* Legacy Rx frames */
  1909. priv->rx_handlers[REPLY_RX] = iwl_rx_reply_rx;
  1910. /* Tx response */
  1911. priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
  1912. }
  1913. static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
  1914. {
  1915. INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
  1916. }
  1917. static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
  1918. {
  1919. cancel_work_sync(&priv->txpower_work);
  1920. }
  1921. static struct iwl_hcmd_ops iwl4965_hcmd = {
  1922. .rxon_assoc = iwl4965_send_rxon_assoc,
  1923. };
  1924. static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
  1925. .get_hcmd_size = iwl4965_get_hcmd_size,
  1926. .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
  1927. .chain_noise_reset = iwl4965_chain_noise_reset,
  1928. .gain_computation = iwl4965_gain_computation,
  1929. .rts_tx_cmd_flag = iwl4965_rts_tx_cmd_flag,
  1930. .calc_rssi = iwl4965_calc_rssi,
  1931. };
  1932. static struct iwl_lib_ops iwl4965_lib = {
  1933. .set_hw_params = iwl4965_hw_set_hw_params,
  1934. .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
  1935. .txq_set_sched = iwl4965_txq_set_sched,
  1936. .txq_agg_enable = iwl4965_txq_agg_enable,
  1937. .txq_agg_disable = iwl4965_txq_agg_disable,
  1938. .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
  1939. .txq_free_tfd = iwl_hw_txq_free_tfd,
  1940. .txq_init = iwl_hw_tx_queue_init,
  1941. .rx_handler_setup = iwl4965_rx_handler_setup,
  1942. .setup_deferred_work = iwl4965_setup_deferred_work,
  1943. .cancel_deferred_work = iwl4965_cancel_deferred_work,
  1944. .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
  1945. .alive_notify = iwl4965_alive_notify,
  1946. .init_alive_start = iwl4965_init_alive_start,
  1947. .load_ucode = iwl4965_load_bsm,
  1948. .apm_ops = {
  1949. .init = iwl4965_apm_init,
  1950. .reset = iwl4965_apm_reset,
  1951. .stop = iwl4965_apm_stop,
  1952. .config = iwl4965_nic_config,
  1953. .set_pwr_src = iwl_set_pwr_src,
  1954. },
  1955. .eeprom_ops = {
  1956. .regulatory_bands = {
  1957. EEPROM_REGULATORY_BAND_1_CHANNELS,
  1958. EEPROM_REGULATORY_BAND_2_CHANNELS,
  1959. EEPROM_REGULATORY_BAND_3_CHANNELS,
  1960. EEPROM_REGULATORY_BAND_4_CHANNELS,
  1961. EEPROM_REGULATORY_BAND_5_CHANNELS,
  1962. EEPROM_4965_REGULATORY_BAND_24_FAT_CHANNELS,
  1963. EEPROM_4965_REGULATORY_BAND_52_FAT_CHANNELS
  1964. },
  1965. .verify_signature = iwlcore_eeprom_verify_signature,
  1966. .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
  1967. .release_semaphore = iwlcore_eeprom_release_semaphore,
  1968. .calib_version = iwl4965_eeprom_calib_version,
  1969. .query_addr = iwlcore_eeprom_query_addr,
  1970. },
  1971. .send_tx_power = iwl4965_send_tx_power,
  1972. .update_chain_flags = iwl_update_chain_flags,
  1973. .temperature = iwl4965_temperature_calib,
  1974. };
  1975. static struct iwl_ops iwl4965_ops = {
  1976. .lib = &iwl4965_lib,
  1977. .hcmd = &iwl4965_hcmd,
  1978. .utils = &iwl4965_hcmd_utils,
  1979. };
  1980. struct iwl_cfg iwl4965_agn_cfg = {
  1981. .name = "4965AGN",
  1982. .fw_name_pre = IWL4965_FW_PRE,
  1983. .ucode_api_max = IWL4965_UCODE_API_MAX,
  1984. .ucode_api_min = IWL4965_UCODE_API_MIN,
  1985. .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
  1986. .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
  1987. .eeprom_ver = EEPROM_4965_EEPROM_VERSION,
  1988. .eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION,
  1989. .ops = &iwl4965_ops,
  1990. .mod_params = &iwl4965_mod_params,
  1991. };
  1992. /* Module firmware */
  1993. MODULE_FIRMWARE(IWL4965_MODULE_FIRMWARE(IWL4965_UCODE_API_MAX));
  1994. module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
  1995. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  1996. module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
  1997. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  1998. module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
  1999. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
  2000. module_param_named(debug, iwl4965_mod_params.debug, uint, 0444);
  2001. MODULE_PARM_DESC(debug, "debug output mask");
  2002. module_param_named(
  2003. disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
  2004. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  2005. module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
  2006. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  2007. /* 11n */
  2008. module_param_named(11n_disable, iwl4965_mod_params.disable_11n, int, 0444);
  2009. MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
  2010. module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
  2011. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  2012. module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, 0444);
  2013. MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");