vxge-traffic.c 66 KB

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  1. /******************************************************************************
  2. * This software may be used and distributed according to the terms of
  3. * the GNU General Public License (GPL), incorporated herein by reference.
  4. * Drivers based on or derived from this code fall under the GPL and must
  5. * retain the authorship, copyright and license notice. This file is not
  6. * a complete program and may only be used when the entire operating
  7. * system is licensed under the GPL.
  8. * See the file COPYING in this distribution for more information.
  9. *
  10. * vxge-traffic.c: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O
  11. * Virtualized Server Adapter.
  12. * Copyright(c) 2002-2009 Neterion Inc.
  13. ******************************************************************************/
  14. #include <linux/etherdevice.h>
  15. #include "vxge-traffic.h"
  16. #include "vxge-config.h"
  17. #include "vxge-main.h"
  18. /*
  19. * vxge_hw_vpath_intr_enable - Enable vpath interrupts.
  20. * @vp: Virtual Path handle.
  21. *
  22. * Enable vpath interrupts. The function is to be executed the last in
  23. * vpath initialization sequence.
  24. *
  25. * See also: vxge_hw_vpath_intr_disable()
  26. */
  27. enum vxge_hw_status vxge_hw_vpath_intr_enable(struct __vxge_hw_vpath_handle *vp)
  28. {
  29. u64 val64;
  30. struct __vxge_hw_virtualpath *vpath;
  31. struct vxge_hw_vpath_reg __iomem *vp_reg;
  32. enum vxge_hw_status status = VXGE_HW_OK;
  33. if (vp == NULL) {
  34. status = VXGE_HW_ERR_INVALID_HANDLE;
  35. goto exit;
  36. }
  37. vpath = vp->vpath;
  38. if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
  39. status = VXGE_HW_ERR_VPATH_NOT_OPEN;
  40. goto exit;
  41. }
  42. vp_reg = vpath->vp_reg;
  43. writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_reg);
  44. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  45. &vp_reg->general_errors_reg);
  46. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  47. &vp_reg->pci_config_errors_reg);
  48. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  49. &vp_reg->mrpcim_to_vpath_alarm_reg);
  50. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  51. &vp_reg->srpcim_to_vpath_alarm_reg);
  52. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  53. &vp_reg->vpath_ppif_int_status);
  54. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  55. &vp_reg->srpcim_msg_to_vpath_reg);
  56. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  57. &vp_reg->vpath_pcipif_int_status);
  58. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  59. &vp_reg->prc_alarm_reg);
  60. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  61. &vp_reg->wrdma_alarm_status);
  62. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  63. &vp_reg->asic_ntwk_vp_err_reg);
  64. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  65. &vp_reg->xgmac_vp_int_status);
  66. val64 = readq(&vp_reg->vpath_general_int_status);
  67. /* Mask unwanted interrupts */
  68. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  69. &vp_reg->vpath_pcipif_int_mask);
  70. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  71. &vp_reg->srpcim_msg_to_vpath_mask);
  72. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  73. &vp_reg->srpcim_to_vpath_alarm_mask);
  74. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  75. &vp_reg->mrpcim_to_vpath_alarm_mask);
  76. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  77. &vp_reg->pci_config_errors_mask);
  78. /* Unmask the individual interrupts */
  79. writeq((u32)vxge_bVALn((VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO1_OVRFLOW|
  80. VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO2_OVRFLOW|
  81. VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ|
  82. VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR), 0, 32),
  83. &vp_reg->general_errors_mask);
  84. __vxge_hw_pio_mem_write32_upper(
  85. (u32)vxge_bVALn((VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_OVRWR|
  86. VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_OVRWR|
  87. VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_POISON|
  88. VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO2_POISON|
  89. VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR|
  90. VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO1_DMA_ERR), 0, 32),
  91. &vp_reg->kdfcctl_errors_mask);
  92. __vxge_hw_pio_mem_write32_upper(0, &vp_reg->vpath_ppif_int_mask);
  93. __vxge_hw_pio_mem_write32_upper(
  94. (u32)vxge_bVALn(VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP, 0, 32),
  95. &vp_reg->prc_alarm_mask);
  96. __vxge_hw_pio_mem_write32_upper(0, &vp_reg->wrdma_alarm_mask);
  97. __vxge_hw_pio_mem_write32_upper(0, &vp_reg->xgmac_vp_int_mask);
  98. if (vpath->hldev->first_vp_id != vpath->vp_id)
  99. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  100. &vp_reg->asic_ntwk_vp_err_mask);
  101. else
  102. __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn((
  103. VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_FAULT |
  104. VXGE_HW_ASIC_NTWK_VP_ERR_REG_XMACJ_NTWK_REAFFIRMED_OK), 0, 32),
  105. &vp_reg->asic_ntwk_vp_err_mask);
  106. __vxge_hw_pio_mem_write32_upper(0,
  107. &vp_reg->vpath_general_int_mask);
  108. exit:
  109. return status;
  110. }
  111. /*
  112. * vxge_hw_vpath_intr_disable - Disable vpath interrupts.
  113. * @vp: Virtual Path handle.
  114. *
  115. * Disable vpath interrupts. The function is to be executed the last in
  116. * vpath initialization sequence.
  117. *
  118. * See also: vxge_hw_vpath_intr_enable()
  119. */
  120. enum vxge_hw_status vxge_hw_vpath_intr_disable(
  121. struct __vxge_hw_vpath_handle *vp)
  122. {
  123. u64 val64;
  124. struct __vxge_hw_virtualpath *vpath;
  125. enum vxge_hw_status status = VXGE_HW_OK;
  126. struct vxge_hw_vpath_reg __iomem *vp_reg;
  127. if (vp == NULL) {
  128. status = VXGE_HW_ERR_INVALID_HANDLE;
  129. goto exit;
  130. }
  131. vpath = vp->vpath;
  132. if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
  133. status = VXGE_HW_ERR_VPATH_NOT_OPEN;
  134. goto exit;
  135. }
  136. vp_reg = vpath->vp_reg;
  137. __vxge_hw_pio_mem_write32_upper(
  138. (u32)VXGE_HW_INTR_MASK_ALL,
  139. &vp_reg->vpath_general_int_mask);
  140. val64 = VXGE_HW_TIM_CLR_INT_EN_VP(1 << (16 - vpath->vp_id));
  141. writeq(VXGE_HW_INTR_MASK_ALL, &vp_reg->kdfcctl_errors_mask);
  142. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  143. &vp_reg->general_errors_mask);
  144. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  145. &vp_reg->pci_config_errors_mask);
  146. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  147. &vp_reg->mrpcim_to_vpath_alarm_mask);
  148. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  149. &vp_reg->srpcim_to_vpath_alarm_mask);
  150. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  151. &vp_reg->vpath_ppif_int_mask);
  152. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  153. &vp_reg->srpcim_msg_to_vpath_mask);
  154. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  155. &vp_reg->vpath_pcipif_int_mask);
  156. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  157. &vp_reg->wrdma_alarm_mask);
  158. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  159. &vp_reg->prc_alarm_mask);
  160. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  161. &vp_reg->xgmac_vp_int_mask);
  162. __vxge_hw_pio_mem_write32_upper((u32)VXGE_HW_INTR_MASK_ALL,
  163. &vp_reg->asic_ntwk_vp_err_mask);
  164. exit:
  165. return status;
  166. }
  167. /**
  168. * vxge_hw_channel_msix_mask - Mask MSIX Vector.
  169. * @channeh: Channel for rx or tx handle
  170. * @msix_id: MSIX ID
  171. *
  172. * The function masks the msix interrupt for the given msix_id
  173. *
  174. * Returns: 0
  175. */
  176. void vxge_hw_channel_msix_mask(struct __vxge_hw_channel *channel, int msix_id)
  177. {
  178. __vxge_hw_pio_mem_write32_upper(
  179. (u32)vxge_bVALn(vxge_mBIT(channel->first_vp_id+(msix_id/4)),
  180. 0, 32),
  181. &channel->common_reg->set_msix_mask_vect[msix_id%4]);
  182. return;
  183. }
  184. /**
  185. * vxge_hw_channel_msix_unmask - Unmask the MSIX Vector.
  186. * @channeh: Channel for rx or tx handle
  187. * @msix_id: MSI ID
  188. *
  189. * The function unmasks the msix interrupt for the given msix_id
  190. *
  191. * Returns: 0
  192. */
  193. void
  194. vxge_hw_channel_msix_unmask(struct __vxge_hw_channel *channel, int msix_id)
  195. {
  196. __vxge_hw_pio_mem_write32_upper(
  197. (u32)vxge_bVALn(vxge_mBIT(channel->first_vp_id+(msix_id/4)),
  198. 0, 32),
  199. &channel->common_reg->clear_msix_mask_vect[msix_id%4]);
  200. return;
  201. }
  202. /**
  203. * vxge_hw_device_set_intr_type - Updates the configuration
  204. * with new interrupt type.
  205. * @hldev: HW device handle.
  206. * @intr_mode: New interrupt type
  207. */
  208. u32 vxge_hw_device_set_intr_type(struct __vxge_hw_device *hldev, u32 intr_mode)
  209. {
  210. if ((intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
  211. (intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
  212. (intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
  213. (intr_mode != VXGE_HW_INTR_MODE_DEF))
  214. intr_mode = VXGE_HW_INTR_MODE_IRQLINE;
  215. hldev->config.intr_mode = intr_mode;
  216. return intr_mode;
  217. }
  218. /**
  219. * vxge_hw_device_intr_enable - Enable interrupts.
  220. * @hldev: HW device handle.
  221. * @op: One of the enum vxge_hw_device_intr enumerated values specifying
  222. * the type(s) of interrupts to enable.
  223. *
  224. * Enable Titan interrupts. The function is to be executed the last in
  225. * Titan initialization sequence.
  226. *
  227. * See also: vxge_hw_device_intr_disable()
  228. */
  229. void vxge_hw_device_intr_enable(struct __vxge_hw_device *hldev)
  230. {
  231. u32 i;
  232. u64 val64;
  233. u32 val32;
  234. for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
  235. if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
  236. continue;
  237. vxge_hw_vpath_intr_enable(
  238. VXGE_HW_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
  239. }
  240. if (hldev->config.intr_mode == VXGE_HW_INTR_MODE_IRQLINE) {
  241. val64 = hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
  242. hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX];
  243. if (val64 != 0) {
  244. writeq(val64, &hldev->common_reg->tim_int_status0);
  245. writeq(~val64, &hldev->common_reg->tim_int_mask0);
  246. }
  247. val32 = hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
  248. hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX];
  249. if (val32 != 0) {
  250. __vxge_hw_pio_mem_write32_upper(val32,
  251. &hldev->common_reg->tim_int_status1);
  252. __vxge_hw_pio_mem_write32_upper(~val32,
  253. &hldev->common_reg->tim_int_mask1);
  254. }
  255. }
  256. val64 = readq(&hldev->common_reg->titan_general_int_status);
  257. vxge_hw_device_unmask_all(hldev);
  258. return;
  259. }
  260. /**
  261. * vxge_hw_device_intr_disable - Disable Titan interrupts.
  262. * @hldev: HW device handle.
  263. * @op: One of the enum vxge_hw_device_intr enumerated values specifying
  264. * the type(s) of interrupts to disable.
  265. *
  266. * Disable Titan interrupts.
  267. *
  268. * See also: vxge_hw_device_intr_enable()
  269. */
  270. void vxge_hw_device_intr_disable(struct __vxge_hw_device *hldev)
  271. {
  272. u32 i;
  273. vxge_hw_device_mask_all(hldev);
  274. /* mask all the tim interrupts */
  275. writeq(VXGE_HW_INTR_MASK_ALL, &hldev->common_reg->tim_int_mask0);
  276. __vxge_hw_pio_mem_write32_upper(VXGE_HW_DEFAULT_32,
  277. &hldev->common_reg->tim_int_mask1);
  278. for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
  279. if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
  280. continue;
  281. vxge_hw_vpath_intr_disable(
  282. VXGE_HW_VIRTUAL_PATH_HANDLE(&hldev->virtual_paths[i]));
  283. }
  284. return;
  285. }
  286. /**
  287. * vxge_hw_device_mask_all - Mask all device interrupts.
  288. * @hldev: HW device handle.
  289. *
  290. * Mask all device interrupts.
  291. *
  292. * See also: vxge_hw_device_unmask_all()
  293. */
  294. void vxge_hw_device_mask_all(struct __vxge_hw_device *hldev)
  295. {
  296. u64 val64;
  297. val64 = VXGE_HW_TITAN_MASK_ALL_INT_ALARM |
  298. VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC;
  299. __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
  300. &hldev->common_reg->titan_mask_all_int);
  301. return;
  302. }
  303. /**
  304. * vxge_hw_device_unmask_all - Unmask all device interrupts.
  305. * @hldev: HW device handle.
  306. *
  307. * Unmask all device interrupts.
  308. *
  309. * See also: vxge_hw_device_mask_all()
  310. */
  311. void vxge_hw_device_unmask_all(struct __vxge_hw_device *hldev)
  312. {
  313. u64 val64 = 0;
  314. if (hldev->config.intr_mode == VXGE_HW_INTR_MODE_IRQLINE)
  315. val64 = VXGE_HW_TITAN_MASK_ALL_INT_TRAFFIC;
  316. __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
  317. &hldev->common_reg->titan_mask_all_int);
  318. return;
  319. }
  320. /**
  321. * vxge_hw_device_flush_io - Flush io writes.
  322. * @hldev: HW device handle.
  323. *
  324. * The function performs a read operation to flush io writes.
  325. *
  326. * Returns: void
  327. */
  328. void vxge_hw_device_flush_io(struct __vxge_hw_device *hldev)
  329. {
  330. u32 val32;
  331. val32 = readl(&hldev->common_reg->titan_general_int_status);
  332. }
  333. /**
  334. * vxge_hw_device_begin_irq - Begin IRQ processing.
  335. * @hldev: HW device handle.
  336. * @skip_alarms: Do not clear the alarms
  337. * @reason: "Reason" for the interrupt, the value of Titan's
  338. * general_int_status register.
  339. *
  340. * The function performs two actions, It first checks whether (shared IRQ) the
  341. * interrupt was raised by the device. Next, it masks the device interrupts.
  342. *
  343. * Note:
  344. * vxge_hw_device_begin_irq() does not flush MMIO writes through the
  345. * bridge. Therefore, two back-to-back interrupts are potentially possible.
  346. *
  347. * Returns: 0, if the interrupt is not "ours" (note that in this case the
  348. * device remain enabled).
  349. * Otherwise, vxge_hw_device_begin_irq() returns 64bit general adapter
  350. * status.
  351. */
  352. enum vxge_hw_status vxge_hw_device_begin_irq(struct __vxge_hw_device *hldev,
  353. u32 skip_alarms, u64 *reason)
  354. {
  355. u32 i;
  356. u64 val64;
  357. u64 adapter_status;
  358. u64 vpath_mask;
  359. enum vxge_hw_status ret = VXGE_HW_OK;
  360. val64 = readq(&hldev->common_reg->titan_general_int_status);
  361. if (unlikely(!val64)) {
  362. /* not Titan interrupt */
  363. *reason = 0;
  364. ret = VXGE_HW_ERR_WRONG_IRQ;
  365. goto exit;
  366. }
  367. if (unlikely(val64 == VXGE_HW_ALL_FOXES)) {
  368. adapter_status = readq(&hldev->common_reg->adapter_status);
  369. if (adapter_status == VXGE_HW_ALL_FOXES) {
  370. __vxge_hw_device_handle_error(hldev,
  371. NULL_VPID, VXGE_HW_EVENT_SLOT_FREEZE);
  372. *reason = 0;
  373. ret = VXGE_HW_ERR_SLOT_FREEZE;
  374. goto exit;
  375. }
  376. }
  377. hldev->stats.sw_dev_info_stats.total_intr_cnt++;
  378. *reason = val64;
  379. vpath_mask = hldev->vpaths_deployed >>
  380. (64 - VXGE_HW_MAX_VIRTUAL_PATHS);
  381. if (val64 &
  382. VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_TRAFFIC_INT(vpath_mask)) {
  383. hldev->stats.sw_dev_info_stats.traffic_intr_cnt++;
  384. return VXGE_HW_OK;
  385. }
  386. hldev->stats.sw_dev_info_stats.not_traffic_intr_cnt++;
  387. if (unlikely(val64 &
  388. VXGE_HW_TITAN_GENERAL_INT_STATUS_VPATH_ALARM_INT)) {
  389. enum vxge_hw_status error_level = VXGE_HW_OK;
  390. hldev->stats.sw_dev_err_stats.vpath_alarms++;
  391. for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
  392. if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
  393. continue;
  394. ret = __vxge_hw_vpath_alarm_process(
  395. &hldev->virtual_paths[i], skip_alarms);
  396. error_level = VXGE_HW_SET_LEVEL(ret, error_level);
  397. if (unlikely((ret == VXGE_HW_ERR_CRITICAL) ||
  398. (ret == VXGE_HW_ERR_SLOT_FREEZE)))
  399. break;
  400. }
  401. ret = error_level;
  402. }
  403. exit:
  404. return ret;
  405. }
  406. /*
  407. * __vxge_hw_device_handle_link_up_ind
  408. * @hldev: HW device handle.
  409. *
  410. * Link up indication handler. The function is invoked by HW when
  411. * Titan indicates that the link is up for programmable amount of time.
  412. */
  413. enum vxge_hw_status
  414. __vxge_hw_device_handle_link_up_ind(struct __vxge_hw_device *hldev)
  415. {
  416. /*
  417. * If the previous link state is not down, return.
  418. */
  419. if (hldev->link_state == VXGE_HW_LINK_UP)
  420. goto exit;
  421. hldev->link_state = VXGE_HW_LINK_UP;
  422. /* notify driver */
  423. if (hldev->uld_callbacks.link_up)
  424. hldev->uld_callbacks.link_up(hldev);
  425. exit:
  426. return VXGE_HW_OK;
  427. }
  428. /*
  429. * __vxge_hw_device_handle_link_down_ind
  430. * @hldev: HW device handle.
  431. *
  432. * Link down indication handler. The function is invoked by HW when
  433. * Titan indicates that the link is down.
  434. */
  435. enum vxge_hw_status
  436. __vxge_hw_device_handle_link_down_ind(struct __vxge_hw_device *hldev)
  437. {
  438. /*
  439. * If the previous link state is not down, return.
  440. */
  441. if (hldev->link_state == VXGE_HW_LINK_DOWN)
  442. goto exit;
  443. hldev->link_state = VXGE_HW_LINK_DOWN;
  444. /* notify driver */
  445. if (hldev->uld_callbacks.link_down)
  446. hldev->uld_callbacks.link_down(hldev);
  447. exit:
  448. return VXGE_HW_OK;
  449. }
  450. /**
  451. * __vxge_hw_device_handle_error - Handle error
  452. * @hldev: HW device
  453. * @vp_id: Vpath Id
  454. * @type: Error type. Please see enum vxge_hw_event{}
  455. *
  456. * Handle error.
  457. */
  458. enum vxge_hw_status
  459. __vxge_hw_device_handle_error(
  460. struct __vxge_hw_device *hldev,
  461. u32 vp_id,
  462. enum vxge_hw_event type)
  463. {
  464. switch (type) {
  465. case VXGE_HW_EVENT_UNKNOWN:
  466. break;
  467. case VXGE_HW_EVENT_RESET_START:
  468. case VXGE_HW_EVENT_RESET_COMPLETE:
  469. case VXGE_HW_EVENT_LINK_DOWN:
  470. case VXGE_HW_EVENT_LINK_UP:
  471. goto out;
  472. case VXGE_HW_EVENT_ALARM_CLEARED:
  473. goto out;
  474. case VXGE_HW_EVENT_ECCERR:
  475. case VXGE_HW_EVENT_MRPCIM_ECCERR:
  476. goto out;
  477. case VXGE_HW_EVENT_FIFO_ERR:
  478. case VXGE_HW_EVENT_VPATH_ERR:
  479. case VXGE_HW_EVENT_CRITICAL_ERR:
  480. case VXGE_HW_EVENT_SERR:
  481. break;
  482. case VXGE_HW_EVENT_SRPCIM_SERR:
  483. case VXGE_HW_EVENT_MRPCIM_SERR:
  484. goto out;
  485. case VXGE_HW_EVENT_SLOT_FREEZE:
  486. break;
  487. default:
  488. vxge_assert(0);
  489. goto out;
  490. }
  491. /* notify driver */
  492. if (hldev->uld_callbacks.crit_err)
  493. hldev->uld_callbacks.crit_err(
  494. (struct __vxge_hw_device *)hldev,
  495. type, vp_id);
  496. out:
  497. return VXGE_HW_OK;
  498. }
  499. /**
  500. * vxge_hw_device_clear_tx_rx - Acknowledge (that is, clear) the
  501. * condition that has caused the Tx and RX interrupt.
  502. * @hldev: HW device.
  503. *
  504. * Acknowledge (that is, clear) the condition that has caused
  505. * the Tx and Rx interrupt.
  506. * See also: vxge_hw_device_begin_irq(),
  507. * vxge_hw_device_mask_tx_rx(), vxge_hw_device_unmask_tx_rx().
  508. */
  509. void vxge_hw_device_clear_tx_rx(struct __vxge_hw_device *hldev)
  510. {
  511. if ((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
  512. (hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
  513. writeq((hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
  514. hldev->tim_int_mask0[VXGE_HW_VPATH_INTR_RX]),
  515. &hldev->common_reg->tim_int_status0);
  516. }
  517. if ((hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) ||
  518. (hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) {
  519. __vxge_hw_pio_mem_write32_upper(
  520. (hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
  521. hldev->tim_int_mask1[VXGE_HW_VPATH_INTR_RX]),
  522. &hldev->common_reg->tim_int_status1);
  523. }
  524. return;
  525. }
  526. /*
  527. * vxge_hw_channel_dtr_alloc - Allocate a dtr from the channel
  528. * @channel: Channel
  529. * @dtrh: Buffer to return the DTR pointer
  530. *
  531. * Allocates a dtr from the reserve array. If the reserve array is empty,
  532. * it swaps the reserve and free arrays.
  533. *
  534. */
  535. enum vxge_hw_status
  536. vxge_hw_channel_dtr_alloc(struct __vxge_hw_channel *channel, void **dtrh)
  537. {
  538. void **tmp_arr;
  539. if (channel->reserve_ptr - channel->reserve_top > 0) {
  540. _alloc_after_swap:
  541. *dtrh = channel->reserve_arr[--channel->reserve_ptr];
  542. return VXGE_HW_OK;
  543. }
  544. /* switch between empty and full arrays */
  545. /* the idea behind such a design is that by having free and reserved
  546. * arrays separated we basically separated irq and non-irq parts.
  547. * i.e. no additional lock need to be done when we free a resource */
  548. if (channel->length - channel->free_ptr > 0) {
  549. tmp_arr = channel->reserve_arr;
  550. channel->reserve_arr = channel->free_arr;
  551. channel->free_arr = tmp_arr;
  552. channel->reserve_ptr = channel->length;
  553. channel->reserve_top = channel->free_ptr;
  554. channel->free_ptr = channel->length;
  555. channel->stats->reserve_free_swaps_cnt++;
  556. goto _alloc_after_swap;
  557. }
  558. channel->stats->full_cnt++;
  559. *dtrh = NULL;
  560. return VXGE_HW_INF_OUT_OF_DESCRIPTORS;
  561. }
  562. /*
  563. * vxge_hw_channel_dtr_post - Post a dtr to the channel
  564. * @channelh: Channel
  565. * @dtrh: DTR pointer
  566. *
  567. * Posts a dtr to work array.
  568. *
  569. */
  570. void vxge_hw_channel_dtr_post(struct __vxge_hw_channel *channel, void *dtrh)
  571. {
  572. vxge_assert(channel->work_arr[channel->post_index] == NULL);
  573. channel->work_arr[channel->post_index++] = dtrh;
  574. /* wrap-around */
  575. if (channel->post_index == channel->length)
  576. channel->post_index = 0;
  577. }
  578. /*
  579. * vxge_hw_channel_dtr_try_complete - Returns next completed dtr
  580. * @channel: Channel
  581. * @dtr: Buffer to return the next completed DTR pointer
  582. *
  583. * Returns the next completed dtr with out removing it from work array
  584. *
  585. */
  586. void
  587. vxge_hw_channel_dtr_try_complete(struct __vxge_hw_channel *channel, void **dtrh)
  588. {
  589. vxge_assert(channel->compl_index < channel->length);
  590. *dtrh = channel->work_arr[channel->compl_index];
  591. }
  592. /*
  593. * vxge_hw_channel_dtr_complete - Removes next completed dtr from the work array
  594. * @channel: Channel handle
  595. *
  596. * Removes the next completed dtr from work array
  597. *
  598. */
  599. void vxge_hw_channel_dtr_complete(struct __vxge_hw_channel *channel)
  600. {
  601. channel->work_arr[channel->compl_index] = NULL;
  602. /* wrap-around */
  603. if (++channel->compl_index == channel->length)
  604. channel->compl_index = 0;
  605. channel->stats->total_compl_cnt++;
  606. }
  607. /*
  608. * vxge_hw_channel_dtr_free - Frees a dtr
  609. * @channel: Channel handle
  610. * @dtr: DTR pointer
  611. *
  612. * Returns the dtr to free array
  613. *
  614. */
  615. void vxge_hw_channel_dtr_free(struct __vxge_hw_channel *channel, void *dtrh)
  616. {
  617. channel->free_arr[--channel->free_ptr] = dtrh;
  618. }
  619. /*
  620. * vxge_hw_channel_dtr_count
  621. * @channel: Channel handle. Obtained via vxge_hw_channel_open().
  622. *
  623. * Retreive number of DTRs available. This function can not be called
  624. * from data path. ring_initial_replenishi() is the only user.
  625. */
  626. int vxge_hw_channel_dtr_count(struct __vxge_hw_channel *channel)
  627. {
  628. return (channel->reserve_ptr - channel->reserve_top) +
  629. (channel->length - channel->free_ptr);
  630. }
  631. /**
  632. * vxge_hw_ring_rxd_reserve - Reserve ring descriptor.
  633. * @ring: Handle to the ring object used for receive
  634. * @rxdh: Reserved descriptor. On success HW fills this "out" parameter
  635. * with a valid handle.
  636. *
  637. * Reserve Rx descriptor for the subsequent filling-in driver
  638. * and posting on the corresponding channel (@channelh)
  639. * via vxge_hw_ring_rxd_post().
  640. *
  641. * Returns: VXGE_HW_OK - success.
  642. * VXGE_HW_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available.
  643. *
  644. */
  645. enum vxge_hw_status vxge_hw_ring_rxd_reserve(struct __vxge_hw_ring *ring,
  646. void **rxdh)
  647. {
  648. enum vxge_hw_status status;
  649. struct __vxge_hw_channel *channel;
  650. channel = &ring->channel;
  651. status = vxge_hw_channel_dtr_alloc(channel, rxdh);
  652. if (status == VXGE_HW_OK) {
  653. struct vxge_hw_ring_rxd_1 *rxdp =
  654. (struct vxge_hw_ring_rxd_1 *)*rxdh;
  655. rxdp->control_0 = rxdp->control_1 = 0;
  656. }
  657. return status;
  658. }
  659. /**
  660. * vxge_hw_ring_rxd_free - Free descriptor.
  661. * @ring: Handle to the ring object used for receive
  662. * @rxdh: Descriptor handle.
  663. *
  664. * Free the reserved descriptor. This operation is "symmetrical" to
  665. * vxge_hw_ring_rxd_reserve. The "free-ing" completes the descriptor's
  666. * lifecycle.
  667. *
  668. * After free-ing (see vxge_hw_ring_rxd_free()) the descriptor again can
  669. * be:
  670. *
  671. * - reserved (vxge_hw_ring_rxd_reserve);
  672. *
  673. * - posted (vxge_hw_ring_rxd_post);
  674. *
  675. * - completed (vxge_hw_ring_rxd_next_completed);
  676. *
  677. * - and recycled again (vxge_hw_ring_rxd_free).
  678. *
  679. * For alternative state transitions and more details please refer to
  680. * the design doc.
  681. *
  682. */
  683. void vxge_hw_ring_rxd_free(struct __vxge_hw_ring *ring, void *rxdh)
  684. {
  685. struct __vxge_hw_channel *channel;
  686. channel = &ring->channel;
  687. vxge_hw_channel_dtr_free(channel, rxdh);
  688. }
  689. /**
  690. * vxge_hw_ring_rxd_pre_post - Prepare rxd and post
  691. * @ring: Handle to the ring object used for receive
  692. * @rxdh: Descriptor handle.
  693. *
  694. * This routine prepares a rxd and posts
  695. */
  696. void vxge_hw_ring_rxd_pre_post(struct __vxge_hw_ring *ring, void *rxdh)
  697. {
  698. struct __vxge_hw_channel *channel;
  699. channel = &ring->channel;
  700. vxge_hw_channel_dtr_post(channel, rxdh);
  701. }
  702. /**
  703. * vxge_hw_ring_rxd_post_post - Process rxd after post.
  704. * @ring: Handle to the ring object used for receive
  705. * @rxdh: Descriptor handle.
  706. *
  707. * Processes rxd after post
  708. */
  709. void vxge_hw_ring_rxd_post_post(struct __vxge_hw_ring *ring, void *rxdh)
  710. {
  711. struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh;
  712. struct __vxge_hw_channel *channel;
  713. channel = &ring->channel;
  714. rxdp->control_0 |= VXGE_HW_RING_RXD_LIST_OWN_ADAPTER;
  715. if (ring->stats->common_stats.usage_cnt > 0)
  716. ring->stats->common_stats.usage_cnt--;
  717. }
  718. /**
  719. * vxge_hw_ring_rxd_post - Post descriptor on the ring.
  720. * @ring: Handle to the ring object used for receive
  721. * @rxdh: Descriptor obtained via vxge_hw_ring_rxd_reserve().
  722. *
  723. * Post descriptor on the ring.
  724. * Prior to posting the descriptor should be filled in accordance with
  725. * Host/Titan interface specification for a given service (LL, etc.).
  726. *
  727. */
  728. void vxge_hw_ring_rxd_post(struct __vxge_hw_ring *ring, void *rxdh)
  729. {
  730. struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh;
  731. struct __vxge_hw_channel *channel;
  732. channel = &ring->channel;
  733. wmb();
  734. rxdp->control_0 |= VXGE_HW_RING_RXD_LIST_OWN_ADAPTER;
  735. vxge_hw_channel_dtr_post(channel, rxdh);
  736. if (ring->stats->common_stats.usage_cnt > 0)
  737. ring->stats->common_stats.usage_cnt--;
  738. }
  739. /**
  740. * vxge_hw_ring_rxd_post_post_wmb - Process rxd after post with memory barrier.
  741. * @ring: Handle to the ring object used for receive
  742. * @rxdh: Descriptor handle.
  743. *
  744. * Processes rxd after post with memory barrier.
  745. */
  746. void vxge_hw_ring_rxd_post_post_wmb(struct __vxge_hw_ring *ring, void *rxdh)
  747. {
  748. struct __vxge_hw_channel *channel;
  749. channel = &ring->channel;
  750. wmb();
  751. vxge_hw_ring_rxd_post_post(ring, rxdh);
  752. }
  753. /**
  754. * vxge_hw_ring_rxd_next_completed - Get the _next_ completed descriptor.
  755. * @ring: Handle to the ring object used for receive
  756. * @rxdh: Descriptor handle. Returned by HW.
  757. * @t_code: Transfer code, as per Titan User Guide,
  758. * Receive Descriptor Format. Returned by HW.
  759. *
  760. * Retrieve the _next_ completed descriptor.
  761. * HW uses ring callback (*vxge_hw_ring_callback_f) to notifiy
  762. * driver of new completed descriptors. After that
  763. * the driver can use vxge_hw_ring_rxd_next_completed to retrieve the rest
  764. * completions (the very first completion is passed by HW via
  765. * vxge_hw_ring_callback_f).
  766. *
  767. * Implementation-wise, the driver is free to call
  768. * vxge_hw_ring_rxd_next_completed either immediately from inside the
  769. * ring callback, or in a deferred fashion and separate (from HW)
  770. * context.
  771. *
  772. * Non-zero @t_code means failure to fill-in receive buffer(s)
  773. * of the descriptor.
  774. * For instance, parity error detected during the data transfer.
  775. * In this case Titan will complete the descriptor and indicate
  776. * for the host that the received data is not to be used.
  777. * For details please refer to Titan User Guide.
  778. *
  779. * Returns: VXGE_HW_OK - success.
  780. * VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors
  781. * are currently available for processing.
  782. *
  783. * See also: vxge_hw_ring_callback_f{},
  784. * vxge_hw_fifo_rxd_next_completed(), enum vxge_hw_status{}.
  785. */
  786. enum vxge_hw_status vxge_hw_ring_rxd_next_completed(
  787. struct __vxge_hw_ring *ring, void **rxdh, u8 *t_code)
  788. {
  789. struct __vxge_hw_channel *channel;
  790. struct vxge_hw_ring_rxd_1 *rxdp;
  791. enum vxge_hw_status status = VXGE_HW_OK;
  792. channel = &ring->channel;
  793. vxge_hw_channel_dtr_try_complete(channel, rxdh);
  794. rxdp = (struct vxge_hw_ring_rxd_1 *)*rxdh;
  795. if (rxdp == NULL) {
  796. status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
  797. goto exit;
  798. }
  799. /* check whether it is not the end */
  800. if (!(rxdp->control_0 & VXGE_HW_RING_RXD_LIST_OWN_ADAPTER)) {
  801. vxge_assert(((struct vxge_hw_ring_rxd_1 *)rxdp)->host_control !=
  802. 0);
  803. ++ring->cmpl_cnt;
  804. vxge_hw_channel_dtr_complete(channel);
  805. *t_code = (u8)VXGE_HW_RING_RXD_T_CODE_GET(rxdp->control_0);
  806. vxge_assert(*t_code != VXGE_HW_RING_RXD_T_CODE_UNUSED);
  807. ring->stats->common_stats.usage_cnt++;
  808. if (ring->stats->common_stats.usage_max <
  809. ring->stats->common_stats.usage_cnt)
  810. ring->stats->common_stats.usage_max =
  811. ring->stats->common_stats.usage_cnt;
  812. status = VXGE_HW_OK;
  813. goto exit;
  814. }
  815. /* reset it. since we don't want to return
  816. * garbage to the driver */
  817. *rxdh = NULL;
  818. status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
  819. exit:
  820. return status;
  821. }
  822. /**
  823. * vxge_hw_ring_handle_tcode - Handle transfer code.
  824. * @ring: Handle to the ring object used for receive
  825. * @rxdh: Descriptor handle.
  826. * @t_code: One of the enumerated (and documented in the Titan user guide)
  827. * "transfer codes".
  828. *
  829. * Handle descriptor's transfer code. The latter comes with each completed
  830. * descriptor.
  831. *
  832. * Returns: one of the enum vxge_hw_status{} enumerated types.
  833. * VXGE_HW_OK - for success.
  834. * VXGE_HW_ERR_CRITICAL - when encounters critical error.
  835. */
  836. enum vxge_hw_status vxge_hw_ring_handle_tcode(
  837. struct __vxge_hw_ring *ring, void *rxdh, u8 t_code)
  838. {
  839. struct __vxge_hw_channel *channel;
  840. enum vxge_hw_status status = VXGE_HW_OK;
  841. channel = &ring->channel;
  842. /* If the t_code is not supported and if the
  843. * t_code is other than 0x5 (unparseable packet
  844. * such as unknown UPV6 header), Drop it !!!
  845. */
  846. if (t_code == 0 || t_code == 5) {
  847. status = VXGE_HW_OK;
  848. goto exit;
  849. }
  850. if (t_code > 0xF) {
  851. status = VXGE_HW_ERR_INVALID_TCODE;
  852. goto exit;
  853. }
  854. ring->stats->rxd_t_code_err_cnt[t_code]++;
  855. exit:
  856. return status;
  857. }
  858. /**
  859. * __vxge_hw_non_offload_db_post - Post non offload doorbell
  860. *
  861. * @fifo: fifohandle
  862. * @txdl_ptr: The starting location of the TxDL in host memory
  863. * @num_txds: The highest TxD in this TxDL (0 to 255 means 1 to 256)
  864. * @no_snoop: No snoop flags
  865. *
  866. * This function posts a non-offload doorbell to doorbell FIFO
  867. *
  868. */
  869. static void __vxge_hw_non_offload_db_post(struct __vxge_hw_fifo *fifo,
  870. u64 txdl_ptr, u32 num_txds, u32 no_snoop)
  871. {
  872. struct __vxge_hw_channel *channel;
  873. channel = &fifo->channel;
  874. writeq(VXGE_HW_NODBW_TYPE(VXGE_HW_NODBW_TYPE_NODBW) |
  875. VXGE_HW_NODBW_LAST_TXD_NUMBER(num_txds) |
  876. VXGE_HW_NODBW_GET_NO_SNOOP(no_snoop),
  877. &fifo->nofl_db->control_0);
  878. wmb();
  879. writeq(txdl_ptr, &fifo->nofl_db->txdl_ptr);
  880. wmb();
  881. }
  882. /**
  883. * vxge_hw_fifo_free_txdl_count_get - returns the number of txdls available in
  884. * the fifo
  885. * @fifoh: Handle to the fifo object used for non offload send
  886. */
  887. u32 vxge_hw_fifo_free_txdl_count_get(struct __vxge_hw_fifo *fifoh)
  888. {
  889. return vxge_hw_channel_dtr_count(&fifoh->channel);
  890. }
  891. /**
  892. * vxge_hw_fifo_txdl_reserve - Reserve fifo descriptor.
  893. * @fifoh: Handle to the fifo object used for non offload send
  894. * @txdlh: Reserved descriptor. On success HW fills this "out" parameter
  895. * with a valid handle.
  896. * @txdl_priv: Buffer to return the pointer to per txdl space
  897. *
  898. * Reserve a single TxDL (that is, fifo descriptor)
  899. * for the subsequent filling-in by driver)
  900. * and posting on the corresponding channel (@channelh)
  901. * via vxge_hw_fifo_txdl_post().
  902. *
  903. * Note: it is the responsibility of driver to reserve multiple descriptors
  904. * for lengthy (e.g., LSO) transmit operation. A single fifo descriptor
  905. * carries up to configured number (fifo.max_frags) of contiguous buffers.
  906. *
  907. * Returns: VXGE_HW_OK - success;
  908. * VXGE_HW_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available
  909. *
  910. */
  911. enum vxge_hw_status vxge_hw_fifo_txdl_reserve(
  912. struct __vxge_hw_fifo *fifo,
  913. void **txdlh, void **txdl_priv)
  914. {
  915. struct __vxge_hw_channel *channel;
  916. enum vxge_hw_status status;
  917. int i;
  918. channel = &fifo->channel;
  919. status = vxge_hw_channel_dtr_alloc(channel, txdlh);
  920. if (status == VXGE_HW_OK) {
  921. struct vxge_hw_fifo_txd *txdp =
  922. (struct vxge_hw_fifo_txd *)*txdlh;
  923. struct __vxge_hw_fifo_txdl_priv *priv;
  924. priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
  925. /* reset the TxDL's private */
  926. priv->align_dma_offset = 0;
  927. priv->align_vaddr_start = priv->align_vaddr;
  928. priv->align_used_frags = 0;
  929. priv->frags = 0;
  930. priv->alloc_frags = fifo->config->max_frags;
  931. priv->next_txdl_priv = NULL;
  932. *txdl_priv = (void *)(size_t)txdp->host_control;
  933. for (i = 0; i < fifo->config->max_frags; i++) {
  934. txdp = ((struct vxge_hw_fifo_txd *)*txdlh) + i;
  935. txdp->control_0 = txdp->control_1 = 0;
  936. }
  937. }
  938. return status;
  939. }
  940. /**
  941. * vxge_hw_fifo_txdl_buffer_set - Set transmit buffer pointer in the
  942. * descriptor.
  943. * @fifo: Handle to the fifo object used for non offload send
  944. * @txdlh: Descriptor handle.
  945. * @frag_idx: Index of the data buffer in the caller's scatter-gather list
  946. * (of buffers).
  947. * @dma_pointer: DMA address of the data buffer referenced by @frag_idx.
  948. * @size: Size of the data buffer (in bytes).
  949. *
  950. * This API is part of the preparation of the transmit descriptor for posting
  951. * (via vxge_hw_fifo_txdl_post()). The related "preparation" APIs include
  952. * vxge_hw_fifo_txdl_mss_set() and vxge_hw_fifo_txdl_cksum_set_bits().
  953. * All three APIs fill in the fields of the fifo descriptor,
  954. * in accordance with the Titan specification.
  955. *
  956. */
  957. void vxge_hw_fifo_txdl_buffer_set(struct __vxge_hw_fifo *fifo,
  958. void *txdlh, u32 frag_idx,
  959. dma_addr_t dma_pointer, u32 size)
  960. {
  961. struct __vxge_hw_fifo_txdl_priv *txdl_priv;
  962. struct vxge_hw_fifo_txd *txdp, *txdp_last;
  963. struct __vxge_hw_channel *channel;
  964. channel = &fifo->channel;
  965. txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdlh);
  966. txdp = (struct vxge_hw_fifo_txd *)txdlh + txdl_priv->frags;
  967. if (frag_idx != 0)
  968. txdp->control_0 = txdp->control_1 = 0;
  969. else {
  970. txdp->control_0 |= VXGE_HW_FIFO_TXD_GATHER_CODE(
  971. VXGE_HW_FIFO_TXD_GATHER_CODE_FIRST);
  972. txdp->control_1 |= fifo->interrupt_type;
  973. txdp->control_1 |= VXGE_HW_FIFO_TXD_INT_NUMBER(
  974. fifo->tx_intr_num);
  975. if (txdl_priv->frags) {
  976. txdp_last = (struct vxge_hw_fifo_txd *)txdlh +
  977. (txdl_priv->frags - 1);
  978. txdp_last->control_0 |= VXGE_HW_FIFO_TXD_GATHER_CODE(
  979. VXGE_HW_FIFO_TXD_GATHER_CODE_LAST);
  980. }
  981. }
  982. vxge_assert(frag_idx < txdl_priv->alloc_frags);
  983. txdp->buffer_pointer = (u64)dma_pointer;
  984. txdp->control_0 |= VXGE_HW_FIFO_TXD_BUFFER_SIZE(size);
  985. fifo->stats->total_buffers++;
  986. txdl_priv->frags++;
  987. }
  988. /**
  989. * vxge_hw_fifo_txdl_post - Post descriptor on the fifo channel.
  990. * @fifo: Handle to the fifo object used for non offload send
  991. * @txdlh: Descriptor obtained via vxge_hw_fifo_txdl_reserve()
  992. * @frags: Number of contiguous buffers that are part of a single
  993. * transmit operation.
  994. *
  995. * Post descriptor on the 'fifo' type channel for transmission.
  996. * Prior to posting the descriptor should be filled in accordance with
  997. * Host/Titan interface specification for a given service (LL, etc.).
  998. *
  999. */
  1000. void vxge_hw_fifo_txdl_post(struct __vxge_hw_fifo *fifo, void *txdlh)
  1001. {
  1002. struct __vxge_hw_fifo_txdl_priv *txdl_priv;
  1003. struct vxge_hw_fifo_txd *txdp_last;
  1004. struct vxge_hw_fifo_txd *txdp_first;
  1005. struct __vxge_hw_channel *channel;
  1006. channel = &fifo->channel;
  1007. txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdlh);
  1008. txdp_first = (struct vxge_hw_fifo_txd *)txdlh;
  1009. txdp_last = (struct vxge_hw_fifo_txd *)txdlh + (txdl_priv->frags - 1);
  1010. txdp_last->control_0 |=
  1011. VXGE_HW_FIFO_TXD_GATHER_CODE(VXGE_HW_FIFO_TXD_GATHER_CODE_LAST);
  1012. txdp_first->control_0 |= VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER;
  1013. vxge_hw_channel_dtr_post(&fifo->channel, txdlh);
  1014. __vxge_hw_non_offload_db_post(fifo,
  1015. (u64)(size_t)txdl_priv->dma_addr,
  1016. txdl_priv->frags - 1,
  1017. fifo->no_snoop_bits);
  1018. fifo->stats->total_posts++;
  1019. fifo->stats->common_stats.usage_cnt++;
  1020. if (fifo->stats->common_stats.usage_max <
  1021. fifo->stats->common_stats.usage_cnt)
  1022. fifo->stats->common_stats.usage_max =
  1023. fifo->stats->common_stats.usage_cnt;
  1024. }
  1025. /**
  1026. * vxge_hw_fifo_txdl_next_completed - Retrieve next completed descriptor.
  1027. * @fifo: Handle to the fifo object used for non offload send
  1028. * @txdlh: Descriptor handle. Returned by HW.
  1029. * @t_code: Transfer code, as per Titan User Guide,
  1030. * Transmit Descriptor Format.
  1031. * Returned by HW.
  1032. *
  1033. * Retrieve the _next_ completed descriptor.
  1034. * HW uses channel callback (*vxge_hw_channel_callback_f) to notifiy
  1035. * driver of new completed descriptors. After that
  1036. * the driver can use vxge_hw_fifo_txdl_next_completed to retrieve the rest
  1037. * completions (the very first completion is passed by HW via
  1038. * vxge_hw_channel_callback_f).
  1039. *
  1040. * Implementation-wise, the driver is free to call
  1041. * vxge_hw_fifo_txdl_next_completed either immediately from inside the
  1042. * channel callback, or in a deferred fashion and separate (from HW)
  1043. * context.
  1044. *
  1045. * Non-zero @t_code means failure to process the descriptor.
  1046. * The failure could happen, for instance, when the link is
  1047. * down, in which case Titan completes the descriptor because it
  1048. * is not able to send the data out.
  1049. *
  1050. * For details please refer to Titan User Guide.
  1051. *
  1052. * Returns: VXGE_HW_OK - success.
  1053. * VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors
  1054. * are currently available for processing.
  1055. *
  1056. */
  1057. enum vxge_hw_status vxge_hw_fifo_txdl_next_completed(
  1058. struct __vxge_hw_fifo *fifo, void **txdlh,
  1059. enum vxge_hw_fifo_tcode *t_code)
  1060. {
  1061. struct __vxge_hw_channel *channel;
  1062. struct vxge_hw_fifo_txd *txdp;
  1063. enum vxge_hw_status status = VXGE_HW_OK;
  1064. channel = &fifo->channel;
  1065. vxge_hw_channel_dtr_try_complete(channel, txdlh);
  1066. txdp = (struct vxge_hw_fifo_txd *)*txdlh;
  1067. if (txdp == NULL) {
  1068. status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
  1069. goto exit;
  1070. }
  1071. /* check whether host owns it */
  1072. if (!(txdp->control_0 & VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER)) {
  1073. vxge_assert(txdp->host_control != 0);
  1074. vxge_hw_channel_dtr_complete(channel);
  1075. *t_code = (u8)VXGE_HW_FIFO_TXD_T_CODE_GET(txdp->control_0);
  1076. if (fifo->stats->common_stats.usage_cnt > 0)
  1077. fifo->stats->common_stats.usage_cnt--;
  1078. status = VXGE_HW_OK;
  1079. goto exit;
  1080. }
  1081. /* no more completions */
  1082. *txdlh = NULL;
  1083. status = VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS;
  1084. exit:
  1085. return status;
  1086. }
  1087. /**
  1088. * vxge_hw_fifo_handle_tcode - Handle transfer code.
  1089. * @fifo: Handle to the fifo object used for non offload send
  1090. * @txdlh: Descriptor handle.
  1091. * @t_code: One of the enumerated (and documented in the Titan user guide)
  1092. * "transfer codes".
  1093. *
  1094. * Handle descriptor's transfer code. The latter comes with each completed
  1095. * descriptor.
  1096. *
  1097. * Returns: one of the enum vxge_hw_status{} enumerated types.
  1098. * VXGE_HW_OK - for success.
  1099. * VXGE_HW_ERR_CRITICAL - when encounters critical error.
  1100. */
  1101. enum vxge_hw_status vxge_hw_fifo_handle_tcode(struct __vxge_hw_fifo *fifo,
  1102. void *txdlh,
  1103. enum vxge_hw_fifo_tcode t_code)
  1104. {
  1105. struct __vxge_hw_channel *channel;
  1106. enum vxge_hw_status status = VXGE_HW_OK;
  1107. channel = &fifo->channel;
  1108. if (((t_code & 0x7) < 0) || ((t_code & 0x7) > 0x4)) {
  1109. status = VXGE_HW_ERR_INVALID_TCODE;
  1110. goto exit;
  1111. }
  1112. fifo->stats->txd_t_code_err_cnt[t_code]++;
  1113. exit:
  1114. return status;
  1115. }
  1116. /**
  1117. * vxge_hw_fifo_txdl_free - Free descriptor.
  1118. * @fifo: Handle to the fifo object used for non offload send
  1119. * @txdlh: Descriptor handle.
  1120. *
  1121. * Free the reserved descriptor. This operation is "symmetrical" to
  1122. * vxge_hw_fifo_txdl_reserve. The "free-ing" completes the descriptor's
  1123. * lifecycle.
  1124. *
  1125. * After free-ing (see vxge_hw_fifo_txdl_free()) the descriptor again can
  1126. * be:
  1127. *
  1128. * - reserved (vxge_hw_fifo_txdl_reserve);
  1129. *
  1130. * - posted (vxge_hw_fifo_txdl_post);
  1131. *
  1132. * - completed (vxge_hw_fifo_txdl_next_completed);
  1133. *
  1134. * - and recycled again (vxge_hw_fifo_txdl_free).
  1135. *
  1136. * For alternative state transitions and more details please refer to
  1137. * the design doc.
  1138. *
  1139. */
  1140. void vxge_hw_fifo_txdl_free(struct __vxge_hw_fifo *fifo, void *txdlh)
  1141. {
  1142. struct __vxge_hw_fifo_txdl_priv *txdl_priv;
  1143. u32 max_frags;
  1144. struct __vxge_hw_channel *channel;
  1145. channel = &fifo->channel;
  1146. txdl_priv = __vxge_hw_fifo_txdl_priv(fifo,
  1147. (struct vxge_hw_fifo_txd *)txdlh);
  1148. max_frags = fifo->config->max_frags;
  1149. vxge_hw_channel_dtr_free(channel, txdlh);
  1150. }
  1151. /**
  1152. * vxge_hw_vpath_mac_addr_add - Add the mac address entry for this vpath
  1153. * to MAC address table.
  1154. * @vp: Vpath handle.
  1155. * @macaddr: MAC address to be added for this vpath into the list
  1156. * @macaddr_mask: MAC address mask for macaddr
  1157. * @duplicate_mode: Duplicate MAC address add mode. Please see
  1158. * enum vxge_hw_vpath_mac_addr_add_mode{}
  1159. *
  1160. * Adds the given mac address and mac address mask into the list for this
  1161. * vpath.
  1162. * see also: vxge_hw_vpath_mac_addr_delete, vxge_hw_vpath_mac_addr_get and
  1163. * vxge_hw_vpath_mac_addr_get_next
  1164. *
  1165. */
  1166. enum vxge_hw_status
  1167. vxge_hw_vpath_mac_addr_add(
  1168. struct __vxge_hw_vpath_handle *vp,
  1169. u8 (macaddr)[ETH_ALEN],
  1170. u8 (macaddr_mask)[ETH_ALEN],
  1171. enum vxge_hw_vpath_mac_addr_add_mode duplicate_mode)
  1172. {
  1173. u32 i;
  1174. u64 data1 = 0ULL;
  1175. u64 data2 = 0ULL;
  1176. enum vxge_hw_status status = VXGE_HW_OK;
  1177. if (vp == NULL) {
  1178. status = VXGE_HW_ERR_INVALID_HANDLE;
  1179. goto exit;
  1180. }
  1181. for (i = 0; i < ETH_ALEN; i++) {
  1182. data1 <<= 8;
  1183. data1 |= (u8)macaddr[i];
  1184. data2 <<= 8;
  1185. data2 |= (u8)macaddr_mask[i];
  1186. }
  1187. switch (duplicate_mode) {
  1188. case VXGE_HW_VPATH_MAC_ADDR_ADD_DUPLICATE:
  1189. i = 0;
  1190. break;
  1191. case VXGE_HW_VPATH_MAC_ADDR_DISCARD_DUPLICATE:
  1192. i = 1;
  1193. break;
  1194. case VXGE_HW_VPATH_MAC_ADDR_REPLACE_DUPLICATE:
  1195. i = 2;
  1196. break;
  1197. default:
  1198. i = 0;
  1199. break;
  1200. }
  1201. status = __vxge_hw_vpath_rts_table_set(vp,
  1202. VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY,
  1203. VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
  1204. 0,
  1205. VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1),
  1206. VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(data2)|
  1207. VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MODE(i));
  1208. exit:
  1209. return status;
  1210. }
  1211. /**
  1212. * vxge_hw_vpath_mac_addr_get - Get the first mac address entry for this vpath
  1213. * from MAC address table.
  1214. * @vp: Vpath handle.
  1215. * @macaddr: First MAC address entry for this vpath in the list
  1216. * @macaddr_mask: MAC address mask for macaddr
  1217. *
  1218. * Returns the first mac address and mac address mask in the list for this
  1219. * vpath.
  1220. * see also: vxge_hw_vpath_mac_addr_get_next
  1221. *
  1222. */
  1223. enum vxge_hw_status
  1224. vxge_hw_vpath_mac_addr_get(
  1225. struct __vxge_hw_vpath_handle *vp,
  1226. u8 (macaddr)[ETH_ALEN],
  1227. u8 (macaddr_mask)[ETH_ALEN])
  1228. {
  1229. u32 i;
  1230. u64 data1 = 0ULL;
  1231. u64 data2 = 0ULL;
  1232. enum vxge_hw_status status = VXGE_HW_OK;
  1233. if (vp == NULL) {
  1234. status = VXGE_HW_ERR_INVALID_HANDLE;
  1235. goto exit;
  1236. }
  1237. status = __vxge_hw_vpath_rts_table_get(vp,
  1238. VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
  1239. VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
  1240. 0, &data1, &data2);
  1241. if (status != VXGE_HW_OK)
  1242. goto exit;
  1243. data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
  1244. data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2);
  1245. for (i = ETH_ALEN; i > 0; i--) {
  1246. macaddr[i-1] = (u8)(data1 & 0xFF);
  1247. data1 >>= 8;
  1248. macaddr_mask[i-1] = (u8)(data2 & 0xFF);
  1249. data2 >>= 8;
  1250. }
  1251. exit:
  1252. return status;
  1253. }
  1254. /**
  1255. * vxge_hw_vpath_mac_addr_get_next - Get the next mac address entry for this
  1256. * vpath
  1257. * from MAC address table.
  1258. * @vp: Vpath handle.
  1259. * @macaddr: Next MAC address entry for this vpath in the list
  1260. * @macaddr_mask: MAC address mask for macaddr
  1261. *
  1262. * Returns the next mac address and mac address mask in the list for this
  1263. * vpath.
  1264. * see also: vxge_hw_vpath_mac_addr_get
  1265. *
  1266. */
  1267. enum vxge_hw_status
  1268. vxge_hw_vpath_mac_addr_get_next(
  1269. struct __vxge_hw_vpath_handle *vp,
  1270. u8 (macaddr)[ETH_ALEN],
  1271. u8 (macaddr_mask)[ETH_ALEN])
  1272. {
  1273. u32 i;
  1274. u64 data1 = 0ULL;
  1275. u64 data2 = 0ULL;
  1276. enum vxge_hw_status status = VXGE_HW_OK;
  1277. if (vp == NULL) {
  1278. status = VXGE_HW_ERR_INVALID_HANDLE;
  1279. goto exit;
  1280. }
  1281. status = __vxge_hw_vpath_rts_table_get(vp,
  1282. VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY,
  1283. VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
  1284. 0, &data1, &data2);
  1285. if (status != VXGE_HW_OK)
  1286. goto exit;
  1287. data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
  1288. data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(data2);
  1289. for (i = ETH_ALEN; i > 0; i--) {
  1290. macaddr[i-1] = (u8)(data1 & 0xFF);
  1291. data1 >>= 8;
  1292. macaddr_mask[i-1] = (u8)(data2 & 0xFF);
  1293. data2 >>= 8;
  1294. }
  1295. exit:
  1296. return status;
  1297. }
  1298. /**
  1299. * vxge_hw_vpath_mac_addr_delete - Delete the mac address entry for this vpath
  1300. * to MAC address table.
  1301. * @vp: Vpath handle.
  1302. * @macaddr: MAC address to be added for this vpath into the list
  1303. * @macaddr_mask: MAC address mask for macaddr
  1304. *
  1305. * Delete the given mac address and mac address mask into the list for this
  1306. * vpath.
  1307. * see also: vxge_hw_vpath_mac_addr_add, vxge_hw_vpath_mac_addr_get and
  1308. * vxge_hw_vpath_mac_addr_get_next
  1309. *
  1310. */
  1311. enum vxge_hw_status
  1312. vxge_hw_vpath_mac_addr_delete(
  1313. struct __vxge_hw_vpath_handle *vp,
  1314. u8 (macaddr)[ETH_ALEN],
  1315. u8 (macaddr_mask)[ETH_ALEN])
  1316. {
  1317. u32 i;
  1318. u64 data1 = 0ULL;
  1319. u64 data2 = 0ULL;
  1320. enum vxge_hw_status status = VXGE_HW_OK;
  1321. if (vp == NULL) {
  1322. status = VXGE_HW_ERR_INVALID_HANDLE;
  1323. goto exit;
  1324. }
  1325. for (i = 0; i < ETH_ALEN; i++) {
  1326. data1 <<= 8;
  1327. data1 |= (u8)macaddr[i];
  1328. data2 <<= 8;
  1329. data2 |= (u8)macaddr_mask[i];
  1330. }
  1331. status = __vxge_hw_vpath_rts_table_set(vp,
  1332. VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY,
  1333. VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
  1334. 0,
  1335. VXGE_HW_RTS_ACCESS_STEER_DATA0_DA_MAC_ADDR(data1),
  1336. VXGE_HW_RTS_ACCESS_STEER_DATA1_DA_MAC_ADDR_MASK(data2));
  1337. exit:
  1338. return status;
  1339. }
  1340. /**
  1341. * vxge_hw_vpath_vid_add - Add the vlan id entry for this vpath
  1342. * to vlan id table.
  1343. * @vp: Vpath handle.
  1344. * @vid: vlan id to be added for this vpath into the list
  1345. *
  1346. * Adds the given vlan id into the list for this vpath.
  1347. * see also: vxge_hw_vpath_vid_delete, vxge_hw_vpath_vid_get and
  1348. * vxge_hw_vpath_vid_get_next
  1349. *
  1350. */
  1351. enum vxge_hw_status
  1352. vxge_hw_vpath_vid_add(struct __vxge_hw_vpath_handle *vp, u64 vid)
  1353. {
  1354. enum vxge_hw_status status = VXGE_HW_OK;
  1355. if (vp == NULL) {
  1356. status = VXGE_HW_ERR_INVALID_HANDLE;
  1357. goto exit;
  1358. }
  1359. status = __vxge_hw_vpath_rts_table_set(vp,
  1360. VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_ADD_ENTRY,
  1361. VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
  1362. 0, VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(vid), 0);
  1363. exit:
  1364. return status;
  1365. }
  1366. /**
  1367. * vxge_hw_vpath_vid_get - Get the first vid entry for this vpath
  1368. * from vlan id table.
  1369. * @vp: Vpath handle.
  1370. * @vid: Buffer to return vlan id
  1371. *
  1372. * Returns the first vlan id in the list for this vpath.
  1373. * see also: vxge_hw_vpath_vid_get_next
  1374. *
  1375. */
  1376. enum vxge_hw_status
  1377. vxge_hw_vpath_vid_get(struct __vxge_hw_vpath_handle *vp, u64 *vid)
  1378. {
  1379. u64 data;
  1380. enum vxge_hw_status status = VXGE_HW_OK;
  1381. if (vp == NULL) {
  1382. status = VXGE_HW_ERR_INVALID_HANDLE;
  1383. goto exit;
  1384. }
  1385. status = __vxge_hw_vpath_rts_table_get(vp,
  1386. VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
  1387. VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
  1388. 0, vid, &data);
  1389. *vid = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(*vid);
  1390. exit:
  1391. return status;
  1392. }
  1393. /**
  1394. * vxge_hw_vpath_vid_get_next - Get the next vid entry for this vpath
  1395. * from vlan id table.
  1396. * @vp: Vpath handle.
  1397. * @vid: Buffer to return vlan id
  1398. *
  1399. * Returns the next vlan id in the list for this vpath.
  1400. * see also: vxge_hw_vpath_vid_get
  1401. *
  1402. */
  1403. enum vxge_hw_status
  1404. vxge_hw_vpath_vid_get_next(struct __vxge_hw_vpath_handle *vp, u64 *vid)
  1405. {
  1406. u64 data;
  1407. enum vxge_hw_status status = VXGE_HW_OK;
  1408. if (vp == NULL) {
  1409. status = VXGE_HW_ERR_INVALID_HANDLE;
  1410. goto exit;
  1411. }
  1412. status = __vxge_hw_vpath_rts_table_get(vp,
  1413. VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY,
  1414. VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
  1415. 0, vid, &data);
  1416. *vid = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_VLAN_ID(*vid);
  1417. exit:
  1418. return status;
  1419. }
  1420. /**
  1421. * vxge_hw_vpath_vid_delete - Delete the vlan id entry for this vpath
  1422. * to vlan id table.
  1423. * @vp: Vpath handle.
  1424. * @vid: vlan id to be added for this vpath into the list
  1425. *
  1426. * Adds the given vlan id into the list for this vpath.
  1427. * see also: vxge_hw_vpath_vid_add, vxge_hw_vpath_vid_get and
  1428. * vxge_hw_vpath_vid_get_next
  1429. *
  1430. */
  1431. enum vxge_hw_status
  1432. vxge_hw_vpath_vid_delete(struct __vxge_hw_vpath_handle *vp, u64 vid)
  1433. {
  1434. enum vxge_hw_status status = VXGE_HW_OK;
  1435. if (vp == NULL) {
  1436. status = VXGE_HW_ERR_INVALID_HANDLE;
  1437. goto exit;
  1438. }
  1439. status = __vxge_hw_vpath_rts_table_set(vp,
  1440. VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_DELETE_ENTRY,
  1441. VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_VID,
  1442. 0, VXGE_HW_RTS_ACCESS_STEER_DATA0_VLAN_ID(vid), 0);
  1443. exit:
  1444. return status;
  1445. }
  1446. /**
  1447. * vxge_hw_vpath_promisc_enable - Enable promiscuous mode.
  1448. * @vp: Vpath handle.
  1449. *
  1450. * Enable promiscuous mode of Titan-e operation.
  1451. *
  1452. * See also: vxge_hw_vpath_promisc_disable().
  1453. */
  1454. enum vxge_hw_status vxge_hw_vpath_promisc_enable(
  1455. struct __vxge_hw_vpath_handle *vp)
  1456. {
  1457. u64 val64;
  1458. struct __vxge_hw_virtualpath *vpath;
  1459. enum vxge_hw_status status = VXGE_HW_OK;
  1460. if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
  1461. status = VXGE_HW_ERR_INVALID_HANDLE;
  1462. goto exit;
  1463. }
  1464. vpath = vp->vpath;
  1465. /* Enable promiscous mode for function 0 only */
  1466. if (!(vpath->hldev->access_rights &
  1467. VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM))
  1468. return VXGE_HW_OK;
  1469. val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
  1470. if (!(val64 & VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN)) {
  1471. val64 |= VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN |
  1472. VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN |
  1473. VXGE_HW_RXMAC_VCFG0_BCAST_EN |
  1474. VXGE_HW_RXMAC_VCFG0_ALL_VID_EN;
  1475. writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
  1476. }
  1477. exit:
  1478. return status;
  1479. }
  1480. /**
  1481. * vxge_hw_vpath_promisc_disable - Disable promiscuous mode.
  1482. * @vp: Vpath handle.
  1483. *
  1484. * Disable promiscuous mode of Titan-e operation.
  1485. *
  1486. * See also: vxge_hw_vpath_promisc_enable().
  1487. */
  1488. enum vxge_hw_status vxge_hw_vpath_promisc_disable(
  1489. struct __vxge_hw_vpath_handle *vp)
  1490. {
  1491. u64 val64;
  1492. struct __vxge_hw_virtualpath *vpath;
  1493. enum vxge_hw_status status = VXGE_HW_OK;
  1494. if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
  1495. status = VXGE_HW_ERR_INVALID_HANDLE;
  1496. goto exit;
  1497. }
  1498. vpath = vp->vpath;
  1499. val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
  1500. if (val64 & VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN) {
  1501. val64 &= ~(VXGE_HW_RXMAC_VCFG0_UCAST_ALL_ADDR_EN |
  1502. VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN |
  1503. VXGE_HW_RXMAC_VCFG0_ALL_VID_EN);
  1504. writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
  1505. }
  1506. exit:
  1507. return status;
  1508. }
  1509. /*
  1510. * vxge_hw_vpath_bcast_enable - Enable broadcast
  1511. * @vp: Vpath handle.
  1512. *
  1513. * Enable receiving broadcasts.
  1514. */
  1515. enum vxge_hw_status vxge_hw_vpath_bcast_enable(
  1516. struct __vxge_hw_vpath_handle *vp)
  1517. {
  1518. u64 val64;
  1519. struct __vxge_hw_virtualpath *vpath;
  1520. enum vxge_hw_status status = VXGE_HW_OK;
  1521. if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
  1522. status = VXGE_HW_ERR_INVALID_HANDLE;
  1523. goto exit;
  1524. }
  1525. vpath = vp->vpath;
  1526. val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
  1527. if (!(val64 & VXGE_HW_RXMAC_VCFG0_BCAST_EN)) {
  1528. val64 |= VXGE_HW_RXMAC_VCFG0_BCAST_EN;
  1529. writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
  1530. }
  1531. exit:
  1532. return status;
  1533. }
  1534. /**
  1535. * vxge_hw_vpath_mcast_enable - Enable multicast addresses.
  1536. * @vp: Vpath handle.
  1537. *
  1538. * Enable Titan-e multicast addresses.
  1539. * Returns: VXGE_HW_OK on success.
  1540. *
  1541. */
  1542. enum vxge_hw_status vxge_hw_vpath_mcast_enable(
  1543. struct __vxge_hw_vpath_handle *vp)
  1544. {
  1545. u64 val64;
  1546. struct __vxge_hw_virtualpath *vpath;
  1547. enum vxge_hw_status status = VXGE_HW_OK;
  1548. if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
  1549. status = VXGE_HW_ERR_INVALID_HANDLE;
  1550. goto exit;
  1551. }
  1552. vpath = vp->vpath;
  1553. val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
  1554. if (!(val64 & VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN)) {
  1555. val64 |= VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
  1556. writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
  1557. }
  1558. exit:
  1559. return status;
  1560. }
  1561. /**
  1562. * vxge_hw_vpath_mcast_disable - Disable multicast addresses.
  1563. * @vp: Vpath handle.
  1564. *
  1565. * Disable Titan-e multicast addresses.
  1566. * Returns: VXGE_HW_OK - success.
  1567. * VXGE_HW_ERR_INVALID_HANDLE - Invalid handle
  1568. *
  1569. */
  1570. enum vxge_hw_status
  1571. vxge_hw_vpath_mcast_disable(struct __vxge_hw_vpath_handle *vp)
  1572. {
  1573. u64 val64;
  1574. struct __vxge_hw_virtualpath *vpath;
  1575. enum vxge_hw_status status = VXGE_HW_OK;
  1576. if ((vp == NULL) || (vp->vpath->ringh == NULL)) {
  1577. status = VXGE_HW_ERR_INVALID_HANDLE;
  1578. goto exit;
  1579. }
  1580. vpath = vp->vpath;
  1581. val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
  1582. if (val64 & VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN) {
  1583. val64 &= ~VXGE_HW_RXMAC_VCFG0_MCAST_ALL_ADDR_EN;
  1584. writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
  1585. }
  1586. exit:
  1587. return status;
  1588. }
  1589. /*
  1590. * __vxge_hw_vpath_alarm_process - Process Alarms.
  1591. * @vpath: Virtual Path.
  1592. * @skip_alarms: Do not clear the alarms
  1593. *
  1594. * Process vpath alarms.
  1595. *
  1596. */
  1597. enum vxge_hw_status __vxge_hw_vpath_alarm_process(
  1598. struct __vxge_hw_virtualpath *vpath,
  1599. u32 skip_alarms)
  1600. {
  1601. u64 val64;
  1602. u64 alarm_status;
  1603. u64 pic_status;
  1604. struct __vxge_hw_device *hldev = NULL;
  1605. enum vxge_hw_event alarm_event = VXGE_HW_EVENT_UNKNOWN;
  1606. u64 mask64;
  1607. struct vxge_hw_vpath_stats_sw_info *sw_stats;
  1608. struct vxge_hw_vpath_reg __iomem *vp_reg;
  1609. if (vpath == NULL) {
  1610. alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_UNKNOWN,
  1611. alarm_event);
  1612. goto out;
  1613. }
  1614. hldev = vpath->hldev;
  1615. vp_reg = vpath->vp_reg;
  1616. alarm_status = readq(&vp_reg->vpath_general_int_status);
  1617. if (alarm_status == VXGE_HW_ALL_FOXES) {
  1618. alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_SLOT_FREEZE,
  1619. alarm_event);
  1620. goto out;
  1621. }
  1622. sw_stats = vpath->sw_stats;
  1623. if (alarm_status & ~(
  1624. VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT |
  1625. VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT |
  1626. VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT |
  1627. VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT)) {
  1628. sw_stats->error_stats.unknown_alarms++;
  1629. alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_UNKNOWN,
  1630. alarm_event);
  1631. goto out;
  1632. }
  1633. if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT) {
  1634. val64 = readq(&vp_reg->xgmac_vp_int_status);
  1635. if (val64 &
  1636. VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT) {
  1637. val64 = readq(&vp_reg->asic_ntwk_vp_err_reg);
  1638. if (((val64 &
  1639. VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT) &&
  1640. (!(val64 &
  1641. VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK))) ||
  1642. ((val64 &
  1643. VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR)
  1644. && (!(val64 &
  1645. VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR)
  1646. ))) {
  1647. sw_stats->error_stats.network_sustained_fault++;
  1648. writeq(
  1649. VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT,
  1650. &vp_reg->asic_ntwk_vp_err_mask);
  1651. __vxge_hw_device_handle_link_down_ind(hldev);
  1652. alarm_event = VXGE_HW_SET_LEVEL(
  1653. VXGE_HW_EVENT_LINK_DOWN, alarm_event);
  1654. }
  1655. if (((val64 &
  1656. VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK) &&
  1657. (!(val64 &
  1658. VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT))) ||
  1659. ((val64 &
  1660. VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR)
  1661. && (!(val64 &
  1662. VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR)
  1663. ))) {
  1664. sw_stats->error_stats.network_sustained_ok++;
  1665. writeq(
  1666. VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK,
  1667. &vp_reg->asic_ntwk_vp_err_mask);
  1668. __vxge_hw_device_handle_link_up_ind(hldev);
  1669. alarm_event = VXGE_HW_SET_LEVEL(
  1670. VXGE_HW_EVENT_LINK_UP, alarm_event);
  1671. }
  1672. writeq(VXGE_HW_INTR_MASK_ALL,
  1673. &vp_reg->asic_ntwk_vp_err_reg);
  1674. alarm_event = VXGE_HW_SET_LEVEL(
  1675. VXGE_HW_EVENT_ALARM_CLEARED, alarm_event);
  1676. if (skip_alarms)
  1677. return VXGE_HW_OK;
  1678. }
  1679. }
  1680. if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT) {
  1681. pic_status = readq(&vp_reg->vpath_ppif_int_status);
  1682. if (pic_status &
  1683. VXGE_HW_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_GENERAL_INT) {
  1684. val64 = readq(&vp_reg->general_errors_reg);
  1685. mask64 = readq(&vp_reg->general_errors_mask);
  1686. if ((val64 &
  1687. VXGE_HW_GENERAL_ERRORS_REG_INI_SERR_DET) &
  1688. ~mask64) {
  1689. sw_stats->error_stats.ini_serr_det++;
  1690. alarm_event = VXGE_HW_SET_LEVEL(
  1691. VXGE_HW_EVENT_SERR, alarm_event);
  1692. }
  1693. if ((val64 &
  1694. VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW) &
  1695. ~mask64) {
  1696. sw_stats->error_stats.dblgen_fifo0_overflow++;
  1697. alarm_event = VXGE_HW_SET_LEVEL(
  1698. VXGE_HW_EVENT_FIFO_ERR, alarm_event);
  1699. }
  1700. if ((val64 &
  1701. VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR) &
  1702. ~mask64)
  1703. sw_stats->error_stats.statsb_pif_chain_error++;
  1704. if ((val64 &
  1705. VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ) &
  1706. ~mask64)
  1707. sw_stats->error_stats.statsb_drop_timeout++;
  1708. if ((val64 &
  1709. VXGE_HW_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS) &
  1710. ~mask64)
  1711. sw_stats->error_stats.target_illegal_access++;
  1712. if (!skip_alarms) {
  1713. writeq(VXGE_HW_INTR_MASK_ALL,
  1714. &vp_reg->general_errors_reg);
  1715. alarm_event = VXGE_HW_SET_LEVEL(
  1716. VXGE_HW_EVENT_ALARM_CLEARED,
  1717. alarm_event);
  1718. }
  1719. }
  1720. if (pic_status &
  1721. VXGE_HW_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_KDFCCTL_INT) {
  1722. val64 = readq(&vp_reg->kdfcctl_errors_reg);
  1723. mask64 = readq(&vp_reg->kdfcctl_errors_mask);
  1724. if ((val64 &
  1725. VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR) &
  1726. ~mask64) {
  1727. sw_stats->error_stats.kdfcctl_fifo0_overwrite++;
  1728. alarm_event = VXGE_HW_SET_LEVEL(
  1729. VXGE_HW_EVENT_FIFO_ERR,
  1730. alarm_event);
  1731. }
  1732. if ((val64 &
  1733. VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON) &
  1734. ~mask64) {
  1735. sw_stats->error_stats.kdfcctl_fifo0_poison++;
  1736. alarm_event = VXGE_HW_SET_LEVEL(
  1737. VXGE_HW_EVENT_FIFO_ERR,
  1738. alarm_event);
  1739. }
  1740. if ((val64 &
  1741. VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR) &
  1742. ~mask64) {
  1743. sw_stats->error_stats.kdfcctl_fifo0_dma_error++;
  1744. alarm_event = VXGE_HW_SET_LEVEL(
  1745. VXGE_HW_EVENT_FIFO_ERR,
  1746. alarm_event);
  1747. }
  1748. if (!skip_alarms) {
  1749. writeq(VXGE_HW_INTR_MASK_ALL,
  1750. &vp_reg->kdfcctl_errors_reg);
  1751. alarm_event = VXGE_HW_SET_LEVEL(
  1752. VXGE_HW_EVENT_ALARM_CLEARED,
  1753. alarm_event);
  1754. }
  1755. }
  1756. }
  1757. if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT) {
  1758. val64 = readq(&vp_reg->wrdma_alarm_status);
  1759. if (val64 & VXGE_HW_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT) {
  1760. val64 = readq(&vp_reg->prc_alarm_reg);
  1761. mask64 = readq(&vp_reg->prc_alarm_mask);
  1762. if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP)&
  1763. ~mask64)
  1764. sw_stats->error_stats.prc_ring_bumps++;
  1765. if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ERR) &
  1766. ~mask64) {
  1767. sw_stats->error_stats.prc_rxdcm_sc_err++;
  1768. alarm_event = VXGE_HW_SET_LEVEL(
  1769. VXGE_HW_EVENT_VPATH_ERR,
  1770. alarm_event);
  1771. }
  1772. if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT)
  1773. & ~mask64) {
  1774. sw_stats->error_stats.prc_rxdcm_sc_abort++;
  1775. alarm_event = VXGE_HW_SET_LEVEL(
  1776. VXGE_HW_EVENT_VPATH_ERR,
  1777. alarm_event);
  1778. }
  1779. if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR)
  1780. & ~mask64) {
  1781. sw_stats->error_stats.prc_quanta_size_err++;
  1782. alarm_event = VXGE_HW_SET_LEVEL(
  1783. VXGE_HW_EVENT_VPATH_ERR,
  1784. alarm_event);
  1785. }
  1786. if (!skip_alarms) {
  1787. writeq(VXGE_HW_INTR_MASK_ALL,
  1788. &vp_reg->prc_alarm_reg);
  1789. alarm_event = VXGE_HW_SET_LEVEL(
  1790. VXGE_HW_EVENT_ALARM_CLEARED,
  1791. alarm_event);
  1792. }
  1793. }
  1794. }
  1795. out:
  1796. hldev->stats.sw_dev_err_stats.vpath_alarms++;
  1797. if ((alarm_event == VXGE_HW_EVENT_ALARM_CLEARED) ||
  1798. (alarm_event == VXGE_HW_EVENT_UNKNOWN))
  1799. return VXGE_HW_OK;
  1800. __vxge_hw_device_handle_error(hldev, vpath->vp_id, alarm_event);
  1801. if (alarm_event == VXGE_HW_EVENT_SERR)
  1802. return VXGE_HW_ERR_CRITICAL;
  1803. return (alarm_event == VXGE_HW_EVENT_SLOT_FREEZE) ?
  1804. VXGE_HW_ERR_SLOT_FREEZE :
  1805. (alarm_event == VXGE_HW_EVENT_FIFO_ERR) ? VXGE_HW_ERR_FIFO :
  1806. VXGE_HW_ERR_VPATH;
  1807. }
  1808. /*
  1809. * vxge_hw_vpath_alarm_process - Process Alarms.
  1810. * @vpath: Virtual Path.
  1811. * @skip_alarms: Do not clear the alarms
  1812. *
  1813. * Process vpath alarms.
  1814. *
  1815. */
  1816. enum vxge_hw_status vxge_hw_vpath_alarm_process(
  1817. struct __vxge_hw_vpath_handle *vp,
  1818. u32 skip_alarms)
  1819. {
  1820. enum vxge_hw_status status = VXGE_HW_OK;
  1821. if (vp == NULL) {
  1822. status = VXGE_HW_ERR_INVALID_HANDLE;
  1823. goto exit;
  1824. }
  1825. status = __vxge_hw_vpath_alarm_process(vp->vpath, skip_alarms);
  1826. exit:
  1827. return status;
  1828. }
  1829. /**
  1830. * vxge_hw_vpath_msix_set - Associate MSIX vectors with TIM interrupts and
  1831. * alrms
  1832. * @vp: Virtual Path handle.
  1833. * @tim_msix_id: MSIX vectors associated with VXGE_HW_MAX_INTR_PER_VP number of
  1834. * interrupts(Can be repeated). If fifo or ring are not enabled
  1835. * the MSIX vector for that should be set to 0
  1836. * @alarm_msix_id: MSIX vector for alarm.
  1837. *
  1838. * This API will associate a given MSIX vector numbers with the four TIM
  1839. * interrupts and alarm interrupt.
  1840. */
  1841. enum vxge_hw_status
  1842. vxge_hw_vpath_msix_set(struct __vxge_hw_vpath_handle *vp, int *tim_msix_id,
  1843. int alarm_msix_id)
  1844. {
  1845. u64 val64;
  1846. struct __vxge_hw_virtualpath *vpath = vp->vpath;
  1847. struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
  1848. u32 first_vp_id = vpath->hldev->first_vp_id;
  1849. val64 = VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(
  1850. (first_vp_id * 4) + tim_msix_id[0]) |
  1851. VXGE_HW_INTERRUPT_CFG0_GROUP1_MSIX_FOR_TXTI(
  1852. (first_vp_id * 4) + tim_msix_id[1]) |
  1853. VXGE_HW_INTERRUPT_CFG0_GROUP2_MSIX_FOR_TXTI(
  1854. (first_vp_id * 4) + tim_msix_id[2]);
  1855. val64 |= VXGE_HW_INTERRUPT_CFG0_GROUP3_MSIX_FOR_TXTI(
  1856. (first_vp_id * 4) + tim_msix_id[3]);
  1857. writeq(val64, &vp_reg->interrupt_cfg0);
  1858. writeq(VXGE_HW_INTERRUPT_CFG2_ALARM_MAP_TO_MSG(
  1859. (first_vp_id * 4) + alarm_msix_id),
  1860. &vp_reg->interrupt_cfg2);
  1861. if (vpath->hldev->config.intr_mode ==
  1862. VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) {
  1863. __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
  1864. VXGE_HW_ONE_SHOT_VECT1_EN_ONE_SHOT_VECT1_EN,
  1865. 0, 32), &vp_reg->one_shot_vect1_en);
  1866. }
  1867. if (vpath->hldev->config.intr_mode ==
  1868. VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) {
  1869. __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
  1870. VXGE_HW_ONE_SHOT_VECT2_EN_ONE_SHOT_VECT2_EN,
  1871. 0, 32), &vp_reg->one_shot_vect2_en);
  1872. __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(
  1873. VXGE_HW_ONE_SHOT_VECT3_EN_ONE_SHOT_VECT3_EN,
  1874. 0, 32), &vp_reg->one_shot_vect3_en);
  1875. }
  1876. return VXGE_HW_OK;
  1877. }
  1878. /**
  1879. * vxge_hw_vpath_msix_mask - Mask MSIX Vector.
  1880. * @vp: Virtual Path handle.
  1881. * @msix_id: MSIX ID
  1882. *
  1883. * The function masks the msix interrupt for the given msix_id
  1884. *
  1885. * Returns: 0,
  1886. * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
  1887. * status.
  1888. * See also:
  1889. */
  1890. void
  1891. vxge_hw_vpath_msix_mask(struct __vxge_hw_vpath_handle *vp, int msix_id)
  1892. {
  1893. struct __vxge_hw_device *hldev = vp->vpath->hldev;
  1894. __vxge_hw_pio_mem_write32_upper(
  1895. (u32) vxge_bVALn(vxge_mBIT(hldev->first_vp_id +
  1896. (msix_id / 4)), 0, 32),
  1897. &hldev->common_reg->set_msix_mask_vect[msix_id % 4]);
  1898. return;
  1899. }
  1900. /**
  1901. * vxge_hw_vpath_msix_clear - Clear MSIX Vector.
  1902. * @vp: Virtual Path handle.
  1903. * @msix_id: MSI ID
  1904. *
  1905. * The function clears the msix interrupt for the given msix_id
  1906. *
  1907. * Returns: 0,
  1908. * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
  1909. * status.
  1910. * See also:
  1911. */
  1912. void
  1913. vxge_hw_vpath_msix_clear(struct __vxge_hw_vpath_handle *vp, int msix_id)
  1914. {
  1915. struct __vxge_hw_device *hldev = vp->vpath->hldev;
  1916. if (hldev->config.intr_mode ==
  1917. VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) {
  1918. __vxge_hw_pio_mem_write32_upper(
  1919. (u32)vxge_bVALn(vxge_mBIT(hldev->first_vp_id +
  1920. (msix_id/4)), 0, 32),
  1921. &hldev->common_reg->
  1922. clr_msix_one_shot_vec[msix_id%4]);
  1923. } else {
  1924. __vxge_hw_pio_mem_write32_upper(
  1925. (u32)vxge_bVALn(vxge_mBIT(hldev->first_vp_id +
  1926. (msix_id/4)), 0, 32),
  1927. &hldev->common_reg->
  1928. clear_msix_mask_vect[msix_id%4]);
  1929. }
  1930. return;
  1931. }
  1932. /**
  1933. * vxge_hw_vpath_msix_unmask - Unmask the MSIX Vector.
  1934. * @vp: Virtual Path handle.
  1935. * @msix_id: MSI ID
  1936. *
  1937. * The function unmasks the msix interrupt for the given msix_id
  1938. *
  1939. * Returns: 0,
  1940. * Otherwise, VXGE_HW_ERR_WRONG_IRQ if the msix index is out of range
  1941. * status.
  1942. * See also:
  1943. */
  1944. void
  1945. vxge_hw_vpath_msix_unmask(struct __vxge_hw_vpath_handle *vp, int msix_id)
  1946. {
  1947. struct __vxge_hw_device *hldev = vp->vpath->hldev;
  1948. __vxge_hw_pio_mem_write32_upper(
  1949. (u32)vxge_bVALn(vxge_mBIT(hldev->first_vp_id +
  1950. (msix_id/4)), 0, 32),
  1951. &hldev->common_reg->clear_msix_mask_vect[msix_id%4]);
  1952. return;
  1953. }
  1954. /**
  1955. * vxge_hw_vpath_msix_mask_all - Mask all MSIX vectors for the vpath.
  1956. * @vp: Virtual Path handle.
  1957. *
  1958. * The function masks all msix interrupt for the given vpath
  1959. *
  1960. */
  1961. void
  1962. vxge_hw_vpath_msix_mask_all(struct __vxge_hw_vpath_handle *vp)
  1963. {
  1964. __vxge_hw_pio_mem_write32_upper(
  1965. (u32)vxge_bVALn(vxge_mBIT(vp->vpath->vp_id), 0, 32),
  1966. &vp->vpath->hldev->common_reg->set_msix_mask_all_vect);
  1967. return;
  1968. }
  1969. /**
  1970. * vxge_hw_vpath_inta_mask_tx_rx - Mask Tx and Rx interrupts.
  1971. * @vp: Virtual Path handle.
  1972. *
  1973. * Mask Tx and Rx vpath interrupts.
  1974. *
  1975. * See also: vxge_hw_vpath_inta_mask_tx_rx()
  1976. */
  1977. void vxge_hw_vpath_inta_mask_tx_rx(struct __vxge_hw_vpath_handle *vp)
  1978. {
  1979. u64 tim_int_mask0[4] = {[0 ...3] = 0};
  1980. u32 tim_int_mask1[4] = {[0 ...3] = 0};
  1981. u64 val64;
  1982. struct __vxge_hw_device *hldev = vp->vpath->hldev;
  1983. VXGE_HW_DEVICE_TIM_INT_MASK_SET(tim_int_mask0,
  1984. tim_int_mask1, vp->vpath->vp_id);
  1985. val64 = readq(&hldev->common_reg->tim_int_mask0);
  1986. if ((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
  1987. (tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
  1988. writeq((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
  1989. tim_int_mask0[VXGE_HW_VPATH_INTR_RX] | val64),
  1990. &hldev->common_reg->tim_int_mask0);
  1991. }
  1992. val64 = readl(&hldev->common_reg->tim_int_mask1);
  1993. if ((tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) ||
  1994. (tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) {
  1995. __vxge_hw_pio_mem_write32_upper(
  1996. (tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
  1997. tim_int_mask1[VXGE_HW_VPATH_INTR_RX] | val64),
  1998. &hldev->common_reg->tim_int_mask1);
  1999. }
  2000. return;
  2001. }
  2002. /**
  2003. * vxge_hw_vpath_inta_unmask_tx_rx - Unmask Tx and Rx interrupts.
  2004. * @vp: Virtual Path handle.
  2005. *
  2006. * Unmask Tx and Rx vpath interrupts.
  2007. *
  2008. * See also: vxge_hw_vpath_inta_mask_tx_rx()
  2009. */
  2010. void vxge_hw_vpath_inta_unmask_tx_rx(struct __vxge_hw_vpath_handle *vp)
  2011. {
  2012. u64 tim_int_mask0[4] = {[0 ...3] = 0};
  2013. u32 tim_int_mask1[4] = {[0 ...3] = 0};
  2014. u64 val64;
  2015. struct __vxge_hw_device *hldev = vp->vpath->hldev;
  2016. VXGE_HW_DEVICE_TIM_INT_MASK_SET(tim_int_mask0,
  2017. tim_int_mask1, vp->vpath->vp_id);
  2018. val64 = readq(&hldev->common_reg->tim_int_mask0);
  2019. if ((tim_int_mask0[VXGE_HW_VPATH_INTR_TX] != 0) ||
  2020. (tim_int_mask0[VXGE_HW_VPATH_INTR_RX] != 0)) {
  2021. writeq((~(tim_int_mask0[VXGE_HW_VPATH_INTR_TX] |
  2022. tim_int_mask0[VXGE_HW_VPATH_INTR_RX])) & val64,
  2023. &hldev->common_reg->tim_int_mask0);
  2024. }
  2025. if ((tim_int_mask1[VXGE_HW_VPATH_INTR_TX] != 0) ||
  2026. (tim_int_mask1[VXGE_HW_VPATH_INTR_RX] != 0)) {
  2027. __vxge_hw_pio_mem_write32_upper(
  2028. (~(tim_int_mask1[VXGE_HW_VPATH_INTR_TX] |
  2029. tim_int_mask1[VXGE_HW_VPATH_INTR_RX])) & val64,
  2030. &hldev->common_reg->tim_int_mask1);
  2031. }
  2032. return;
  2033. }
  2034. /**
  2035. * vxge_hw_vpath_poll_rx - Poll Rx Virtual Path for completed
  2036. * descriptors and process the same.
  2037. * @ring: Handle to the ring object used for receive
  2038. *
  2039. * The function polls the Rx for the completed descriptors and calls
  2040. * the driver via supplied completion callback.
  2041. *
  2042. * Returns: VXGE_HW_OK, if the polling is completed successful.
  2043. * VXGE_HW_COMPLETIONS_REMAIN: There are still more completed
  2044. * descriptors available which are yet to be processed.
  2045. *
  2046. * See also: vxge_hw_vpath_poll_rx()
  2047. */
  2048. enum vxge_hw_status vxge_hw_vpath_poll_rx(struct __vxge_hw_ring *ring)
  2049. {
  2050. u8 t_code;
  2051. enum vxge_hw_status status = VXGE_HW_OK;
  2052. void *first_rxdh;
  2053. u64 val64 = 0;
  2054. int new_count = 0;
  2055. ring->cmpl_cnt = 0;
  2056. status = vxge_hw_ring_rxd_next_completed(ring, &first_rxdh, &t_code);
  2057. if (status == VXGE_HW_OK)
  2058. ring->callback(ring, first_rxdh,
  2059. t_code, ring->channel.userdata);
  2060. if (ring->cmpl_cnt != 0) {
  2061. ring->doorbell_cnt += ring->cmpl_cnt;
  2062. if (ring->doorbell_cnt >= ring->rxds_limit) {
  2063. /*
  2064. * Each RxD is of 4 qwords, update the number of
  2065. * qwords replenished
  2066. */
  2067. new_count = (ring->doorbell_cnt * 4);
  2068. /* For each block add 4 more qwords */
  2069. ring->total_db_cnt += ring->doorbell_cnt;
  2070. if (ring->total_db_cnt >= ring->rxds_per_block) {
  2071. new_count += 4;
  2072. /* Reset total count */
  2073. ring->total_db_cnt %= ring->rxds_per_block;
  2074. }
  2075. writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(new_count),
  2076. &ring->vp_reg->prc_rxd_doorbell);
  2077. val64 =
  2078. readl(&ring->common_reg->titan_general_int_status);
  2079. ring->doorbell_cnt = 0;
  2080. }
  2081. }
  2082. return status;
  2083. }
  2084. /**
  2085. * vxge_hw_vpath_poll_tx - Poll Tx for completed descriptors and process
  2086. * the same.
  2087. * @fifo: Handle to the fifo object used for non offload send
  2088. *
  2089. * The function polls the Tx for the completed descriptors and calls
  2090. * the driver via supplied completion callback.
  2091. *
  2092. * Returns: VXGE_HW_OK, if the polling is completed successful.
  2093. * VXGE_HW_COMPLETIONS_REMAIN: There are still more completed
  2094. * descriptors available which are yet to be processed.
  2095. *
  2096. * See also: vxge_hw_vpath_poll_tx().
  2097. */
  2098. enum vxge_hw_status vxge_hw_vpath_poll_tx(struct __vxge_hw_fifo *fifo,
  2099. void **skb_ptr)
  2100. {
  2101. enum vxge_hw_fifo_tcode t_code;
  2102. void *first_txdlh;
  2103. enum vxge_hw_status status = VXGE_HW_OK;
  2104. struct __vxge_hw_channel *channel;
  2105. channel = &fifo->channel;
  2106. status = vxge_hw_fifo_txdl_next_completed(fifo,
  2107. &first_txdlh, &t_code);
  2108. if (status == VXGE_HW_OK)
  2109. if (fifo->callback(fifo, first_txdlh,
  2110. t_code, channel->userdata, skb_ptr) != VXGE_HW_OK)
  2111. status = VXGE_HW_COMPLETIONS_REMAIN;
  2112. return status;
  2113. }