smsc95xx.c 31 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2008 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. *
  19. *****************************************************************************/
  20. #include <linux/module.h>
  21. #include <linux/kmod.h>
  22. #include <linux/init.h>
  23. #include <linux/netdevice.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/mii.h>
  27. #include <linux/usb.h>
  28. #include <linux/crc32.h>
  29. #include <linux/usb/usbnet.h>
  30. #include "smsc95xx.h"
  31. #define SMSC_CHIPNAME "smsc95xx"
  32. #define SMSC_DRIVER_VERSION "1.0.4"
  33. #define HS_USB_PKT_SIZE (512)
  34. #define FS_USB_PKT_SIZE (64)
  35. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  36. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  37. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  38. #define MAX_SINGLE_PACKET_SIZE (2048)
  39. #define LAN95XX_EEPROM_MAGIC (0x9500)
  40. #define EEPROM_MAC_OFFSET (0x01)
  41. #define DEFAULT_TX_CSUM_ENABLE (true)
  42. #define DEFAULT_RX_CSUM_ENABLE (true)
  43. #define SMSC95XX_INTERNAL_PHY_ID (1)
  44. #define SMSC95XX_TX_OVERHEAD (8)
  45. #define SMSC95XX_TX_OVERHEAD_CSUM (12)
  46. struct smsc95xx_priv {
  47. u32 mac_cr;
  48. spinlock_t mac_cr_lock;
  49. bool use_tx_csum;
  50. bool use_rx_csum;
  51. };
  52. struct usb_context {
  53. struct usb_ctrlrequest req;
  54. struct usbnet *dev;
  55. };
  56. static int turbo_mode = true;
  57. module_param(turbo_mode, bool, 0644);
  58. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  59. static int smsc95xx_read_reg(struct usbnet *dev, u32 index, u32 *data)
  60. {
  61. u32 *buf = kmalloc(4, GFP_KERNEL);
  62. int ret;
  63. BUG_ON(!dev);
  64. if (!buf)
  65. return -ENOMEM;
  66. ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
  67. USB_VENDOR_REQUEST_READ_REGISTER,
  68. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  69. 00, index, buf, 4, USB_CTRL_GET_TIMEOUT);
  70. if (unlikely(ret < 0))
  71. devwarn(dev, "Failed to read register index 0x%08x", index);
  72. le32_to_cpus(buf);
  73. *data = *buf;
  74. kfree(buf);
  75. return ret;
  76. }
  77. static int smsc95xx_write_reg(struct usbnet *dev, u32 index, u32 data)
  78. {
  79. u32 *buf = kmalloc(4, GFP_KERNEL);
  80. int ret;
  81. BUG_ON(!dev);
  82. if (!buf)
  83. return -ENOMEM;
  84. *buf = data;
  85. cpu_to_le32s(buf);
  86. ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
  87. USB_VENDOR_REQUEST_WRITE_REGISTER,
  88. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  89. 00, index, buf, 4, USB_CTRL_SET_TIMEOUT);
  90. if (unlikely(ret < 0))
  91. devwarn(dev, "Failed to write register index 0x%08x", index);
  92. kfree(buf);
  93. return ret;
  94. }
  95. /* Loop until the read is completed with timeout
  96. * called with phy_mutex held */
  97. static int smsc95xx_phy_wait_not_busy(struct usbnet *dev)
  98. {
  99. unsigned long start_time = jiffies;
  100. u32 val;
  101. do {
  102. smsc95xx_read_reg(dev, MII_ADDR, &val);
  103. if (!(val & MII_BUSY_))
  104. return 0;
  105. } while (!time_after(jiffies, start_time + HZ));
  106. return -EIO;
  107. }
  108. static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  109. {
  110. struct usbnet *dev = netdev_priv(netdev);
  111. u32 val, addr;
  112. mutex_lock(&dev->phy_mutex);
  113. /* confirm MII not busy */
  114. if (smsc95xx_phy_wait_not_busy(dev)) {
  115. devwarn(dev, "MII is busy in smsc95xx_mdio_read");
  116. mutex_unlock(&dev->phy_mutex);
  117. return -EIO;
  118. }
  119. /* set the address, index & direction (read from PHY) */
  120. phy_id &= dev->mii.phy_id_mask;
  121. idx &= dev->mii.reg_num_mask;
  122. addr = (phy_id << 11) | (idx << 6) | MII_READ_;
  123. smsc95xx_write_reg(dev, MII_ADDR, addr);
  124. if (smsc95xx_phy_wait_not_busy(dev)) {
  125. devwarn(dev, "Timed out reading MII reg %02X", idx);
  126. mutex_unlock(&dev->phy_mutex);
  127. return -EIO;
  128. }
  129. smsc95xx_read_reg(dev, MII_DATA, &val);
  130. mutex_unlock(&dev->phy_mutex);
  131. return (u16)(val & 0xFFFF);
  132. }
  133. static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  134. int regval)
  135. {
  136. struct usbnet *dev = netdev_priv(netdev);
  137. u32 val, addr;
  138. mutex_lock(&dev->phy_mutex);
  139. /* confirm MII not busy */
  140. if (smsc95xx_phy_wait_not_busy(dev)) {
  141. devwarn(dev, "MII is busy in smsc95xx_mdio_write");
  142. mutex_unlock(&dev->phy_mutex);
  143. return;
  144. }
  145. val = regval;
  146. smsc95xx_write_reg(dev, MII_DATA, val);
  147. /* set the address, index & direction (write to PHY) */
  148. phy_id &= dev->mii.phy_id_mask;
  149. idx &= dev->mii.reg_num_mask;
  150. addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
  151. smsc95xx_write_reg(dev, MII_ADDR, addr);
  152. if (smsc95xx_phy_wait_not_busy(dev))
  153. devwarn(dev, "Timed out writing MII reg %02X", idx);
  154. mutex_unlock(&dev->phy_mutex);
  155. }
  156. static int smsc95xx_wait_eeprom(struct usbnet *dev)
  157. {
  158. unsigned long start_time = jiffies;
  159. u32 val;
  160. do {
  161. smsc95xx_read_reg(dev, E2P_CMD, &val);
  162. if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
  163. break;
  164. udelay(40);
  165. } while (!time_after(jiffies, start_time + HZ));
  166. if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
  167. devwarn(dev, "EEPROM read operation timeout");
  168. return -EIO;
  169. }
  170. return 0;
  171. }
  172. static int smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
  173. {
  174. unsigned long start_time = jiffies;
  175. u32 val;
  176. do {
  177. smsc95xx_read_reg(dev, E2P_CMD, &val);
  178. if (!(val & E2P_CMD_LOADED_)) {
  179. devwarn(dev, "No EEPROM present");
  180. return -EIO;
  181. }
  182. if (!(val & E2P_CMD_BUSY_))
  183. return 0;
  184. udelay(40);
  185. } while (!time_after(jiffies, start_time + HZ));
  186. devwarn(dev, "EEPROM is busy");
  187. return -EIO;
  188. }
  189. static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  190. u8 *data)
  191. {
  192. u32 val;
  193. int i, ret;
  194. BUG_ON(!dev);
  195. BUG_ON(!data);
  196. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  197. if (ret)
  198. return ret;
  199. for (i = 0; i < length; i++) {
  200. val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
  201. smsc95xx_write_reg(dev, E2P_CMD, val);
  202. ret = smsc95xx_wait_eeprom(dev);
  203. if (ret < 0)
  204. return ret;
  205. smsc95xx_read_reg(dev, E2P_DATA, &val);
  206. data[i] = val & 0xFF;
  207. offset++;
  208. }
  209. return 0;
  210. }
  211. static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  212. u8 *data)
  213. {
  214. u32 val;
  215. int i, ret;
  216. BUG_ON(!dev);
  217. BUG_ON(!data);
  218. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  219. if (ret)
  220. return ret;
  221. /* Issue write/erase enable command */
  222. val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
  223. smsc95xx_write_reg(dev, E2P_CMD, val);
  224. ret = smsc95xx_wait_eeprom(dev);
  225. if (ret < 0)
  226. return ret;
  227. for (i = 0; i < length; i++) {
  228. /* Fill data register */
  229. val = data[i];
  230. smsc95xx_write_reg(dev, E2P_DATA, val);
  231. /* Send "write" command */
  232. val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
  233. smsc95xx_write_reg(dev, E2P_CMD, val);
  234. ret = smsc95xx_wait_eeprom(dev);
  235. if (ret < 0)
  236. return ret;
  237. offset++;
  238. }
  239. return 0;
  240. }
  241. static void smsc95xx_async_cmd_callback(struct urb *urb)
  242. {
  243. struct usb_context *usb_context = urb->context;
  244. struct usbnet *dev = usb_context->dev;
  245. int status = urb->status;
  246. if (status < 0)
  247. devwarn(dev, "async callback failed with %d", status);
  248. kfree(usb_context);
  249. usb_free_urb(urb);
  250. }
  251. static int smsc95xx_write_reg_async(struct usbnet *dev, u16 index, u32 *data)
  252. {
  253. struct usb_context *usb_context;
  254. int status;
  255. struct urb *urb;
  256. const u16 size = 4;
  257. urb = usb_alloc_urb(0, GFP_ATOMIC);
  258. if (!urb) {
  259. devwarn(dev, "Error allocating URB");
  260. return -ENOMEM;
  261. }
  262. usb_context = kmalloc(sizeof(struct usb_context), GFP_ATOMIC);
  263. if (usb_context == NULL) {
  264. devwarn(dev, "Error allocating control msg");
  265. usb_free_urb(urb);
  266. return -ENOMEM;
  267. }
  268. usb_context->req.bRequestType =
  269. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE;
  270. usb_context->req.bRequest = USB_VENDOR_REQUEST_WRITE_REGISTER;
  271. usb_context->req.wValue = 00;
  272. usb_context->req.wIndex = cpu_to_le16(index);
  273. usb_context->req.wLength = cpu_to_le16(size);
  274. usb_fill_control_urb(urb, dev->udev, usb_sndctrlpipe(dev->udev, 0),
  275. (void *)&usb_context->req, data, size,
  276. smsc95xx_async_cmd_callback,
  277. (void *)usb_context);
  278. status = usb_submit_urb(urb, GFP_ATOMIC);
  279. if (status < 0) {
  280. devwarn(dev, "Error submitting control msg, sts=%d", status);
  281. kfree(usb_context);
  282. usb_free_urb(urb);
  283. }
  284. return status;
  285. }
  286. /* returns hash bit number for given MAC address
  287. * example:
  288. * 01 00 5E 00 00 01 -> returns bit number 31 */
  289. static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
  290. {
  291. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  292. }
  293. static void smsc95xx_set_multicast(struct net_device *netdev)
  294. {
  295. struct usbnet *dev = netdev_priv(netdev);
  296. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  297. u32 hash_hi = 0;
  298. u32 hash_lo = 0;
  299. unsigned long flags;
  300. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  301. if (dev->net->flags & IFF_PROMISC) {
  302. if (netif_msg_drv(dev))
  303. devdbg(dev, "promiscuous mode enabled");
  304. pdata->mac_cr |= MAC_CR_PRMS_;
  305. pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  306. } else if (dev->net->flags & IFF_ALLMULTI) {
  307. if (netif_msg_drv(dev))
  308. devdbg(dev, "receive all multicast enabled");
  309. pdata->mac_cr |= MAC_CR_MCPAS_;
  310. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  311. } else if (dev->net->mc_count > 0) {
  312. struct dev_mc_list *mc_list = dev->net->mc_list;
  313. int count = 0;
  314. pdata->mac_cr |= MAC_CR_HPFILT_;
  315. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  316. while (mc_list) {
  317. count++;
  318. if (mc_list->dmi_addrlen == ETH_ALEN) {
  319. u32 bitnum = smsc95xx_hash(mc_list->dmi_addr);
  320. u32 mask = 0x01 << (bitnum & 0x1F);
  321. if (bitnum & 0x20)
  322. hash_hi |= mask;
  323. else
  324. hash_lo |= mask;
  325. } else {
  326. devwarn(dev, "dmi_addrlen != 6");
  327. }
  328. mc_list = mc_list->next;
  329. }
  330. if (count != ((u32)dev->net->mc_count))
  331. devwarn(dev, "mc_count != dev->mc_count");
  332. if (netif_msg_drv(dev))
  333. devdbg(dev, "HASHH=0x%08X, HASHL=0x%08X", hash_hi,
  334. hash_lo);
  335. } else {
  336. if (netif_msg_drv(dev))
  337. devdbg(dev, "receive own packets only");
  338. pdata->mac_cr &=
  339. ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  340. }
  341. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  342. /* Initiate async writes, as we can't wait for completion here */
  343. smsc95xx_write_reg_async(dev, HASHH, &hash_hi);
  344. smsc95xx_write_reg_async(dev, HASHL, &hash_lo);
  345. smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr);
  346. }
  347. static void smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex,
  348. u16 lcladv, u16 rmtadv)
  349. {
  350. u32 flow, afc_cfg = 0;
  351. int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
  352. if (ret < 0) {
  353. devwarn(dev, "error reading AFC_CFG");
  354. return;
  355. }
  356. if (duplex == DUPLEX_FULL) {
  357. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  358. if (cap & FLOW_CTRL_RX)
  359. flow = 0xFFFF0002;
  360. else
  361. flow = 0;
  362. if (cap & FLOW_CTRL_TX)
  363. afc_cfg |= 0xF;
  364. else
  365. afc_cfg &= ~0xF;
  366. if (netif_msg_link(dev))
  367. devdbg(dev, "rx pause %s, tx pause %s",
  368. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  369. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  370. } else {
  371. if (netif_msg_link(dev))
  372. devdbg(dev, "half duplex");
  373. flow = 0;
  374. afc_cfg |= 0xF;
  375. }
  376. smsc95xx_write_reg(dev, FLOW, flow);
  377. smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
  378. }
  379. static int smsc95xx_link_reset(struct usbnet *dev)
  380. {
  381. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  382. struct mii_if_info *mii = &dev->mii;
  383. struct ethtool_cmd ecmd;
  384. unsigned long flags;
  385. u16 lcladv, rmtadv;
  386. u32 intdata;
  387. /* clear interrupt status */
  388. smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
  389. intdata = 0xFFFFFFFF;
  390. smsc95xx_write_reg(dev, INT_STS, intdata);
  391. mii_check_media(mii, 1, 1);
  392. mii_ethtool_gset(&dev->mii, &ecmd);
  393. lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  394. rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  395. if (netif_msg_link(dev))
  396. devdbg(dev, "speed: %d duplex: %d lcladv: %04x rmtadv: %04x",
  397. ecmd.speed, ecmd.duplex, lcladv, rmtadv);
  398. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  399. if (ecmd.duplex != DUPLEX_FULL) {
  400. pdata->mac_cr &= ~MAC_CR_FDPX_;
  401. pdata->mac_cr |= MAC_CR_RCVOWN_;
  402. } else {
  403. pdata->mac_cr &= ~MAC_CR_RCVOWN_;
  404. pdata->mac_cr |= MAC_CR_FDPX_;
  405. }
  406. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  407. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  408. smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  409. return 0;
  410. }
  411. static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
  412. {
  413. u32 intdata;
  414. if (urb->actual_length != 4) {
  415. devwarn(dev, "unexpected urb length %d", urb->actual_length);
  416. return;
  417. }
  418. memcpy(&intdata, urb->transfer_buffer, 4);
  419. le32_to_cpus(&intdata);
  420. if (netif_msg_link(dev))
  421. devdbg(dev, "intdata: 0x%08X", intdata);
  422. if (intdata & INT_ENP_PHY_INT_)
  423. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  424. else
  425. devwarn(dev, "unexpected interrupt, intdata=0x%08X", intdata);
  426. }
  427. /* Enable or disable Tx & Rx checksum offload engines */
  428. static int smsc95xx_set_csums(struct usbnet *dev)
  429. {
  430. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  431. u32 read_buf;
  432. int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
  433. if (ret < 0) {
  434. devwarn(dev, "Failed to read COE_CR: %d", ret);
  435. return ret;
  436. }
  437. if (pdata->use_tx_csum)
  438. read_buf |= Tx_COE_EN_;
  439. else
  440. read_buf &= ~Tx_COE_EN_;
  441. if (pdata->use_rx_csum)
  442. read_buf |= Rx_COE_EN_;
  443. else
  444. read_buf &= ~Rx_COE_EN_;
  445. ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
  446. if (ret < 0) {
  447. devwarn(dev, "Failed to write COE_CR: %d", ret);
  448. return ret;
  449. }
  450. if (netif_msg_hw(dev))
  451. devdbg(dev, "COE_CR = 0x%08x", read_buf);
  452. return 0;
  453. }
  454. static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
  455. {
  456. return MAX_EEPROM_SIZE;
  457. }
  458. static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
  459. struct ethtool_eeprom *ee, u8 *data)
  460. {
  461. struct usbnet *dev = netdev_priv(netdev);
  462. ee->magic = LAN95XX_EEPROM_MAGIC;
  463. return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
  464. }
  465. static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
  466. struct ethtool_eeprom *ee, u8 *data)
  467. {
  468. struct usbnet *dev = netdev_priv(netdev);
  469. if (ee->magic != LAN95XX_EEPROM_MAGIC) {
  470. devwarn(dev, "EEPROM: magic value mismatch, magic = 0x%x",
  471. ee->magic);
  472. return -EINVAL;
  473. }
  474. return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
  475. }
  476. static u32 smsc95xx_ethtool_get_rx_csum(struct net_device *netdev)
  477. {
  478. struct usbnet *dev = netdev_priv(netdev);
  479. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  480. return pdata->use_rx_csum;
  481. }
  482. static int smsc95xx_ethtool_set_rx_csum(struct net_device *netdev, u32 val)
  483. {
  484. struct usbnet *dev = netdev_priv(netdev);
  485. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  486. pdata->use_rx_csum = !!val;
  487. return smsc95xx_set_csums(dev);
  488. }
  489. static u32 smsc95xx_ethtool_get_tx_csum(struct net_device *netdev)
  490. {
  491. struct usbnet *dev = netdev_priv(netdev);
  492. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  493. return pdata->use_tx_csum;
  494. }
  495. static int smsc95xx_ethtool_set_tx_csum(struct net_device *netdev, u32 val)
  496. {
  497. struct usbnet *dev = netdev_priv(netdev);
  498. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  499. pdata->use_tx_csum = !!val;
  500. ethtool_op_set_tx_hw_csum(netdev, pdata->use_tx_csum);
  501. return smsc95xx_set_csums(dev);
  502. }
  503. static struct ethtool_ops smsc95xx_ethtool_ops = {
  504. .get_link = usbnet_get_link,
  505. .nway_reset = usbnet_nway_reset,
  506. .get_drvinfo = usbnet_get_drvinfo,
  507. .get_msglevel = usbnet_get_msglevel,
  508. .set_msglevel = usbnet_set_msglevel,
  509. .get_settings = usbnet_get_settings,
  510. .set_settings = usbnet_set_settings,
  511. .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
  512. .get_eeprom = smsc95xx_ethtool_get_eeprom,
  513. .set_eeprom = smsc95xx_ethtool_set_eeprom,
  514. .get_tx_csum = smsc95xx_ethtool_get_tx_csum,
  515. .set_tx_csum = smsc95xx_ethtool_set_tx_csum,
  516. .get_rx_csum = smsc95xx_ethtool_get_rx_csum,
  517. .set_rx_csum = smsc95xx_ethtool_set_rx_csum,
  518. };
  519. static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  520. {
  521. struct usbnet *dev = netdev_priv(netdev);
  522. if (!netif_running(netdev))
  523. return -EINVAL;
  524. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  525. }
  526. static void smsc95xx_init_mac_address(struct usbnet *dev)
  527. {
  528. /* try reading mac address from EEPROM */
  529. if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  530. dev->net->dev_addr) == 0) {
  531. if (is_valid_ether_addr(dev->net->dev_addr)) {
  532. /* eeprom values are valid so use them */
  533. if (netif_msg_ifup(dev))
  534. devdbg(dev, "MAC address read from EEPROM");
  535. return;
  536. }
  537. }
  538. /* no eeprom, or eeprom values are invalid. generate random MAC */
  539. random_ether_addr(dev->net->dev_addr);
  540. if (netif_msg_ifup(dev))
  541. devdbg(dev, "MAC address set to random_ether_addr");
  542. }
  543. static int smsc95xx_set_mac_address(struct usbnet *dev)
  544. {
  545. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  546. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  547. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  548. int ret;
  549. ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
  550. if (ret < 0) {
  551. devwarn(dev, "Failed to write ADDRL: %d", ret);
  552. return ret;
  553. }
  554. ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
  555. if (ret < 0) {
  556. devwarn(dev, "Failed to write ADDRH: %d", ret);
  557. return ret;
  558. }
  559. return 0;
  560. }
  561. /* starts the TX path */
  562. static void smsc95xx_start_tx_path(struct usbnet *dev)
  563. {
  564. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  565. unsigned long flags;
  566. u32 reg_val;
  567. /* Enable Tx at MAC */
  568. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  569. pdata->mac_cr |= MAC_CR_TXEN_;
  570. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  571. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  572. /* Enable Tx at SCSRs */
  573. reg_val = TX_CFG_ON_;
  574. smsc95xx_write_reg(dev, TX_CFG, reg_val);
  575. }
  576. /* Starts the Receive path */
  577. static void smsc95xx_start_rx_path(struct usbnet *dev)
  578. {
  579. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  580. unsigned long flags;
  581. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  582. pdata->mac_cr |= MAC_CR_RXEN_;
  583. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  584. smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  585. }
  586. static int smsc95xx_phy_initialize(struct usbnet *dev)
  587. {
  588. /* Initialize MII structure */
  589. dev->mii.dev = dev->net;
  590. dev->mii.mdio_read = smsc95xx_mdio_read;
  591. dev->mii.mdio_write = smsc95xx_mdio_write;
  592. dev->mii.phy_id_mask = 0x1f;
  593. dev->mii.reg_num_mask = 0x1f;
  594. dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID;
  595. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  596. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  597. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  598. ADVERTISE_PAUSE_ASYM);
  599. /* read to clear */
  600. smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  601. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  602. PHY_INT_MASK_DEFAULT_);
  603. mii_nway_restart(&dev->mii);
  604. if (netif_msg_ifup(dev))
  605. devdbg(dev, "phy initialised succesfully");
  606. return 0;
  607. }
  608. static int smsc95xx_reset(struct usbnet *dev)
  609. {
  610. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  611. struct net_device *netdev = dev->net;
  612. u32 read_buf, write_buf, burst_cap;
  613. int ret = 0, timeout;
  614. if (netif_msg_ifup(dev))
  615. devdbg(dev, "entering smsc95xx_reset");
  616. write_buf = HW_CFG_LRST_;
  617. ret = smsc95xx_write_reg(dev, HW_CFG, write_buf);
  618. if (ret < 0) {
  619. devwarn(dev, "Failed to write HW_CFG_LRST_ bit in HW_CFG "
  620. "register, ret = %d", ret);
  621. return ret;
  622. }
  623. timeout = 0;
  624. do {
  625. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  626. if (ret < 0) {
  627. devwarn(dev, "Failed to read HW_CFG: %d", ret);
  628. return ret;
  629. }
  630. msleep(10);
  631. timeout++;
  632. } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
  633. if (timeout >= 100) {
  634. devwarn(dev, "timeout waiting for completion of Lite Reset");
  635. return ret;
  636. }
  637. write_buf = PM_CTL_PHY_RST_;
  638. ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf);
  639. if (ret < 0) {
  640. devwarn(dev, "Failed to write PM_CTRL: %d", ret);
  641. return ret;
  642. }
  643. timeout = 0;
  644. do {
  645. ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
  646. if (ret < 0) {
  647. devwarn(dev, "Failed to read PM_CTRL: %d", ret);
  648. return ret;
  649. }
  650. msleep(10);
  651. timeout++;
  652. } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
  653. if (timeout >= 100) {
  654. devwarn(dev, "timeout waiting for PHY Reset");
  655. return ret;
  656. }
  657. smsc95xx_init_mac_address(dev);
  658. ret = smsc95xx_set_mac_address(dev);
  659. if (ret < 0)
  660. return ret;
  661. if (netif_msg_ifup(dev))
  662. devdbg(dev, "MAC Address: %pM", dev->net->dev_addr);
  663. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  664. if (ret < 0) {
  665. devwarn(dev, "Failed to read HW_CFG: %d", ret);
  666. return ret;
  667. }
  668. if (netif_msg_ifup(dev))
  669. devdbg(dev, "Read Value from HW_CFG : 0x%08x", read_buf);
  670. read_buf |= HW_CFG_BIR_;
  671. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  672. if (ret < 0) {
  673. devwarn(dev, "Failed to write HW_CFG_BIR_ bit in HW_CFG "
  674. "register, ret = %d", ret);
  675. return ret;
  676. }
  677. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  678. if (ret < 0) {
  679. devwarn(dev, "Failed to read HW_CFG: %d", ret);
  680. return ret;
  681. }
  682. if (netif_msg_ifup(dev))
  683. devdbg(dev, "Read Value from HW_CFG after writing "
  684. "HW_CFG_BIR_: 0x%08x", read_buf);
  685. if (!turbo_mode) {
  686. burst_cap = 0;
  687. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  688. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  689. burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  690. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  691. } else {
  692. burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  693. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  694. }
  695. if (netif_msg_ifup(dev))
  696. devdbg(dev, "rx_urb_size=%ld", (ulong)dev->rx_urb_size);
  697. ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
  698. if (ret < 0) {
  699. devwarn(dev, "Failed to write BURST_CAP: %d", ret);
  700. return ret;
  701. }
  702. ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
  703. if (ret < 0) {
  704. devwarn(dev, "Failed to read BURST_CAP: %d", ret);
  705. return ret;
  706. }
  707. if (netif_msg_ifup(dev))
  708. devdbg(dev, "Read Value from BURST_CAP after writing: 0x%08x",
  709. read_buf);
  710. read_buf = DEFAULT_BULK_IN_DELAY;
  711. ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf);
  712. if (ret < 0) {
  713. devwarn(dev, "ret = %d", ret);
  714. return ret;
  715. }
  716. ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
  717. if (ret < 0) {
  718. devwarn(dev, "Failed to read BULK_IN_DLY: %d", ret);
  719. return ret;
  720. }
  721. if (netif_msg_ifup(dev))
  722. devdbg(dev, "Read Value from BULK_IN_DLY after writing: "
  723. "0x%08x", read_buf);
  724. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  725. if (ret < 0) {
  726. devwarn(dev, "Failed to read HW_CFG: %d", ret);
  727. return ret;
  728. }
  729. if (netif_msg_ifup(dev))
  730. devdbg(dev, "Read Value from HW_CFG: 0x%08x", read_buf);
  731. if (turbo_mode)
  732. read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
  733. read_buf &= ~HW_CFG_RXDOFF_;
  734. /* set Rx data offset=2, Make IP header aligns on word boundary. */
  735. read_buf |= NET_IP_ALIGN << 9;
  736. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  737. if (ret < 0) {
  738. devwarn(dev, "Failed to write HW_CFG register, ret=%d", ret);
  739. return ret;
  740. }
  741. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  742. if (ret < 0) {
  743. devwarn(dev, "Failed to read HW_CFG: %d", ret);
  744. return ret;
  745. }
  746. if (netif_msg_ifup(dev))
  747. devdbg(dev, "Read Value from HW_CFG after writing: 0x%08x",
  748. read_buf);
  749. write_buf = 0xFFFFFFFF;
  750. ret = smsc95xx_write_reg(dev, INT_STS, write_buf);
  751. if (ret < 0) {
  752. devwarn(dev, "Failed to write INT_STS register, ret=%d", ret);
  753. return ret;
  754. }
  755. ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
  756. if (ret < 0) {
  757. devwarn(dev, "Failed to read ID_REV: %d", ret);
  758. return ret;
  759. }
  760. if (netif_msg_ifup(dev))
  761. devdbg(dev, "ID_REV = 0x%08x", read_buf);
  762. /* Init Tx */
  763. write_buf = 0;
  764. ret = smsc95xx_write_reg(dev, FLOW, write_buf);
  765. if (ret < 0) {
  766. devwarn(dev, "Failed to write FLOW: %d", ret);
  767. return ret;
  768. }
  769. read_buf = AFC_CFG_DEFAULT;
  770. ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf);
  771. if (ret < 0) {
  772. devwarn(dev, "Failed to write AFC_CFG: %d", ret);
  773. return ret;
  774. }
  775. /* Don't need mac_cr_lock during initialisation */
  776. ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr);
  777. if (ret < 0) {
  778. devwarn(dev, "Failed to read MAC_CR: %d", ret);
  779. return ret;
  780. }
  781. /* Init Rx */
  782. /* Set Vlan */
  783. write_buf = (u32)ETH_P_8021Q;
  784. ret = smsc95xx_write_reg(dev, VLAN1, write_buf);
  785. if (ret < 0) {
  786. devwarn(dev, "Failed to write VAN1: %d", ret);
  787. return ret;
  788. }
  789. /* Enable or disable checksum offload engines */
  790. ethtool_op_set_tx_hw_csum(netdev, pdata->use_tx_csum);
  791. ret = smsc95xx_set_csums(dev);
  792. if (ret < 0) {
  793. devwarn(dev, "Failed to set csum offload: %d", ret);
  794. return ret;
  795. }
  796. smsc95xx_set_multicast(dev->net);
  797. if (smsc95xx_phy_initialize(dev) < 0)
  798. return -EIO;
  799. ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
  800. if (ret < 0) {
  801. devwarn(dev, "Failed to read INT_EP_CTL: %d", ret);
  802. return ret;
  803. }
  804. /* enable PHY interrupts */
  805. read_buf |= INT_EP_CTL_PHY_INT_;
  806. ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
  807. if (ret < 0) {
  808. devwarn(dev, "Failed to write INT_EP_CTL: %d", ret);
  809. return ret;
  810. }
  811. smsc95xx_start_tx_path(dev);
  812. smsc95xx_start_rx_path(dev);
  813. if (netif_msg_ifup(dev))
  814. devdbg(dev, "smsc95xx_reset, return 0");
  815. return 0;
  816. }
  817. static const struct net_device_ops smsc95xx_netdev_ops = {
  818. .ndo_open = usbnet_open,
  819. .ndo_stop = usbnet_stop,
  820. .ndo_start_xmit = usbnet_start_xmit,
  821. .ndo_tx_timeout = usbnet_tx_timeout,
  822. .ndo_change_mtu = usbnet_change_mtu,
  823. .ndo_set_mac_address = eth_mac_addr,
  824. .ndo_validate_addr = eth_validate_addr,
  825. .ndo_do_ioctl = smsc95xx_ioctl,
  826. .ndo_set_multicast_list = smsc95xx_set_multicast,
  827. };
  828. static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
  829. {
  830. struct smsc95xx_priv *pdata = NULL;
  831. int ret;
  832. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  833. ret = usbnet_get_endpoints(dev, intf);
  834. if (ret < 0) {
  835. devwarn(dev, "usbnet_get_endpoints failed: %d", ret);
  836. return ret;
  837. }
  838. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv),
  839. GFP_KERNEL);
  840. pdata = (struct smsc95xx_priv *)(dev->data[0]);
  841. if (!pdata) {
  842. devwarn(dev, "Unable to allocate struct smsc95xx_priv");
  843. return -ENOMEM;
  844. }
  845. spin_lock_init(&pdata->mac_cr_lock);
  846. pdata->use_tx_csum = DEFAULT_TX_CSUM_ENABLE;
  847. pdata->use_rx_csum = DEFAULT_RX_CSUM_ENABLE;
  848. /* Init all registers */
  849. ret = smsc95xx_reset(dev);
  850. dev->net->netdev_ops = &smsc95xx_netdev_ops;
  851. dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
  852. dev->net->flags |= IFF_MULTICAST;
  853. dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD;
  854. return 0;
  855. }
  856. static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  857. {
  858. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  859. if (pdata) {
  860. if (netif_msg_ifdown(dev))
  861. devdbg(dev, "free pdata");
  862. kfree(pdata);
  863. pdata = NULL;
  864. dev->data[0] = 0;
  865. }
  866. }
  867. static void smsc95xx_rx_csum_offload(struct sk_buff *skb)
  868. {
  869. skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2);
  870. skb->ip_summed = CHECKSUM_COMPLETE;
  871. skb_trim(skb, skb->len - 2);
  872. }
  873. static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  874. {
  875. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  876. while (skb->len > 0) {
  877. u32 header, align_count;
  878. struct sk_buff *ax_skb;
  879. unsigned char *packet;
  880. u16 size;
  881. memcpy(&header, skb->data, sizeof(header));
  882. le32_to_cpus(&header);
  883. skb_pull(skb, 4 + NET_IP_ALIGN);
  884. packet = skb->data;
  885. /* get the packet length */
  886. size = (u16)((header & RX_STS_FL_) >> 16);
  887. align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4;
  888. if (unlikely(header & RX_STS_ES_)) {
  889. if (netif_msg_rx_err(dev))
  890. devdbg(dev, "Error header=0x%08x", header);
  891. dev->stats.rx_errors++;
  892. dev->stats.rx_dropped++;
  893. if (header & RX_STS_CRC_) {
  894. dev->stats.rx_crc_errors++;
  895. } else {
  896. if (header & (RX_STS_TL_ | RX_STS_RF_))
  897. dev->stats.rx_frame_errors++;
  898. if ((header & RX_STS_LE_) &&
  899. (!(header & RX_STS_FT_)))
  900. dev->stats.rx_length_errors++;
  901. }
  902. } else {
  903. /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
  904. if (unlikely(size > (ETH_FRAME_LEN + 12))) {
  905. if (netif_msg_rx_err(dev))
  906. devdbg(dev, "size err header=0x%08x",
  907. header);
  908. return 0;
  909. }
  910. /* last frame in this batch */
  911. if (skb->len == size) {
  912. if (pdata->use_rx_csum)
  913. smsc95xx_rx_csum_offload(skb);
  914. skb->truesize = size + sizeof(struct sk_buff);
  915. return 1;
  916. }
  917. ax_skb = skb_clone(skb, GFP_ATOMIC);
  918. if (unlikely(!ax_skb)) {
  919. devwarn(dev, "Error allocating skb");
  920. return 0;
  921. }
  922. ax_skb->len = size;
  923. ax_skb->data = packet;
  924. skb_set_tail_pointer(ax_skb, size);
  925. if (pdata->use_rx_csum)
  926. smsc95xx_rx_csum_offload(ax_skb);
  927. ax_skb->truesize = size + sizeof(struct sk_buff);
  928. usbnet_skb_return(dev, ax_skb);
  929. }
  930. skb_pull(skb, size);
  931. /* padding bytes before the next frame starts */
  932. if (skb->len)
  933. skb_pull(skb, align_count);
  934. }
  935. if (unlikely(skb->len < 0)) {
  936. devwarn(dev, "invalid rx length<0 %d", skb->len);
  937. return 0;
  938. }
  939. return 1;
  940. }
  941. static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb)
  942. {
  943. int len = skb->data - skb->head;
  944. u16 high_16 = (u16)(skb->csum_offset + skb->csum_start - len);
  945. u16 low_16 = (u16)(skb->csum_start - len);
  946. return (high_16 << 16) | low_16;
  947. }
  948. static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
  949. struct sk_buff *skb, gfp_t flags)
  950. {
  951. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  952. bool csum = pdata->use_tx_csum && (skb->ip_summed == CHECKSUM_PARTIAL);
  953. int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD;
  954. u32 tx_cmd_a, tx_cmd_b;
  955. /* We do not advertise SG, so skbs should be already linearized */
  956. BUG_ON(skb_shinfo(skb)->nr_frags);
  957. if (skb_headroom(skb) < overhead) {
  958. struct sk_buff *skb2 = skb_copy_expand(skb,
  959. overhead, 0, flags);
  960. dev_kfree_skb_any(skb);
  961. skb = skb2;
  962. if (!skb)
  963. return NULL;
  964. }
  965. if (csum) {
  966. u32 csum_preamble = smsc95xx_calc_csum_preamble(skb);
  967. skb_push(skb, 4);
  968. memcpy(skb->data, &csum_preamble, 4);
  969. }
  970. skb_push(skb, 4);
  971. tx_cmd_b = (u32)(skb->len - 4);
  972. if (csum)
  973. tx_cmd_b |= TX_CMD_B_CSUM_ENABLE;
  974. cpu_to_le32s(&tx_cmd_b);
  975. memcpy(skb->data, &tx_cmd_b, 4);
  976. skb_push(skb, 4);
  977. tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ |
  978. TX_CMD_A_LAST_SEG_;
  979. cpu_to_le32s(&tx_cmd_a);
  980. memcpy(skb->data, &tx_cmd_a, 4);
  981. return skb;
  982. }
  983. static const struct driver_info smsc95xx_info = {
  984. .description = "smsc95xx USB 2.0 Ethernet",
  985. .bind = smsc95xx_bind,
  986. .unbind = smsc95xx_unbind,
  987. .link_reset = smsc95xx_link_reset,
  988. .reset = smsc95xx_reset,
  989. .rx_fixup = smsc95xx_rx_fixup,
  990. .tx_fixup = smsc95xx_tx_fixup,
  991. .status = smsc95xx_status,
  992. .flags = FLAG_ETHER,
  993. };
  994. static const struct usb_device_id products[] = {
  995. {
  996. /* SMSC9500 USB Ethernet Device */
  997. USB_DEVICE(0x0424, 0x9500),
  998. .driver_info = (unsigned long) &smsc95xx_info,
  999. },
  1000. { }, /* END */
  1001. };
  1002. MODULE_DEVICE_TABLE(usb, products);
  1003. static struct usb_driver smsc95xx_driver = {
  1004. .name = "smsc95xx",
  1005. .id_table = products,
  1006. .probe = usbnet_probe,
  1007. .suspend = usbnet_suspend,
  1008. .resume = usbnet_resume,
  1009. .disconnect = usbnet_disconnect,
  1010. };
  1011. static int __init smsc95xx_init(void)
  1012. {
  1013. return usb_register(&smsc95xx_driver);
  1014. }
  1015. module_init(smsc95xx_init);
  1016. static void __exit smsc95xx_exit(void)
  1017. {
  1018. usb_deregister(&smsc95xx_driver);
  1019. }
  1020. module_exit(smsc95xx_exit);
  1021. MODULE_AUTHOR("Nancy Lin");
  1022. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@smsc.com>");
  1023. MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices");
  1024. MODULE_LICENSE("GPL");