tsi108_eth.c 47 KB

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  1. /*******************************************************************************
  2. Copyright(c) 2006 Tundra Semiconductor Corporation.
  3. This program is free software; you can redistribute it and/or modify it
  4. under the terms of the GNU General Public License as published by the Free
  5. Software Foundation; either version 2 of the License, or (at your option)
  6. any later version.
  7. This program is distributed in the hope that it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc., 59
  13. Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  14. *******************************************************************************/
  15. /* This driver is based on the driver code originally developed
  16. * for the Intel IOC80314 (ForestLake) Gigabit Ethernet by
  17. * scott.wood@timesys.com * Copyright (C) 2003 TimeSys Corporation
  18. *
  19. * Currently changes from original version are:
  20. * - porting to Tsi108-based platform and kernel 2.6 (kong.lai@tundra.com)
  21. * - modifications to handle two ports independently and support for
  22. * additional PHY devices (alexandre.bounine@tundra.com)
  23. * - Get hardware information from platform device. (tie-fei.zang@freescale.com)
  24. *
  25. */
  26. #include <linux/module.h>
  27. #include <linux/types.h>
  28. #include <linux/init.h>
  29. #include <linux/net.h>
  30. #include <linux/netdevice.h>
  31. #include <linux/etherdevice.h>
  32. #include <linux/ethtool.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/slab.h>
  35. #include <linux/spinlock.h>
  36. #include <linux/delay.h>
  37. #include <linux/crc32.h>
  38. #include <linux/mii.h>
  39. #include <linux/device.h>
  40. #include <linux/pci.h>
  41. #include <linux/rtnetlink.h>
  42. #include <linux/timer.h>
  43. #include <linux/platform_device.h>
  44. #include <asm/system.h>
  45. #include <asm/io.h>
  46. #include <asm/tsi108.h>
  47. #include "tsi108_eth.h"
  48. #define MII_READ_DELAY 10000 /* max link wait time in msec */
  49. #define TSI108_RXRING_LEN 256
  50. /* NOTE: The driver currently does not support receiving packets
  51. * larger than the buffer size, so don't decrease this (unless you
  52. * want to add such support).
  53. */
  54. #define TSI108_RXBUF_SIZE 1536
  55. #define TSI108_TXRING_LEN 256
  56. #define TSI108_TX_INT_FREQ 64
  57. /* Check the phy status every half a second. */
  58. #define CHECK_PHY_INTERVAL (HZ/2)
  59. static int tsi108_init_one(struct platform_device *pdev);
  60. static int tsi108_ether_remove(struct platform_device *pdev);
  61. struct tsi108_prv_data {
  62. void __iomem *regs; /* Base of normal regs */
  63. void __iomem *phyregs; /* Base of register bank used for PHY access */
  64. struct net_device *dev;
  65. struct napi_struct napi;
  66. unsigned int phy; /* Index of PHY for this interface */
  67. unsigned int irq_num;
  68. unsigned int id;
  69. unsigned int phy_type;
  70. struct timer_list timer;/* Timer that triggers the check phy function */
  71. unsigned int rxtail; /* Next entry in rxring to read */
  72. unsigned int rxhead; /* Next entry in rxring to give a new buffer */
  73. unsigned int rxfree; /* Number of free, allocated RX buffers */
  74. unsigned int rxpending; /* Non-zero if there are still descriptors
  75. * to be processed from a previous descriptor
  76. * interrupt condition that has been cleared */
  77. unsigned int txtail; /* Next TX descriptor to check status on */
  78. unsigned int txhead; /* Next TX descriptor to use */
  79. /* Number of free TX descriptors. This could be calculated from
  80. * rxhead and rxtail if one descriptor were left unused to disambiguate
  81. * full and empty conditions, but it's simpler to just keep track
  82. * explicitly. */
  83. unsigned int txfree;
  84. unsigned int phy_ok; /* The PHY is currently powered on. */
  85. /* PHY status (duplex is 1 for half, 2 for full,
  86. * so that the default 0 indicates that neither has
  87. * yet been configured). */
  88. unsigned int link_up;
  89. unsigned int speed;
  90. unsigned int duplex;
  91. tx_desc *txring;
  92. rx_desc *rxring;
  93. struct sk_buff *txskbs[TSI108_TXRING_LEN];
  94. struct sk_buff *rxskbs[TSI108_RXRING_LEN];
  95. dma_addr_t txdma, rxdma;
  96. /* txlock nests in misclock and phy_lock */
  97. spinlock_t txlock, misclock;
  98. /* stats is used to hold the upper bits of each hardware counter,
  99. * and tmpstats is used to hold the full values for returning
  100. * to the caller of get_stats(). They must be separate in case
  101. * an overflow interrupt occurs before the stats are consumed.
  102. */
  103. struct net_device_stats stats;
  104. struct net_device_stats tmpstats;
  105. /* These stats are kept separate in hardware, thus require individual
  106. * fields for handling carry. They are combined in get_stats.
  107. */
  108. unsigned long rx_fcs; /* Add to rx_frame_errors */
  109. unsigned long rx_short_fcs; /* Add to rx_frame_errors */
  110. unsigned long rx_long_fcs; /* Add to rx_frame_errors */
  111. unsigned long rx_underruns; /* Add to rx_length_errors */
  112. unsigned long rx_overruns; /* Add to rx_length_errors */
  113. unsigned long tx_coll_abort; /* Add to tx_aborted_errors/collisions */
  114. unsigned long tx_pause_drop; /* Add to tx_aborted_errors */
  115. unsigned long mc_hash[16];
  116. u32 msg_enable; /* debug message level */
  117. struct mii_if_info mii_if;
  118. unsigned int init_media;
  119. };
  120. /* Structure for a device driver */
  121. static struct platform_driver tsi_eth_driver = {
  122. .probe = tsi108_init_one,
  123. .remove = tsi108_ether_remove,
  124. .driver = {
  125. .name = "tsi-ethernet",
  126. .owner = THIS_MODULE,
  127. },
  128. };
  129. static void tsi108_timed_checker(unsigned long dev_ptr);
  130. static void dump_eth_one(struct net_device *dev)
  131. {
  132. struct tsi108_prv_data *data = netdev_priv(dev);
  133. printk("Dumping %s...\n", dev->name);
  134. printk("intstat %x intmask %x phy_ok %d"
  135. " link %d speed %d duplex %d\n",
  136. TSI_READ(TSI108_EC_INTSTAT),
  137. TSI_READ(TSI108_EC_INTMASK), data->phy_ok,
  138. data->link_up, data->speed, data->duplex);
  139. printk("TX: head %d, tail %d, free %d, stat %x, estat %x, err %x\n",
  140. data->txhead, data->txtail, data->txfree,
  141. TSI_READ(TSI108_EC_TXSTAT),
  142. TSI_READ(TSI108_EC_TXESTAT),
  143. TSI_READ(TSI108_EC_TXERR));
  144. printk("RX: head %d, tail %d, free %d, stat %x,"
  145. " estat %x, err %x, pending %d\n\n",
  146. data->rxhead, data->rxtail, data->rxfree,
  147. TSI_READ(TSI108_EC_RXSTAT),
  148. TSI_READ(TSI108_EC_RXESTAT),
  149. TSI_READ(TSI108_EC_RXERR), data->rxpending);
  150. }
  151. /* Synchronization is needed between the thread and up/down events.
  152. * Note that the PHY is accessed through the same registers for both
  153. * interfaces, so this can't be made interface-specific.
  154. */
  155. static DEFINE_SPINLOCK(phy_lock);
  156. static int tsi108_read_mii(struct tsi108_prv_data *data, int reg)
  157. {
  158. unsigned i;
  159. TSI_WRITE_PHY(TSI108_MAC_MII_ADDR,
  160. (data->phy << TSI108_MAC_MII_ADDR_PHY) |
  161. (reg << TSI108_MAC_MII_ADDR_REG));
  162. TSI_WRITE_PHY(TSI108_MAC_MII_CMD, 0);
  163. TSI_WRITE_PHY(TSI108_MAC_MII_CMD, TSI108_MAC_MII_CMD_READ);
  164. for (i = 0; i < 100; i++) {
  165. if (!(TSI_READ_PHY(TSI108_MAC_MII_IND) &
  166. (TSI108_MAC_MII_IND_NOTVALID | TSI108_MAC_MII_IND_BUSY)))
  167. break;
  168. udelay(10);
  169. }
  170. if (i == 100)
  171. return 0xffff;
  172. else
  173. return (TSI_READ_PHY(TSI108_MAC_MII_DATAIN));
  174. }
  175. static void tsi108_write_mii(struct tsi108_prv_data *data,
  176. int reg, u16 val)
  177. {
  178. unsigned i = 100;
  179. TSI_WRITE_PHY(TSI108_MAC_MII_ADDR,
  180. (data->phy << TSI108_MAC_MII_ADDR_PHY) |
  181. (reg << TSI108_MAC_MII_ADDR_REG));
  182. TSI_WRITE_PHY(TSI108_MAC_MII_DATAOUT, val);
  183. while (i--) {
  184. if(!(TSI_READ_PHY(TSI108_MAC_MII_IND) &
  185. TSI108_MAC_MII_IND_BUSY))
  186. break;
  187. udelay(10);
  188. }
  189. }
  190. static int tsi108_mdio_read(struct net_device *dev, int addr, int reg)
  191. {
  192. struct tsi108_prv_data *data = netdev_priv(dev);
  193. return tsi108_read_mii(data, reg);
  194. }
  195. static void tsi108_mdio_write(struct net_device *dev, int addr, int reg, int val)
  196. {
  197. struct tsi108_prv_data *data = netdev_priv(dev);
  198. tsi108_write_mii(data, reg, val);
  199. }
  200. static inline void tsi108_write_tbi(struct tsi108_prv_data *data,
  201. int reg, u16 val)
  202. {
  203. unsigned i = 1000;
  204. TSI_WRITE(TSI108_MAC_MII_ADDR,
  205. (0x1e << TSI108_MAC_MII_ADDR_PHY)
  206. | (reg << TSI108_MAC_MII_ADDR_REG));
  207. TSI_WRITE(TSI108_MAC_MII_DATAOUT, val);
  208. while(i--) {
  209. if(!(TSI_READ(TSI108_MAC_MII_IND) & TSI108_MAC_MII_IND_BUSY))
  210. return;
  211. udelay(10);
  212. }
  213. printk(KERN_ERR "%s function time out \n", __func__);
  214. }
  215. static int mii_speed(struct mii_if_info *mii)
  216. {
  217. int advert, lpa, val, media;
  218. int lpa2 = 0;
  219. int speed;
  220. if (!mii_link_ok(mii))
  221. return 0;
  222. val = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_BMSR);
  223. if ((val & BMSR_ANEGCOMPLETE) == 0)
  224. return 0;
  225. advert = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_ADVERTISE);
  226. lpa = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_LPA);
  227. media = mii_nway_result(advert & lpa);
  228. if (mii->supports_gmii)
  229. lpa2 = mii->mdio_read(mii->dev, mii->phy_id, MII_STAT1000);
  230. speed = lpa2 & (LPA_1000FULL | LPA_1000HALF) ? 1000 :
  231. (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) ? 100 : 10);
  232. return speed;
  233. }
  234. static void tsi108_check_phy(struct net_device *dev)
  235. {
  236. struct tsi108_prv_data *data = netdev_priv(dev);
  237. u32 mac_cfg2_reg, portctrl_reg;
  238. u32 duplex;
  239. u32 speed;
  240. unsigned long flags;
  241. spin_lock_irqsave(&phy_lock, flags);
  242. if (!data->phy_ok)
  243. goto out;
  244. duplex = mii_check_media(&data->mii_if, netif_msg_link(data), data->init_media);
  245. data->init_media = 0;
  246. if (netif_carrier_ok(dev)) {
  247. speed = mii_speed(&data->mii_if);
  248. if ((speed != data->speed) || duplex) {
  249. mac_cfg2_reg = TSI_READ(TSI108_MAC_CFG2);
  250. portctrl_reg = TSI_READ(TSI108_EC_PORTCTRL);
  251. mac_cfg2_reg &= ~TSI108_MAC_CFG2_IFACE_MASK;
  252. if (speed == 1000) {
  253. mac_cfg2_reg |= TSI108_MAC_CFG2_GIG;
  254. portctrl_reg &= ~TSI108_EC_PORTCTRL_NOGIG;
  255. } else {
  256. mac_cfg2_reg |= TSI108_MAC_CFG2_NOGIG;
  257. portctrl_reg |= TSI108_EC_PORTCTRL_NOGIG;
  258. }
  259. data->speed = speed;
  260. if (data->mii_if.full_duplex) {
  261. mac_cfg2_reg |= TSI108_MAC_CFG2_FULLDUPLEX;
  262. portctrl_reg &= ~TSI108_EC_PORTCTRL_HALFDUPLEX;
  263. data->duplex = 2;
  264. } else {
  265. mac_cfg2_reg &= ~TSI108_MAC_CFG2_FULLDUPLEX;
  266. portctrl_reg |= TSI108_EC_PORTCTRL_HALFDUPLEX;
  267. data->duplex = 1;
  268. }
  269. TSI_WRITE(TSI108_MAC_CFG2, mac_cfg2_reg);
  270. TSI_WRITE(TSI108_EC_PORTCTRL, portctrl_reg);
  271. }
  272. if (data->link_up == 0) {
  273. /* The manual says it can take 3-4 usecs for the speed change
  274. * to take effect.
  275. */
  276. udelay(5);
  277. spin_lock(&data->txlock);
  278. if (is_valid_ether_addr(dev->dev_addr) && data->txfree)
  279. netif_wake_queue(dev);
  280. data->link_up = 1;
  281. spin_unlock(&data->txlock);
  282. }
  283. } else {
  284. if (data->link_up == 1) {
  285. netif_stop_queue(dev);
  286. data->link_up = 0;
  287. printk(KERN_NOTICE "%s : link is down\n", dev->name);
  288. }
  289. goto out;
  290. }
  291. out:
  292. spin_unlock_irqrestore(&phy_lock, flags);
  293. }
  294. static inline void
  295. tsi108_stat_carry_one(int carry, int carry_bit, int carry_shift,
  296. unsigned long *upper)
  297. {
  298. if (carry & carry_bit)
  299. *upper += carry_shift;
  300. }
  301. static void tsi108_stat_carry(struct net_device *dev)
  302. {
  303. struct tsi108_prv_data *data = netdev_priv(dev);
  304. u32 carry1, carry2;
  305. spin_lock_irq(&data->misclock);
  306. carry1 = TSI_READ(TSI108_STAT_CARRY1);
  307. carry2 = TSI_READ(TSI108_STAT_CARRY2);
  308. TSI_WRITE(TSI108_STAT_CARRY1, carry1);
  309. TSI_WRITE(TSI108_STAT_CARRY2, carry2);
  310. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXBYTES,
  311. TSI108_STAT_RXBYTES_CARRY, &data->stats.rx_bytes);
  312. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXPKTS,
  313. TSI108_STAT_RXPKTS_CARRY,
  314. &data->stats.rx_packets);
  315. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXFCS,
  316. TSI108_STAT_RXFCS_CARRY, &data->rx_fcs);
  317. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXMCAST,
  318. TSI108_STAT_RXMCAST_CARRY,
  319. &data->stats.multicast);
  320. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXALIGN,
  321. TSI108_STAT_RXALIGN_CARRY,
  322. &data->stats.rx_frame_errors);
  323. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXLENGTH,
  324. TSI108_STAT_RXLENGTH_CARRY,
  325. &data->stats.rx_length_errors);
  326. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXRUNT,
  327. TSI108_STAT_RXRUNT_CARRY, &data->rx_underruns);
  328. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXJUMBO,
  329. TSI108_STAT_RXJUMBO_CARRY, &data->rx_overruns);
  330. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXFRAG,
  331. TSI108_STAT_RXFRAG_CARRY, &data->rx_short_fcs);
  332. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXJABBER,
  333. TSI108_STAT_RXJABBER_CARRY, &data->rx_long_fcs);
  334. tsi108_stat_carry_one(carry1, TSI108_STAT_CARRY1_RXDROP,
  335. TSI108_STAT_RXDROP_CARRY,
  336. &data->stats.rx_missed_errors);
  337. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXBYTES,
  338. TSI108_STAT_TXBYTES_CARRY, &data->stats.tx_bytes);
  339. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXPKTS,
  340. TSI108_STAT_TXPKTS_CARRY,
  341. &data->stats.tx_packets);
  342. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXEXDEF,
  343. TSI108_STAT_TXEXDEF_CARRY,
  344. &data->stats.tx_aborted_errors);
  345. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXEXCOL,
  346. TSI108_STAT_TXEXCOL_CARRY, &data->tx_coll_abort);
  347. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXTCOL,
  348. TSI108_STAT_TXTCOL_CARRY,
  349. &data->stats.collisions);
  350. tsi108_stat_carry_one(carry2, TSI108_STAT_CARRY2_TXPAUSE,
  351. TSI108_STAT_TXPAUSEDROP_CARRY,
  352. &data->tx_pause_drop);
  353. spin_unlock_irq(&data->misclock);
  354. }
  355. /* Read a stat counter atomically with respect to carries.
  356. * data->misclock must be held.
  357. */
  358. static inline unsigned long
  359. tsi108_read_stat(struct tsi108_prv_data * data, int reg, int carry_bit,
  360. int carry_shift, unsigned long *upper)
  361. {
  362. int carryreg;
  363. unsigned long val;
  364. if (reg < 0xb0)
  365. carryreg = TSI108_STAT_CARRY1;
  366. else
  367. carryreg = TSI108_STAT_CARRY2;
  368. again:
  369. val = TSI_READ(reg) | *upper;
  370. /* Check to see if it overflowed, but the interrupt hasn't
  371. * been serviced yet. If so, handle the carry here, and
  372. * try again.
  373. */
  374. if (unlikely(TSI_READ(carryreg) & carry_bit)) {
  375. *upper += carry_shift;
  376. TSI_WRITE(carryreg, carry_bit);
  377. goto again;
  378. }
  379. return val;
  380. }
  381. static struct net_device_stats *tsi108_get_stats(struct net_device *dev)
  382. {
  383. unsigned long excol;
  384. struct tsi108_prv_data *data = netdev_priv(dev);
  385. spin_lock_irq(&data->misclock);
  386. data->tmpstats.rx_packets =
  387. tsi108_read_stat(data, TSI108_STAT_RXPKTS,
  388. TSI108_STAT_CARRY1_RXPKTS,
  389. TSI108_STAT_RXPKTS_CARRY, &data->stats.rx_packets);
  390. data->tmpstats.tx_packets =
  391. tsi108_read_stat(data, TSI108_STAT_TXPKTS,
  392. TSI108_STAT_CARRY2_TXPKTS,
  393. TSI108_STAT_TXPKTS_CARRY, &data->stats.tx_packets);
  394. data->tmpstats.rx_bytes =
  395. tsi108_read_stat(data, TSI108_STAT_RXBYTES,
  396. TSI108_STAT_CARRY1_RXBYTES,
  397. TSI108_STAT_RXBYTES_CARRY, &data->stats.rx_bytes);
  398. data->tmpstats.tx_bytes =
  399. tsi108_read_stat(data, TSI108_STAT_TXBYTES,
  400. TSI108_STAT_CARRY2_TXBYTES,
  401. TSI108_STAT_TXBYTES_CARRY, &data->stats.tx_bytes);
  402. data->tmpstats.multicast =
  403. tsi108_read_stat(data, TSI108_STAT_RXMCAST,
  404. TSI108_STAT_CARRY1_RXMCAST,
  405. TSI108_STAT_RXMCAST_CARRY, &data->stats.multicast);
  406. excol = tsi108_read_stat(data, TSI108_STAT_TXEXCOL,
  407. TSI108_STAT_CARRY2_TXEXCOL,
  408. TSI108_STAT_TXEXCOL_CARRY,
  409. &data->tx_coll_abort);
  410. data->tmpstats.collisions =
  411. tsi108_read_stat(data, TSI108_STAT_TXTCOL,
  412. TSI108_STAT_CARRY2_TXTCOL,
  413. TSI108_STAT_TXTCOL_CARRY, &data->stats.collisions);
  414. data->tmpstats.collisions += excol;
  415. data->tmpstats.rx_length_errors =
  416. tsi108_read_stat(data, TSI108_STAT_RXLENGTH,
  417. TSI108_STAT_CARRY1_RXLENGTH,
  418. TSI108_STAT_RXLENGTH_CARRY,
  419. &data->stats.rx_length_errors);
  420. data->tmpstats.rx_length_errors +=
  421. tsi108_read_stat(data, TSI108_STAT_RXRUNT,
  422. TSI108_STAT_CARRY1_RXRUNT,
  423. TSI108_STAT_RXRUNT_CARRY, &data->rx_underruns);
  424. data->tmpstats.rx_length_errors +=
  425. tsi108_read_stat(data, TSI108_STAT_RXJUMBO,
  426. TSI108_STAT_CARRY1_RXJUMBO,
  427. TSI108_STAT_RXJUMBO_CARRY, &data->rx_overruns);
  428. data->tmpstats.rx_frame_errors =
  429. tsi108_read_stat(data, TSI108_STAT_RXALIGN,
  430. TSI108_STAT_CARRY1_RXALIGN,
  431. TSI108_STAT_RXALIGN_CARRY,
  432. &data->stats.rx_frame_errors);
  433. data->tmpstats.rx_frame_errors +=
  434. tsi108_read_stat(data, TSI108_STAT_RXFCS,
  435. TSI108_STAT_CARRY1_RXFCS, TSI108_STAT_RXFCS_CARRY,
  436. &data->rx_fcs);
  437. data->tmpstats.rx_frame_errors +=
  438. tsi108_read_stat(data, TSI108_STAT_RXFRAG,
  439. TSI108_STAT_CARRY1_RXFRAG,
  440. TSI108_STAT_RXFRAG_CARRY, &data->rx_short_fcs);
  441. data->tmpstats.rx_missed_errors =
  442. tsi108_read_stat(data, TSI108_STAT_RXDROP,
  443. TSI108_STAT_CARRY1_RXDROP,
  444. TSI108_STAT_RXDROP_CARRY,
  445. &data->stats.rx_missed_errors);
  446. /* These three are maintained by software. */
  447. data->tmpstats.rx_fifo_errors = data->stats.rx_fifo_errors;
  448. data->tmpstats.rx_crc_errors = data->stats.rx_crc_errors;
  449. data->tmpstats.tx_aborted_errors =
  450. tsi108_read_stat(data, TSI108_STAT_TXEXDEF,
  451. TSI108_STAT_CARRY2_TXEXDEF,
  452. TSI108_STAT_TXEXDEF_CARRY,
  453. &data->stats.tx_aborted_errors);
  454. data->tmpstats.tx_aborted_errors +=
  455. tsi108_read_stat(data, TSI108_STAT_TXPAUSEDROP,
  456. TSI108_STAT_CARRY2_TXPAUSE,
  457. TSI108_STAT_TXPAUSEDROP_CARRY,
  458. &data->tx_pause_drop);
  459. data->tmpstats.tx_aborted_errors += excol;
  460. data->tmpstats.tx_errors = data->tmpstats.tx_aborted_errors;
  461. data->tmpstats.rx_errors = data->tmpstats.rx_length_errors +
  462. data->tmpstats.rx_crc_errors +
  463. data->tmpstats.rx_frame_errors +
  464. data->tmpstats.rx_fifo_errors + data->tmpstats.rx_missed_errors;
  465. spin_unlock_irq(&data->misclock);
  466. return &data->tmpstats;
  467. }
  468. static void tsi108_restart_rx(struct tsi108_prv_data * data, struct net_device *dev)
  469. {
  470. TSI_WRITE(TSI108_EC_RXQ_PTRHIGH,
  471. TSI108_EC_RXQ_PTRHIGH_VALID);
  472. TSI_WRITE(TSI108_EC_RXCTRL, TSI108_EC_RXCTRL_GO
  473. | TSI108_EC_RXCTRL_QUEUE0);
  474. }
  475. static void tsi108_restart_tx(struct tsi108_prv_data * data)
  476. {
  477. TSI_WRITE(TSI108_EC_TXQ_PTRHIGH,
  478. TSI108_EC_TXQ_PTRHIGH_VALID);
  479. TSI_WRITE(TSI108_EC_TXCTRL, TSI108_EC_TXCTRL_IDLEINT |
  480. TSI108_EC_TXCTRL_GO | TSI108_EC_TXCTRL_QUEUE0);
  481. }
  482. /* txlock must be held by caller, with IRQs disabled, and
  483. * with permission to re-enable them when the lock is dropped.
  484. */
  485. static void tsi108_complete_tx(struct net_device *dev)
  486. {
  487. struct tsi108_prv_data *data = netdev_priv(dev);
  488. int tx;
  489. struct sk_buff *skb;
  490. int release = 0;
  491. while (!data->txfree || data->txhead != data->txtail) {
  492. tx = data->txtail;
  493. if (data->txring[tx].misc & TSI108_TX_OWN)
  494. break;
  495. skb = data->txskbs[tx];
  496. if (!(data->txring[tx].misc & TSI108_TX_OK))
  497. printk("%s: bad tx packet, misc %x\n",
  498. dev->name, data->txring[tx].misc);
  499. data->txtail = (data->txtail + 1) % TSI108_TXRING_LEN;
  500. data->txfree++;
  501. if (data->txring[tx].misc & TSI108_TX_EOF) {
  502. dev_kfree_skb_any(skb);
  503. release++;
  504. }
  505. }
  506. if (release) {
  507. if (is_valid_ether_addr(dev->dev_addr) && data->link_up)
  508. netif_wake_queue(dev);
  509. }
  510. }
  511. static int tsi108_send_packet(struct sk_buff * skb, struct net_device *dev)
  512. {
  513. struct tsi108_prv_data *data = netdev_priv(dev);
  514. int frags = skb_shinfo(skb)->nr_frags + 1;
  515. int i;
  516. if (!data->phy_ok && net_ratelimit())
  517. printk(KERN_ERR "%s: Transmit while PHY is down!\n", dev->name);
  518. if (!data->link_up) {
  519. printk(KERN_ERR "%s: Transmit while link is down!\n",
  520. dev->name);
  521. netif_stop_queue(dev);
  522. return NETDEV_TX_BUSY;
  523. }
  524. if (data->txfree < MAX_SKB_FRAGS + 1) {
  525. netif_stop_queue(dev);
  526. if (net_ratelimit())
  527. printk(KERN_ERR "%s: Transmit with full tx ring!\n",
  528. dev->name);
  529. return NETDEV_TX_BUSY;
  530. }
  531. if (data->txfree - frags < MAX_SKB_FRAGS + 1) {
  532. netif_stop_queue(dev);
  533. }
  534. spin_lock_irq(&data->txlock);
  535. for (i = 0; i < frags; i++) {
  536. int misc = 0;
  537. int tx = data->txhead;
  538. /* This is done to mark every TSI108_TX_INT_FREQ tx buffers with
  539. * the interrupt bit. TX descriptor-complete interrupts are
  540. * enabled when the queue fills up, and masked when there is
  541. * still free space. This way, when saturating the outbound
  542. * link, the tx interrupts are kept to a reasonable level.
  543. * When the queue is not full, reclamation of skbs still occurs
  544. * as new packets are transmitted, or on a queue-empty
  545. * interrupt.
  546. */
  547. if ((tx % TSI108_TX_INT_FREQ == 0) &&
  548. ((TSI108_TXRING_LEN - data->txfree) >= TSI108_TX_INT_FREQ))
  549. misc = TSI108_TX_INT;
  550. data->txskbs[tx] = skb;
  551. if (i == 0) {
  552. data->txring[tx].buf0 = dma_map_single(NULL, skb->data,
  553. skb->len - skb->data_len, DMA_TO_DEVICE);
  554. data->txring[tx].len = skb->len - skb->data_len;
  555. misc |= TSI108_TX_SOF;
  556. } else {
  557. skb_frag_t *frag = &skb_shinfo(skb)->frags[i - 1];
  558. data->txring[tx].buf0 =
  559. dma_map_page(NULL, frag->page, frag->page_offset,
  560. frag->size, DMA_TO_DEVICE);
  561. data->txring[tx].len = frag->size;
  562. }
  563. if (i == frags - 1)
  564. misc |= TSI108_TX_EOF;
  565. if (netif_msg_pktdata(data)) {
  566. int i;
  567. printk("%s: Tx Frame contents (%d)\n", dev->name,
  568. skb->len);
  569. for (i = 0; i < skb->len; i++)
  570. printk(" %2.2x", skb->data[i]);
  571. printk(".\n");
  572. }
  573. data->txring[tx].misc = misc | TSI108_TX_OWN;
  574. data->txhead = (data->txhead + 1) % TSI108_TXRING_LEN;
  575. data->txfree--;
  576. }
  577. tsi108_complete_tx(dev);
  578. /* This must be done after the check for completed tx descriptors,
  579. * so that the tail pointer is correct.
  580. */
  581. if (!(TSI_READ(TSI108_EC_TXSTAT) & TSI108_EC_TXSTAT_QUEUE0))
  582. tsi108_restart_tx(data);
  583. spin_unlock_irq(&data->txlock);
  584. return NETDEV_TX_OK;
  585. }
  586. static int tsi108_complete_rx(struct net_device *dev, int budget)
  587. {
  588. struct tsi108_prv_data *data = netdev_priv(dev);
  589. int done = 0;
  590. while (data->rxfree && done != budget) {
  591. int rx = data->rxtail;
  592. struct sk_buff *skb;
  593. if (data->rxring[rx].misc & TSI108_RX_OWN)
  594. break;
  595. skb = data->rxskbs[rx];
  596. data->rxtail = (data->rxtail + 1) % TSI108_RXRING_LEN;
  597. data->rxfree--;
  598. done++;
  599. if (data->rxring[rx].misc & TSI108_RX_BAD) {
  600. spin_lock_irq(&data->misclock);
  601. if (data->rxring[rx].misc & TSI108_RX_CRC)
  602. data->stats.rx_crc_errors++;
  603. if (data->rxring[rx].misc & TSI108_RX_OVER)
  604. data->stats.rx_fifo_errors++;
  605. spin_unlock_irq(&data->misclock);
  606. dev_kfree_skb_any(skb);
  607. continue;
  608. }
  609. if (netif_msg_pktdata(data)) {
  610. int i;
  611. printk("%s: Rx Frame contents (%d)\n",
  612. dev->name, data->rxring[rx].len);
  613. for (i = 0; i < data->rxring[rx].len; i++)
  614. printk(" %2.2x", skb->data[i]);
  615. printk(".\n");
  616. }
  617. skb_put(skb, data->rxring[rx].len);
  618. skb->protocol = eth_type_trans(skb, dev);
  619. netif_receive_skb(skb);
  620. }
  621. return done;
  622. }
  623. static int tsi108_refill_rx(struct net_device *dev, int budget)
  624. {
  625. struct tsi108_prv_data *data = netdev_priv(dev);
  626. int done = 0;
  627. while (data->rxfree != TSI108_RXRING_LEN && done != budget) {
  628. int rx = data->rxhead;
  629. struct sk_buff *skb;
  630. data->rxskbs[rx] = skb = netdev_alloc_skb(dev,
  631. TSI108_RXBUF_SIZE + 2);
  632. if (!skb)
  633. break;
  634. skb_reserve(skb, 2); /* Align the data on a 4-byte boundary. */
  635. data->rxring[rx].buf0 = dma_map_single(NULL, skb->data,
  636. TSI108_RX_SKB_SIZE,
  637. DMA_FROM_DEVICE);
  638. /* Sometimes the hardware sets blen to zero after packet
  639. * reception, even though the manual says that it's only ever
  640. * modified by the driver.
  641. */
  642. data->rxring[rx].blen = TSI108_RX_SKB_SIZE;
  643. data->rxring[rx].misc = TSI108_RX_OWN | TSI108_RX_INT;
  644. data->rxhead = (data->rxhead + 1) % TSI108_RXRING_LEN;
  645. data->rxfree++;
  646. done++;
  647. }
  648. if (done != 0 && !(TSI_READ(TSI108_EC_RXSTAT) &
  649. TSI108_EC_RXSTAT_QUEUE0))
  650. tsi108_restart_rx(data, dev);
  651. return done;
  652. }
  653. static int tsi108_poll(struct napi_struct *napi, int budget)
  654. {
  655. struct tsi108_prv_data *data = container_of(napi, struct tsi108_prv_data, napi);
  656. struct net_device *dev = data->dev;
  657. u32 estat = TSI_READ(TSI108_EC_RXESTAT);
  658. u32 intstat = TSI_READ(TSI108_EC_INTSTAT);
  659. int num_received = 0, num_filled = 0;
  660. intstat &= TSI108_INT_RXQUEUE0 | TSI108_INT_RXTHRESH |
  661. TSI108_INT_RXOVERRUN | TSI108_INT_RXERROR | TSI108_INT_RXWAIT;
  662. TSI_WRITE(TSI108_EC_RXESTAT, estat);
  663. TSI_WRITE(TSI108_EC_INTSTAT, intstat);
  664. if (data->rxpending || (estat & TSI108_EC_RXESTAT_Q0_DESCINT))
  665. num_received = tsi108_complete_rx(dev, budget);
  666. /* This should normally fill no more slots than the number of
  667. * packets received in tsi108_complete_rx(). The exception
  668. * is when we previously ran out of memory for RX SKBs. In that
  669. * case, it's helpful to obey the budget, not only so that the
  670. * CPU isn't hogged, but so that memory (which may still be low)
  671. * is not hogged by one device.
  672. *
  673. * A work unit is considered to be two SKBs to allow us to catch
  674. * up when the ring has shrunk due to out-of-memory but we're
  675. * still removing the full budget's worth of packets each time.
  676. */
  677. if (data->rxfree < TSI108_RXRING_LEN)
  678. num_filled = tsi108_refill_rx(dev, budget * 2);
  679. if (intstat & TSI108_INT_RXERROR) {
  680. u32 err = TSI_READ(TSI108_EC_RXERR);
  681. TSI_WRITE(TSI108_EC_RXERR, err);
  682. if (err) {
  683. if (net_ratelimit())
  684. printk(KERN_DEBUG "%s: RX error %x\n",
  685. dev->name, err);
  686. if (!(TSI_READ(TSI108_EC_RXSTAT) &
  687. TSI108_EC_RXSTAT_QUEUE0))
  688. tsi108_restart_rx(data, dev);
  689. }
  690. }
  691. if (intstat & TSI108_INT_RXOVERRUN) {
  692. spin_lock_irq(&data->misclock);
  693. data->stats.rx_fifo_errors++;
  694. spin_unlock_irq(&data->misclock);
  695. }
  696. if (num_received < budget) {
  697. data->rxpending = 0;
  698. napi_complete(napi);
  699. TSI_WRITE(TSI108_EC_INTMASK,
  700. TSI_READ(TSI108_EC_INTMASK)
  701. & ~(TSI108_INT_RXQUEUE0
  702. | TSI108_INT_RXTHRESH |
  703. TSI108_INT_RXOVERRUN |
  704. TSI108_INT_RXERROR |
  705. TSI108_INT_RXWAIT));
  706. } else {
  707. data->rxpending = 1;
  708. }
  709. return num_received;
  710. }
  711. static void tsi108_rx_int(struct net_device *dev)
  712. {
  713. struct tsi108_prv_data *data = netdev_priv(dev);
  714. /* A race could cause dev to already be scheduled, so it's not an
  715. * error if that happens (and interrupts shouldn't be re-masked,
  716. * because that can cause harmful races, if poll has already
  717. * unmasked them but not cleared LINK_STATE_SCHED).
  718. *
  719. * This can happen if this code races with tsi108_poll(), which masks
  720. * the interrupts after tsi108_irq_one() read the mask, but before
  721. * napi_schedule is called. It could also happen due to calls
  722. * from tsi108_check_rxring().
  723. */
  724. if (napi_schedule_prep(&data->napi)) {
  725. /* Mask, rather than ack, the receive interrupts. The ack
  726. * will happen in tsi108_poll().
  727. */
  728. TSI_WRITE(TSI108_EC_INTMASK,
  729. TSI_READ(TSI108_EC_INTMASK) |
  730. TSI108_INT_RXQUEUE0
  731. | TSI108_INT_RXTHRESH |
  732. TSI108_INT_RXOVERRUN | TSI108_INT_RXERROR |
  733. TSI108_INT_RXWAIT);
  734. __napi_schedule(&data->napi);
  735. } else {
  736. if (!netif_running(dev)) {
  737. /* This can happen if an interrupt occurs while the
  738. * interface is being brought down, as the START
  739. * bit is cleared before the stop function is called.
  740. *
  741. * In this case, the interrupts must be masked, or
  742. * they will continue indefinitely.
  743. *
  744. * There's a race here if the interface is brought down
  745. * and then up in rapid succession, as the device could
  746. * be made running after the above check and before
  747. * the masking below. This will only happen if the IRQ
  748. * thread has a lower priority than the task brining
  749. * up the interface. Fixing this race would likely
  750. * require changes in generic code.
  751. */
  752. TSI_WRITE(TSI108_EC_INTMASK,
  753. TSI_READ
  754. (TSI108_EC_INTMASK) |
  755. TSI108_INT_RXQUEUE0 |
  756. TSI108_INT_RXTHRESH |
  757. TSI108_INT_RXOVERRUN |
  758. TSI108_INT_RXERROR |
  759. TSI108_INT_RXWAIT);
  760. }
  761. }
  762. }
  763. /* If the RX ring has run out of memory, try periodically
  764. * to allocate some more, as otherwise poll would never
  765. * get called (apart from the initial end-of-queue condition).
  766. *
  767. * This is called once per second (by default) from the thread.
  768. */
  769. static void tsi108_check_rxring(struct net_device *dev)
  770. {
  771. struct tsi108_prv_data *data = netdev_priv(dev);
  772. /* A poll is scheduled, as opposed to caling tsi108_refill_rx
  773. * directly, so as to keep the receive path single-threaded
  774. * (and thus not needing a lock).
  775. */
  776. if (netif_running(dev) && data->rxfree < TSI108_RXRING_LEN / 4)
  777. tsi108_rx_int(dev);
  778. }
  779. static void tsi108_tx_int(struct net_device *dev)
  780. {
  781. struct tsi108_prv_data *data = netdev_priv(dev);
  782. u32 estat = TSI_READ(TSI108_EC_TXESTAT);
  783. TSI_WRITE(TSI108_EC_TXESTAT, estat);
  784. TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_TXQUEUE0 |
  785. TSI108_INT_TXIDLE | TSI108_INT_TXERROR);
  786. if (estat & TSI108_EC_TXESTAT_Q0_ERR) {
  787. u32 err = TSI_READ(TSI108_EC_TXERR);
  788. TSI_WRITE(TSI108_EC_TXERR, err);
  789. if (err && net_ratelimit())
  790. printk(KERN_ERR "%s: TX error %x\n", dev->name, err);
  791. }
  792. if (estat & (TSI108_EC_TXESTAT_Q0_DESCINT | TSI108_EC_TXESTAT_Q0_EOQ)) {
  793. spin_lock(&data->txlock);
  794. tsi108_complete_tx(dev);
  795. spin_unlock(&data->txlock);
  796. }
  797. }
  798. static irqreturn_t tsi108_irq(int irq, void *dev_id)
  799. {
  800. struct net_device *dev = dev_id;
  801. struct tsi108_prv_data *data = netdev_priv(dev);
  802. u32 stat = TSI_READ(TSI108_EC_INTSTAT);
  803. if (!(stat & TSI108_INT_ANY))
  804. return IRQ_NONE; /* Not our interrupt */
  805. stat &= ~TSI_READ(TSI108_EC_INTMASK);
  806. if (stat & (TSI108_INT_TXQUEUE0 | TSI108_INT_TXIDLE |
  807. TSI108_INT_TXERROR))
  808. tsi108_tx_int(dev);
  809. if (stat & (TSI108_INT_RXQUEUE0 | TSI108_INT_RXTHRESH |
  810. TSI108_INT_RXWAIT | TSI108_INT_RXOVERRUN |
  811. TSI108_INT_RXERROR))
  812. tsi108_rx_int(dev);
  813. if (stat & TSI108_INT_SFN) {
  814. if (net_ratelimit())
  815. printk(KERN_DEBUG "%s: SFN error\n", dev->name);
  816. TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_SFN);
  817. }
  818. if (stat & TSI108_INT_STATCARRY) {
  819. tsi108_stat_carry(dev);
  820. TSI_WRITE(TSI108_EC_INTSTAT, TSI108_INT_STATCARRY);
  821. }
  822. return IRQ_HANDLED;
  823. }
  824. static void tsi108_stop_ethernet(struct net_device *dev)
  825. {
  826. struct tsi108_prv_data *data = netdev_priv(dev);
  827. int i = 1000;
  828. /* Disable all TX and RX queues ... */
  829. TSI_WRITE(TSI108_EC_TXCTRL, 0);
  830. TSI_WRITE(TSI108_EC_RXCTRL, 0);
  831. /* ...and wait for them to become idle */
  832. while(i--) {
  833. if(!(TSI_READ(TSI108_EC_TXSTAT) & TSI108_EC_TXSTAT_ACTIVE))
  834. break;
  835. udelay(10);
  836. }
  837. i = 1000;
  838. while(i--){
  839. if(!(TSI_READ(TSI108_EC_RXSTAT) & TSI108_EC_RXSTAT_ACTIVE))
  840. return;
  841. udelay(10);
  842. }
  843. printk(KERN_ERR "%s function time out \n", __func__);
  844. }
  845. static void tsi108_reset_ether(struct tsi108_prv_data * data)
  846. {
  847. TSI_WRITE(TSI108_MAC_CFG1, TSI108_MAC_CFG1_SOFTRST);
  848. udelay(100);
  849. TSI_WRITE(TSI108_MAC_CFG1, 0);
  850. TSI_WRITE(TSI108_EC_PORTCTRL, TSI108_EC_PORTCTRL_STATRST);
  851. udelay(100);
  852. TSI_WRITE(TSI108_EC_PORTCTRL,
  853. TSI_READ(TSI108_EC_PORTCTRL) &
  854. ~TSI108_EC_PORTCTRL_STATRST);
  855. TSI_WRITE(TSI108_EC_TXCFG, TSI108_EC_TXCFG_RST);
  856. udelay(100);
  857. TSI_WRITE(TSI108_EC_TXCFG,
  858. TSI_READ(TSI108_EC_TXCFG) &
  859. ~TSI108_EC_TXCFG_RST);
  860. TSI_WRITE(TSI108_EC_RXCFG, TSI108_EC_RXCFG_RST);
  861. udelay(100);
  862. TSI_WRITE(TSI108_EC_RXCFG,
  863. TSI_READ(TSI108_EC_RXCFG) &
  864. ~TSI108_EC_RXCFG_RST);
  865. TSI_WRITE(TSI108_MAC_MII_MGMT_CFG,
  866. TSI_READ(TSI108_MAC_MII_MGMT_CFG) |
  867. TSI108_MAC_MII_MGMT_RST);
  868. udelay(100);
  869. TSI_WRITE(TSI108_MAC_MII_MGMT_CFG,
  870. (TSI_READ(TSI108_MAC_MII_MGMT_CFG) &
  871. ~(TSI108_MAC_MII_MGMT_RST |
  872. TSI108_MAC_MII_MGMT_CLK)) | 0x07);
  873. }
  874. static int tsi108_get_mac(struct net_device *dev)
  875. {
  876. struct tsi108_prv_data *data = netdev_priv(dev);
  877. u32 word1 = TSI_READ(TSI108_MAC_ADDR1);
  878. u32 word2 = TSI_READ(TSI108_MAC_ADDR2);
  879. /* Note that the octets are reversed from what the manual says,
  880. * producing an even weirder ordering...
  881. */
  882. if (word2 == 0 && word1 == 0) {
  883. dev->dev_addr[0] = 0x00;
  884. dev->dev_addr[1] = 0x06;
  885. dev->dev_addr[2] = 0xd2;
  886. dev->dev_addr[3] = 0x00;
  887. dev->dev_addr[4] = 0x00;
  888. if (0x8 == data->phy)
  889. dev->dev_addr[5] = 0x01;
  890. else
  891. dev->dev_addr[5] = 0x02;
  892. word2 = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 24);
  893. word1 = (dev->dev_addr[2] << 0) | (dev->dev_addr[3] << 8) |
  894. (dev->dev_addr[4] << 16) | (dev->dev_addr[5] << 24);
  895. TSI_WRITE(TSI108_MAC_ADDR1, word1);
  896. TSI_WRITE(TSI108_MAC_ADDR2, word2);
  897. } else {
  898. dev->dev_addr[0] = (word2 >> 16) & 0xff;
  899. dev->dev_addr[1] = (word2 >> 24) & 0xff;
  900. dev->dev_addr[2] = (word1 >> 0) & 0xff;
  901. dev->dev_addr[3] = (word1 >> 8) & 0xff;
  902. dev->dev_addr[4] = (word1 >> 16) & 0xff;
  903. dev->dev_addr[5] = (word1 >> 24) & 0xff;
  904. }
  905. if (!is_valid_ether_addr(dev->dev_addr)) {
  906. printk("KERN_ERR: word1: %08x, word2: %08x\n", word1, word2);
  907. return -EINVAL;
  908. }
  909. return 0;
  910. }
  911. static int tsi108_set_mac(struct net_device *dev, void *addr)
  912. {
  913. struct tsi108_prv_data *data = netdev_priv(dev);
  914. u32 word1, word2;
  915. int i;
  916. if (!is_valid_ether_addr(addr))
  917. return -EINVAL;
  918. for (i = 0; i < 6; i++)
  919. /* +2 is for the offset of the HW addr type */
  920. dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
  921. word2 = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 24);
  922. word1 = (dev->dev_addr[2] << 0) | (dev->dev_addr[3] << 8) |
  923. (dev->dev_addr[4] << 16) | (dev->dev_addr[5] << 24);
  924. spin_lock_irq(&data->misclock);
  925. TSI_WRITE(TSI108_MAC_ADDR1, word1);
  926. TSI_WRITE(TSI108_MAC_ADDR2, word2);
  927. spin_lock(&data->txlock);
  928. if (data->txfree && data->link_up)
  929. netif_wake_queue(dev);
  930. spin_unlock(&data->txlock);
  931. spin_unlock_irq(&data->misclock);
  932. return 0;
  933. }
  934. /* Protected by dev->xmit_lock. */
  935. static void tsi108_set_rx_mode(struct net_device *dev)
  936. {
  937. struct tsi108_prv_data *data = netdev_priv(dev);
  938. u32 rxcfg = TSI_READ(TSI108_EC_RXCFG);
  939. if (dev->flags & IFF_PROMISC) {
  940. rxcfg &= ~(TSI108_EC_RXCFG_UC_HASH | TSI108_EC_RXCFG_MC_HASH);
  941. rxcfg |= TSI108_EC_RXCFG_UFE | TSI108_EC_RXCFG_MFE;
  942. goto out;
  943. }
  944. rxcfg &= ~(TSI108_EC_RXCFG_UFE | TSI108_EC_RXCFG_MFE);
  945. if (dev->flags & IFF_ALLMULTI || dev->mc_count) {
  946. int i;
  947. struct dev_mc_list *mc = dev->mc_list;
  948. rxcfg |= TSI108_EC_RXCFG_MFE | TSI108_EC_RXCFG_MC_HASH;
  949. memset(data->mc_hash, 0, sizeof(data->mc_hash));
  950. while (mc) {
  951. u32 hash, crc;
  952. if (mc->dmi_addrlen == 6) {
  953. crc = ether_crc(6, mc->dmi_addr);
  954. hash = crc >> 23;
  955. __set_bit(hash, &data->mc_hash[0]);
  956. } else {
  957. printk(KERN_ERR
  958. "%s: got multicast address of length %d "
  959. "instead of 6.\n", dev->name,
  960. mc->dmi_addrlen);
  961. }
  962. mc = mc->next;
  963. }
  964. TSI_WRITE(TSI108_EC_HASHADDR,
  965. TSI108_EC_HASHADDR_AUTOINC |
  966. TSI108_EC_HASHADDR_MCAST);
  967. for (i = 0; i < 16; i++) {
  968. /* The manual says that the hardware may drop
  969. * back-to-back writes to the data register.
  970. */
  971. udelay(1);
  972. TSI_WRITE(TSI108_EC_HASHDATA,
  973. data->mc_hash[i]);
  974. }
  975. }
  976. out:
  977. TSI_WRITE(TSI108_EC_RXCFG, rxcfg);
  978. }
  979. static void tsi108_init_phy(struct net_device *dev)
  980. {
  981. struct tsi108_prv_data *data = netdev_priv(dev);
  982. u32 i = 0;
  983. u16 phyval = 0;
  984. unsigned long flags;
  985. spin_lock_irqsave(&phy_lock, flags);
  986. tsi108_write_mii(data, MII_BMCR, BMCR_RESET);
  987. while (--i) {
  988. if(!(tsi108_read_mii(data, MII_BMCR) & BMCR_RESET))
  989. break;
  990. udelay(10);
  991. }
  992. if (i == 0)
  993. printk(KERN_ERR "%s function time out \n", __func__);
  994. if (data->phy_type == TSI108_PHY_BCM54XX) {
  995. tsi108_write_mii(data, 0x09, 0x0300);
  996. tsi108_write_mii(data, 0x10, 0x1020);
  997. tsi108_write_mii(data, 0x1c, 0x8c00);
  998. }
  999. tsi108_write_mii(data,
  1000. MII_BMCR,
  1001. BMCR_ANENABLE | BMCR_ANRESTART);
  1002. while (tsi108_read_mii(data, MII_BMCR) & BMCR_ANRESTART)
  1003. cpu_relax();
  1004. /* Set G/MII mode and receive clock select in TBI control #2. The
  1005. * second port won't work if this isn't done, even though we don't
  1006. * use TBI mode.
  1007. */
  1008. tsi108_write_tbi(data, 0x11, 0x30);
  1009. /* FIXME: It seems to take more than 2 back-to-back reads to the
  1010. * PHY_STAT register before the link up status bit is set.
  1011. */
  1012. data->link_up = 0;
  1013. while (!((phyval = tsi108_read_mii(data, MII_BMSR)) &
  1014. BMSR_LSTATUS)) {
  1015. if (i++ > (MII_READ_DELAY / 10)) {
  1016. break;
  1017. }
  1018. spin_unlock_irqrestore(&phy_lock, flags);
  1019. msleep(10);
  1020. spin_lock_irqsave(&phy_lock, flags);
  1021. }
  1022. data->mii_if.supports_gmii = mii_check_gmii_support(&data->mii_if);
  1023. printk(KERN_DEBUG "PHY_STAT reg contains %08x\n", phyval);
  1024. data->phy_ok = 1;
  1025. data->init_media = 1;
  1026. spin_unlock_irqrestore(&phy_lock, flags);
  1027. }
  1028. static void tsi108_kill_phy(struct net_device *dev)
  1029. {
  1030. struct tsi108_prv_data *data = netdev_priv(dev);
  1031. unsigned long flags;
  1032. spin_lock_irqsave(&phy_lock, flags);
  1033. tsi108_write_mii(data, MII_BMCR, BMCR_PDOWN);
  1034. data->phy_ok = 0;
  1035. spin_unlock_irqrestore(&phy_lock, flags);
  1036. }
  1037. static int tsi108_open(struct net_device *dev)
  1038. {
  1039. int i;
  1040. struct tsi108_prv_data *data = netdev_priv(dev);
  1041. unsigned int rxring_size = TSI108_RXRING_LEN * sizeof(rx_desc);
  1042. unsigned int txring_size = TSI108_TXRING_LEN * sizeof(tx_desc);
  1043. i = request_irq(data->irq_num, tsi108_irq, 0, dev->name, dev);
  1044. if (i != 0) {
  1045. printk(KERN_ERR "tsi108_eth%d: Could not allocate IRQ%d.\n",
  1046. data->id, data->irq_num);
  1047. return i;
  1048. } else {
  1049. dev->irq = data->irq_num;
  1050. printk(KERN_NOTICE
  1051. "tsi108_open : Port %d Assigned IRQ %d to %s\n",
  1052. data->id, dev->irq, dev->name);
  1053. }
  1054. data->rxring = dma_alloc_coherent(NULL, rxring_size,
  1055. &data->rxdma, GFP_KERNEL);
  1056. if (!data->rxring) {
  1057. printk(KERN_DEBUG
  1058. "TSI108_ETH: failed to allocate memory for rxring!\n");
  1059. return -ENOMEM;
  1060. } else {
  1061. memset(data->rxring, 0, rxring_size);
  1062. }
  1063. data->txring = dma_alloc_coherent(NULL, txring_size,
  1064. &data->txdma, GFP_KERNEL);
  1065. if (!data->txring) {
  1066. printk(KERN_DEBUG
  1067. "TSI108_ETH: failed to allocate memory for txring!\n");
  1068. pci_free_consistent(0, rxring_size, data->rxring, data->rxdma);
  1069. return -ENOMEM;
  1070. } else {
  1071. memset(data->txring, 0, txring_size);
  1072. }
  1073. for (i = 0; i < TSI108_RXRING_LEN; i++) {
  1074. data->rxring[i].next0 = data->rxdma + (i + 1) * sizeof(rx_desc);
  1075. data->rxring[i].blen = TSI108_RXBUF_SIZE;
  1076. data->rxring[i].vlan = 0;
  1077. }
  1078. data->rxring[TSI108_RXRING_LEN - 1].next0 = data->rxdma;
  1079. data->rxtail = 0;
  1080. data->rxhead = 0;
  1081. for (i = 0; i < TSI108_RXRING_LEN; i++) {
  1082. struct sk_buff *skb;
  1083. skb = netdev_alloc_skb(dev, TSI108_RXBUF_SIZE + NET_IP_ALIGN);
  1084. if (!skb) {
  1085. /* Bah. No memory for now, but maybe we'll get
  1086. * some more later.
  1087. * For now, we'll live with the smaller ring.
  1088. */
  1089. printk(KERN_WARNING
  1090. "%s: Could only allocate %d receive skb(s).\n",
  1091. dev->name, i);
  1092. data->rxhead = i;
  1093. break;
  1094. }
  1095. data->rxskbs[i] = skb;
  1096. /* Align the payload on a 4-byte boundary */
  1097. skb_reserve(skb, 2);
  1098. data->rxskbs[i] = skb;
  1099. data->rxring[i].buf0 = virt_to_phys(data->rxskbs[i]->data);
  1100. data->rxring[i].misc = TSI108_RX_OWN | TSI108_RX_INT;
  1101. }
  1102. data->rxfree = i;
  1103. TSI_WRITE(TSI108_EC_RXQ_PTRLOW, data->rxdma);
  1104. for (i = 0; i < TSI108_TXRING_LEN; i++) {
  1105. data->txring[i].next0 = data->txdma + (i + 1) * sizeof(tx_desc);
  1106. data->txring[i].misc = 0;
  1107. }
  1108. data->txring[TSI108_TXRING_LEN - 1].next0 = data->txdma;
  1109. data->txtail = 0;
  1110. data->txhead = 0;
  1111. data->txfree = TSI108_TXRING_LEN;
  1112. TSI_WRITE(TSI108_EC_TXQ_PTRLOW, data->txdma);
  1113. tsi108_init_phy(dev);
  1114. napi_enable(&data->napi);
  1115. setup_timer(&data->timer, tsi108_timed_checker, (unsigned long)dev);
  1116. mod_timer(&data->timer, jiffies + 1);
  1117. tsi108_restart_rx(data, dev);
  1118. TSI_WRITE(TSI108_EC_INTSTAT, ~0);
  1119. TSI_WRITE(TSI108_EC_INTMASK,
  1120. ~(TSI108_INT_TXQUEUE0 | TSI108_INT_RXERROR |
  1121. TSI108_INT_RXTHRESH | TSI108_INT_RXQUEUE0 |
  1122. TSI108_INT_RXOVERRUN | TSI108_INT_RXWAIT |
  1123. TSI108_INT_SFN | TSI108_INT_STATCARRY));
  1124. TSI_WRITE(TSI108_MAC_CFG1,
  1125. TSI108_MAC_CFG1_RXEN | TSI108_MAC_CFG1_TXEN);
  1126. netif_start_queue(dev);
  1127. return 0;
  1128. }
  1129. static int tsi108_close(struct net_device *dev)
  1130. {
  1131. struct tsi108_prv_data *data = netdev_priv(dev);
  1132. netif_stop_queue(dev);
  1133. napi_disable(&data->napi);
  1134. del_timer_sync(&data->timer);
  1135. tsi108_stop_ethernet(dev);
  1136. tsi108_kill_phy(dev);
  1137. TSI_WRITE(TSI108_EC_INTMASK, ~0);
  1138. TSI_WRITE(TSI108_MAC_CFG1, 0);
  1139. /* Check for any pending TX packets, and drop them. */
  1140. while (!data->txfree || data->txhead != data->txtail) {
  1141. int tx = data->txtail;
  1142. struct sk_buff *skb;
  1143. skb = data->txskbs[tx];
  1144. data->txtail = (data->txtail + 1) % TSI108_TXRING_LEN;
  1145. data->txfree++;
  1146. dev_kfree_skb(skb);
  1147. }
  1148. free_irq(data->irq_num, dev);
  1149. /* Discard the RX ring. */
  1150. while (data->rxfree) {
  1151. int rx = data->rxtail;
  1152. struct sk_buff *skb;
  1153. skb = data->rxskbs[rx];
  1154. data->rxtail = (data->rxtail + 1) % TSI108_RXRING_LEN;
  1155. data->rxfree--;
  1156. dev_kfree_skb(skb);
  1157. }
  1158. dma_free_coherent(0,
  1159. TSI108_RXRING_LEN * sizeof(rx_desc),
  1160. data->rxring, data->rxdma);
  1161. dma_free_coherent(0,
  1162. TSI108_TXRING_LEN * sizeof(tx_desc),
  1163. data->txring, data->txdma);
  1164. return 0;
  1165. }
  1166. static void tsi108_init_mac(struct net_device *dev)
  1167. {
  1168. struct tsi108_prv_data *data = netdev_priv(dev);
  1169. TSI_WRITE(TSI108_MAC_CFG2, TSI108_MAC_CFG2_DFLT_PREAMBLE |
  1170. TSI108_MAC_CFG2_PADCRC);
  1171. TSI_WRITE(TSI108_EC_TXTHRESH,
  1172. (192 << TSI108_EC_TXTHRESH_STARTFILL) |
  1173. (192 << TSI108_EC_TXTHRESH_STOPFILL));
  1174. TSI_WRITE(TSI108_STAT_CARRYMASK1,
  1175. ~(TSI108_STAT_CARRY1_RXBYTES |
  1176. TSI108_STAT_CARRY1_RXPKTS |
  1177. TSI108_STAT_CARRY1_RXFCS |
  1178. TSI108_STAT_CARRY1_RXMCAST |
  1179. TSI108_STAT_CARRY1_RXALIGN |
  1180. TSI108_STAT_CARRY1_RXLENGTH |
  1181. TSI108_STAT_CARRY1_RXRUNT |
  1182. TSI108_STAT_CARRY1_RXJUMBO |
  1183. TSI108_STAT_CARRY1_RXFRAG |
  1184. TSI108_STAT_CARRY1_RXJABBER |
  1185. TSI108_STAT_CARRY1_RXDROP));
  1186. TSI_WRITE(TSI108_STAT_CARRYMASK2,
  1187. ~(TSI108_STAT_CARRY2_TXBYTES |
  1188. TSI108_STAT_CARRY2_TXPKTS |
  1189. TSI108_STAT_CARRY2_TXEXDEF |
  1190. TSI108_STAT_CARRY2_TXEXCOL |
  1191. TSI108_STAT_CARRY2_TXTCOL |
  1192. TSI108_STAT_CARRY2_TXPAUSE));
  1193. TSI_WRITE(TSI108_EC_PORTCTRL, TSI108_EC_PORTCTRL_STATEN);
  1194. TSI_WRITE(TSI108_MAC_CFG1, 0);
  1195. TSI_WRITE(TSI108_EC_RXCFG,
  1196. TSI108_EC_RXCFG_SE | TSI108_EC_RXCFG_BFE);
  1197. TSI_WRITE(TSI108_EC_TXQ_CFG, TSI108_EC_TXQ_CFG_DESC_INT |
  1198. TSI108_EC_TXQ_CFG_EOQ_OWN_INT |
  1199. TSI108_EC_TXQ_CFG_WSWP | (TSI108_PBM_PORT <<
  1200. TSI108_EC_TXQ_CFG_SFNPORT));
  1201. TSI_WRITE(TSI108_EC_RXQ_CFG, TSI108_EC_RXQ_CFG_DESC_INT |
  1202. TSI108_EC_RXQ_CFG_EOQ_OWN_INT |
  1203. TSI108_EC_RXQ_CFG_WSWP | (TSI108_PBM_PORT <<
  1204. TSI108_EC_RXQ_CFG_SFNPORT));
  1205. TSI_WRITE(TSI108_EC_TXQ_BUFCFG,
  1206. TSI108_EC_TXQ_BUFCFG_BURST256 |
  1207. TSI108_EC_TXQ_BUFCFG_BSWP | (TSI108_PBM_PORT <<
  1208. TSI108_EC_TXQ_BUFCFG_SFNPORT));
  1209. TSI_WRITE(TSI108_EC_RXQ_BUFCFG,
  1210. TSI108_EC_RXQ_BUFCFG_BURST256 |
  1211. TSI108_EC_RXQ_BUFCFG_BSWP | (TSI108_PBM_PORT <<
  1212. TSI108_EC_RXQ_BUFCFG_SFNPORT));
  1213. TSI_WRITE(TSI108_EC_INTMASK, ~0);
  1214. }
  1215. static int tsi108_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1216. {
  1217. struct tsi108_prv_data *data = netdev_priv(dev);
  1218. unsigned long flags;
  1219. int rc;
  1220. spin_lock_irqsave(&data->txlock, flags);
  1221. rc = mii_ethtool_gset(&data->mii_if, cmd);
  1222. spin_unlock_irqrestore(&data->txlock, flags);
  1223. return rc;
  1224. }
  1225. static int tsi108_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1226. {
  1227. struct tsi108_prv_data *data = netdev_priv(dev);
  1228. unsigned long flags;
  1229. int rc;
  1230. spin_lock_irqsave(&data->txlock, flags);
  1231. rc = mii_ethtool_sset(&data->mii_if, cmd);
  1232. spin_unlock_irqrestore(&data->txlock, flags);
  1233. return rc;
  1234. }
  1235. static int tsi108_do_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  1236. {
  1237. struct tsi108_prv_data *data = netdev_priv(dev);
  1238. if (!netif_running(dev))
  1239. return -EINVAL;
  1240. return generic_mii_ioctl(&data->mii_if, if_mii(rq), cmd, NULL);
  1241. }
  1242. static const struct ethtool_ops tsi108_ethtool_ops = {
  1243. .get_link = ethtool_op_get_link,
  1244. .get_settings = tsi108_get_settings,
  1245. .set_settings = tsi108_set_settings,
  1246. };
  1247. static const struct net_device_ops tsi108_netdev_ops = {
  1248. .ndo_open = tsi108_open,
  1249. .ndo_stop = tsi108_close,
  1250. .ndo_start_xmit = tsi108_send_packet,
  1251. .ndo_set_multicast_list = tsi108_set_rx_mode,
  1252. .ndo_get_stats = tsi108_get_stats,
  1253. .ndo_do_ioctl = tsi108_do_ioctl,
  1254. .ndo_set_mac_address = tsi108_set_mac,
  1255. .ndo_validate_addr = eth_validate_addr,
  1256. .ndo_change_mtu = eth_change_mtu,
  1257. };
  1258. static int
  1259. tsi108_init_one(struct platform_device *pdev)
  1260. {
  1261. struct net_device *dev = NULL;
  1262. struct tsi108_prv_data *data = NULL;
  1263. hw_info *einfo;
  1264. int err = 0;
  1265. einfo = pdev->dev.platform_data;
  1266. if (NULL == einfo) {
  1267. printk(KERN_ERR "tsi-eth %d: Missing additional data!\n",
  1268. pdev->id);
  1269. return -ENODEV;
  1270. }
  1271. /* Create an ethernet device instance */
  1272. dev = alloc_etherdev(sizeof(struct tsi108_prv_data));
  1273. if (!dev) {
  1274. printk("tsi108_eth: Could not allocate a device structure\n");
  1275. return -ENOMEM;
  1276. }
  1277. printk("tsi108_eth%d: probe...\n", pdev->id);
  1278. data = netdev_priv(dev);
  1279. data->dev = dev;
  1280. pr_debug("tsi108_eth%d:regs:phyresgs:phy:irq_num=0x%x:0x%x:0x%x:0x%x\n",
  1281. pdev->id, einfo->regs, einfo->phyregs,
  1282. einfo->phy, einfo->irq_num);
  1283. data->regs = ioremap(einfo->regs, 0x400);
  1284. if (NULL == data->regs) {
  1285. err = -ENOMEM;
  1286. goto regs_fail;
  1287. }
  1288. data->phyregs = ioremap(einfo->phyregs, 0x400);
  1289. if (NULL == data->phyregs) {
  1290. err = -ENOMEM;
  1291. goto regs_fail;
  1292. }
  1293. /* MII setup */
  1294. data->mii_if.dev = dev;
  1295. data->mii_if.mdio_read = tsi108_mdio_read;
  1296. data->mii_if.mdio_write = tsi108_mdio_write;
  1297. data->mii_if.phy_id = einfo->phy;
  1298. data->mii_if.phy_id_mask = 0x1f;
  1299. data->mii_if.reg_num_mask = 0x1f;
  1300. data->phy = einfo->phy;
  1301. data->phy_type = einfo->phy_type;
  1302. data->irq_num = einfo->irq_num;
  1303. data->id = pdev->id;
  1304. netif_napi_add(dev, &data->napi, tsi108_poll, 64);
  1305. dev->netdev_ops = &tsi108_netdev_ops;
  1306. dev->ethtool_ops = &tsi108_ethtool_ops;
  1307. /* Apparently, the Linux networking code won't use scatter-gather
  1308. * if the hardware doesn't do checksums. However, it's faster
  1309. * to checksum in place and use SG, as (among other reasons)
  1310. * the cache won't be dirtied (which then has to be flushed
  1311. * before DMA). The checksumming is done by the driver (via
  1312. * a new function skb_csum_dev() in net/core/skbuff.c).
  1313. */
  1314. dev->features = NETIF_F_HIGHDMA;
  1315. spin_lock_init(&data->txlock);
  1316. spin_lock_init(&data->misclock);
  1317. tsi108_reset_ether(data);
  1318. tsi108_kill_phy(dev);
  1319. if ((err = tsi108_get_mac(dev)) != 0) {
  1320. printk(KERN_ERR "%s: Invalid MAC address. Please correct.\n",
  1321. dev->name);
  1322. goto register_fail;
  1323. }
  1324. tsi108_init_mac(dev);
  1325. err = register_netdev(dev);
  1326. if (err) {
  1327. printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
  1328. dev->name);
  1329. goto register_fail;
  1330. }
  1331. platform_set_drvdata(pdev, dev);
  1332. printk(KERN_INFO "%s: Tsi108 Gigabit Ethernet, MAC: %pM\n",
  1333. dev->name, dev->dev_addr);
  1334. #ifdef DEBUG
  1335. data->msg_enable = DEBUG;
  1336. dump_eth_one(dev);
  1337. #endif
  1338. return 0;
  1339. register_fail:
  1340. iounmap(data->regs);
  1341. iounmap(data->phyregs);
  1342. regs_fail:
  1343. free_netdev(dev);
  1344. return err;
  1345. }
  1346. /* There's no way to either get interrupts from the PHY when
  1347. * something changes, or to have the Tsi108 automatically communicate
  1348. * with the PHY to reconfigure itself.
  1349. *
  1350. * Thus, we have to do it using a timer.
  1351. */
  1352. static void tsi108_timed_checker(unsigned long dev_ptr)
  1353. {
  1354. struct net_device *dev = (struct net_device *)dev_ptr;
  1355. struct tsi108_prv_data *data = netdev_priv(dev);
  1356. tsi108_check_phy(dev);
  1357. tsi108_check_rxring(dev);
  1358. mod_timer(&data->timer, jiffies + CHECK_PHY_INTERVAL);
  1359. }
  1360. static int tsi108_ether_init(void)
  1361. {
  1362. int ret;
  1363. ret = platform_driver_register (&tsi_eth_driver);
  1364. if (ret < 0){
  1365. printk("tsi108_ether_init: error initializing ethernet "
  1366. "device\n");
  1367. return ret;
  1368. }
  1369. return 0;
  1370. }
  1371. static int tsi108_ether_remove(struct platform_device *pdev)
  1372. {
  1373. struct net_device *dev = platform_get_drvdata(pdev);
  1374. struct tsi108_prv_data *priv = netdev_priv(dev);
  1375. unregister_netdev(dev);
  1376. tsi108_stop_ethernet(dev);
  1377. platform_set_drvdata(pdev, NULL);
  1378. iounmap(priv->regs);
  1379. iounmap(priv->phyregs);
  1380. free_netdev(dev);
  1381. return 0;
  1382. }
  1383. static void tsi108_ether_exit(void)
  1384. {
  1385. platform_driver_unregister(&tsi_eth_driver);
  1386. }
  1387. module_init(tsi108_ether_init);
  1388. module_exit(tsi108_ether_exit);
  1389. MODULE_AUTHOR("Tundra Semiconductor Corporation");
  1390. MODULE_DESCRIPTION("Tsi108 Gigabit Ethernet driver");
  1391. MODULE_LICENSE("GPL");
  1392. MODULE_ALIAS("platform:tsi-ethernet");