xfp_phy.c 6.3 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2006-2008 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. /*
  10. * Driver for SFP+ and XFP optical PHYs plus some support specific to the
  11. * AMCC QT20xx adapters; see www.amcc.com for details
  12. */
  13. #include <linux/timer.h>
  14. #include <linux/delay.h>
  15. #include "efx.h"
  16. #include "mdio_10g.h"
  17. #include "xenpack.h"
  18. #include "phy.h"
  19. #include "falcon.h"
  20. #define XFP_REQUIRED_DEVS (MDIO_MMDREG_DEVS_PCS | \
  21. MDIO_MMDREG_DEVS_PMAPMD | \
  22. MDIO_MMDREG_DEVS_PHYXS)
  23. #define XFP_LOOPBACKS ((1 << LOOPBACK_PCS) | \
  24. (1 << LOOPBACK_PMAPMD) | \
  25. (1 << LOOPBACK_NETWORK))
  26. /****************************************************************************/
  27. /* Quake-specific MDIO registers */
  28. #define MDIO_QUAKE_LED0_REG (0xD006)
  29. /* QT2025C only */
  30. #define PCS_FW_HEARTBEAT_REG 0xd7ee
  31. #define PCS_FW_HEARTB_LBN 0
  32. #define PCS_FW_HEARTB_WIDTH 8
  33. #define PCS_UC8051_STATUS_REG 0xd7fd
  34. #define PCS_UC_STATUS_LBN 0
  35. #define PCS_UC_STATUS_WIDTH 8
  36. #define PCS_UC_STATUS_FW_SAVE 0x20
  37. #define PMA_PMD_FTX_CTRL2_REG 0xc309
  38. #define PMA_PMD_FTX_STATIC_LBN 13
  39. #define PMA_PMD_VEND1_REG 0xc001
  40. #define PMA_PMD_VEND1_LBTXD_LBN 15
  41. #define PCS_VEND1_REG 0xc000
  42. #define PCS_VEND1_LBTXD_LBN 5
  43. void xfp_set_led(struct efx_nic *p, int led, int mode)
  44. {
  45. int addr = MDIO_QUAKE_LED0_REG + led;
  46. mdio_clause45_write(p, p->mii.phy_id, MDIO_MMD_PMAPMD, addr,
  47. mode);
  48. }
  49. struct xfp_phy_data {
  50. enum efx_phy_mode phy_mode;
  51. };
  52. #define XFP_MAX_RESET_TIME 500
  53. #define XFP_RESET_WAIT 10
  54. static int qt2025c_wait_reset(struct efx_nic *efx)
  55. {
  56. unsigned long timeout = jiffies + 10 * HZ;
  57. int phy_id = efx->mii.phy_id;
  58. int reg, old_counter = 0;
  59. /* Wait for firmware heartbeat to start */
  60. for (;;) {
  61. int counter;
  62. reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS,
  63. PCS_FW_HEARTBEAT_REG);
  64. if (reg < 0)
  65. return reg;
  66. counter = ((reg >> PCS_FW_HEARTB_LBN) &
  67. ((1 << PCS_FW_HEARTB_WIDTH) - 1));
  68. if (old_counter == 0)
  69. old_counter = counter;
  70. else if (counter != old_counter)
  71. break;
  72. if (time_after(jiffies, timeout))
  73. return -ETIMEDOUT;
  74. msleep(10);
  75. }
  76. /* Wait for firmware status to look good */
  77. for (;;) {
  78. reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS,
  79. PCS_UC8051_STATUS_REG);
  80. if (reg < 0)
  81. return reg;
  82. if ((reg &
  83. ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
  84. PCS_UC_STATUS_FW_SAVE)
  85. break;
  86. if (time_after(jiffies, timeout))
  87. return -ETIMEDOUT;
  88. msleep(100);
  89. }
  90. return 0;
  91. }
  92. /* Reset the PHYXS MMD. This is documented (for the Quake PHYs) as doing
  93. * a complete soft reset.
  94. */
  95. static int xfp_reset_phy(struct efx_nic *efx)
  96. {
  97. int rc;
  98. rc = mdio_clause45_reset_mmd(efx, MDIO_MMD_PHYXS,
  99. XFP_MAX_RESET_TIME / XFP_RESET_WAIT,
  100. XFP_RESET_WAIT);
  101. if (rc < 0)
  102. goto fail;
  103. if (efx->phy_type == PHY_TYPE_QT2025C) {
  104. rc = qt2025c_wait_reset(efx);
  105. if (rc < 0)
  106. goto fail;
  107. }
  108. /* Wait 250ms for the PHY to complete bootup */
  109. msleep(250);
  110. /* Check that all the MMDs we expect are present and responding. We
  111. * expect faults on some if the link is down, but not on the PHY XS */
  112. rc = mdio_clause45_check_mmds(efx, XFP_REQUIRED_DEVS,
  113. MDIO_MMDREG_DEVS_PHYXS);
  114. if (rc < 0)
  115. goto fail;
  116. efx->board_info.init_leds(efx);
  117. return rc;
  118. fail:
  119. EFX_ERR(efx, "PHY reset timed out\n");
  120. return rc;
  121. }
  122. static int xfp_phy_init(struct efx_nic *efx)
  123. {
  124. struct xfp_phy_data *phy_data;
  125. u32 devid = mdio_clause45_read_id(efx, MDIO_MMD_PHYXS);
  126. int rc;
  127. phy_data = kzalloc(sizeof(struct xfp_phy_data), GFP_KERNEL);
  128. if (!phy_data)
  129. return -ENOMEM;
  130. efx->phy_data = phy_data;
  131. EFX_INFO(efx, "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
  132. devid, mdio_id_oui(devid), mdio_id_model(devid),
  133. mdio_id_rev(devid));
  134. phy_data->phy_mode = efx->phy_mode;
  135. rc = xfp_reset_phy(efx);
  136. EFX_INFO(efx, "PHY init %s.\n",
  137. rc ? "failed" : "successful");
  138. if (rc < 0)
  139. goto fail;
  140. return 0;
  141. fail:
  142. kfree(efx->phy_data);
  143. efx->phy_data = NULL;
  144. return rc;
  145. }
  146. static void xfp_phy_clear_interrupt(struct efx_nic *efx)
  147. {
  148. xenpack_clear_lasi_irqs(efx);
  149. }
  150. static int xfp_link_ok(struct efx_nic *efx)
  151. {
  152. return mdio_clause45_links_ok(efx, XFP_REQUIRED_DEVS);
  153. }
  154. static void xfp_phy_poll(struct efx_nic *efx)
  155. {
  156. int link_up = xfp_link_ok(efx);
  157. /* Simulate a PHY event if link state has changed */
  158. if (link_up != efx->link_up)
  159. falcon_sim_phy_event(efx);
  160. }
  161. static void xfp_phy_reconfigure(struct efx_nic *efx)
  162. {
  163. struct xfp_phy_data *phy_data = efx->phy_data;
  164. if (efx->phy_type == PHY_TYPE_QT2025C) {
  165. /* There are several different register bits which can
  166. * disable TX (and save power) on direct-attach cables
  167. * or optical transceivers, varying somewhat between
  168. * firmware versions. Only 'static mode' appears to
  169. * cover everything. */
  170. mdio_clause45_set_flag(
  171. efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
  172. PMA_PMD_FTX_CTRL2_REG, PMA_PMD_FTX_STATIC_LBN,
  173. efx->phy_mode & PHY_MODE_TX_DISABLED ||
  174. efx->phy_mode & PHY_MODE_LOW_POWER ||
  175. efx->loopback_mode == LOOPBACK_PCS ||
  176. efx->loopback_mode == LOOPBACK_PMAPMD);
  177. } else {
  178. /* Reset the PHY when moving from tx off to tx on */
  179. if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
  180. (phy_data->phy_mode & PHY_MODE_TX_DISABLED))
  181. xfp_reset_phy(efx);
  182. mdio_clause45_transmit_disable(efx);
  183. }
  184. mdio_clause45_phy_reconfigure(efx);
  185. phy_data->phy_mode = efx->phy_mode;
  186. efx->link_up = xfp_link_ok(efx);
  187. efx->link_speed = 10000;
  188. efx->link_fd = true;
  189. efx->link_fc = efx->wanted_fc;
  190. }
  191. static void xfp_phy_fini(struct efx_nic *efx)
  192. {
  193. /* Clobber the LED if it was blinking */
  194. efx->board_info.blink(efx, false);
  195. /* Free the context block */
  196. kfree(efx->phy_data);
  197. efx->phy_data = NULL;
  198. }
  199. struct efx_phy_operations falcon_xfp_phy_ops = {
  200. .macs = EFX_XMAC,
  201. .init = xfp_phy_init,
  202. .reconfigure = xfp_phy_reconfigure,
  203. .poll = xfp_phy_poll,
  204. .fini = xfp_phy_fini,
  205. .clear_interrupt = xfp_phy_clear_interrupt,
  206. .get_settings = mdio_clause45_get_settings,
  207. .set_settings = mdio_clause45_set_settings,
  208. .mmds = XFP_REQUIRED_DEVS,
  209. .loopbacks = XFP_LOOPBACKS,
  210. };