falcon_xmac.c 12 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2006-2008 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/delay.h>
  11. #include "net_driver.h"
  12. #include "efx.h"
  13. #include "falcon.h"
  14. #include "falcon_hwdefs.h"
  15. #include "falcon_io.h"
  16. #include "mac.h"
  17. #include "mdio_10g.h"
  18. #include "phy.h"
  19. #include "boards.h"
  20. #include "workarounds.h"
  21. /**************************************************************************
  22. *
  23. * MAC operations
  24. *
  25. *************************************************************************/
  26. /* Configure the XAUI driver that is an output from Falcon */
  27. static void falcon_setup_xaui(struct efx_nic *efx)
  28. {
  29. efx_oword_t sdctl, txdrv;
  30. /* Move the XAUI into low power, unless there is no PHY, in
  31. * which case the XAUI will have to drive a cable. */
  32. if (efx->phy_type == PHY_TYPE_NONE)
  33. return;
  34. falcon_read(efx, &sdctl, XX_SD_CTL_REG);
  35. EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT);
  36. EFX_SET_OWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT);
  37. EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT);
  38. EFX_SET_OWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT);
  39. EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT);
  40. EFX_SET_OWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT);
  41. EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT);
  42. EFX_SET_OWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT);
  43. falcon_write(efx, &sdctl, XX_SD_CTL_REG);
  44. EFX_POPULATE_OWORD_8(txdrv,
  45. XX_DEQD, XX_TXDRV_DEQ_DEFAULT,
  46. XX_DEQC, XX_TXDRV_DEQ_DEFAULT,
  47. XX_DEQB, XX_TXDRV_DEQ_DEFAULT,
  48. XX_DEQA, XX_TXDRV_DEQ_DEFAULT,
  49. XX_DTXD, XX_TXDRV_DTX_DEFAULT,
  50. XX_DTXC, XX_TXDRV_DTX_DEFAULT,
  51. XX_DTXB, XX_TXDRV_DTX_DEFAULT,
  52. XX_DTXA, XX_TXDRV_DTX_DEFAULT);
  53. falcon_write(efx, &txdrv, XX_TXDRV_CTL_REG);
  54. }
  55. int falcon_reset_xaui(struct efx_nic *efx)
  56. {
  57. efx_oword_t reg;
  58. int count;
  59. EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1);
  60. falcon_write(efx, &reg, XX_PWR_RST_REG);
  61. /* Give some time for the link to establish */
  62. for (count = 0; count < 1000; count++) { /* wait upto 10ms */
  63. falcon_read(efx, &reg, XX_PWR_RST_REG);
  64. if (EFX_OWORD_FIELD(reg, XX_RST_XX_EN) == 0) {
  65. falcon_setup_xaui(efx);
  66. return 0;
  67. }
  68. udelay(10);
  69. }
  70. EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n");
  71. return -ETIMEDOUT;
  72. }
  73. static void falcon_mask_status_intr(struct efx_nic *efx, bool enable)
  74. {
  75. efx_oword_t reg;
  76. if ((falcon_rev(efx) != FALCON_REV_B0) || LOOPBACK_INTERNAL(efx))
  77. return;
  78. /* We expect xgmii faults if the wireside link is up */
  79. if (!EFX_WORKAROUND_5147(efx) || !efx->link_up)
  80. return;
  81. /* We can only use this interrupt to signal the negative edge of
  82. * xaui_align [we have to poll the positive edge]. */
  83. if (!efx->mac_up)
  84. return;
  85. /* Flush the ISR */
  86. if (enable)
  87. falcon_read(efx, &reg, XM_MGT_INT_REG_B0);
  88. EFX_POPULATE_OWORD_2(reg,
  89. XM_MSK_RMTFLT, !enable,
  90. XM_MSK_LCLFLT, !enable);
  91. falcon_write(efx, &reg, XM_MGT_INT_MSK_REG_B0);
  92. }
  93. /* Get status of XAUI link */
  94. bool falcon_xaui_link_ok(struct efx_nic *efx)
  95. {
  96. efx_oword_t reg;
  97. bool align_done, link_ok = false;
  98. int sync_status;
  99. if (LOOPBACK_INTERNAL(efx))
  100. return true;
  101. /* Read link status */
  102. falcon_read(efx, &reg, XX_CORE_STAT_REG);
  103. align_done = EFX_OWORD_FIELD(reg, XX_ALIGN_DONE);
  104. sync_status = EFX_OWORD_FIELD(reg, XX_SYNC_STAT);
  105. if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED))
  106. link_ok = true;
  107. /* Clear link status ready for next read */
  108. EFX_SET_OWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET);
  109. EFX_SET_OWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET);
  110. EFX_SET_OWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET);
  111. falcon_write(efx, &reg, XX_CORE_STAT_REG);
  112. /* If the link is up, then check the phy side of the xaui link */
  113. if (efx->link_up && link_ok)
  114. if (efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS))
  115. link_ok = mdio_clause45_phyxgxs_lane_sync(efx);
  116. return link_ok;
  117. }
  118. static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
  119. {
  120. unsigned int max_frame_len;
  121. efx_oword_t reg;
  122. bool rx_fc = !!(efx->link_fc & EFX_FC_RX);
  123. /* Configure MAC - cut-thru mode is hard wired on */
  124. EFX_POPULATE_DWORD_3(reg,
  125. XM_RX_JUMBO_MODE, 1,
  126. XM_TX_STAT_EN, 1,
  127. XM_RX_STAT_EN, 1);
  128. falcon_write(efx, &reg, XM_GLB_CFG_REG);
  129. /* Configure TX */
  130. EFX_POPULATE_DWORD_6(reg,
  131. XM_TXEN, 1,
  132. XM_TX_PRMBL, 1,
  133. XM_AUTO_PAD, 1,
  134. XM_TXCRC, 1,
  135. XM_FCNTL, 1,
  136. XM_IPG, 0x3);
  137. falcon_write(efx, &reg, XM_TX_CFG_REG);
  138. /* Configure RX */
  139. EFX_POPULATE_DWORD_5(reg,
  140. XM_RXEN, 1,
  141. XM_AUTO_DEPAD, 0,
  142. XM_ACPT_ALL_MCAST, 1,
  143. XM_ACPT_ALL_UCAST, efx->promiscuous,
  144. XM_PASS_CRC_ERR, 1);
  145. falcon_write(efx, &reg, XM_RX_CFG_REG);
  146. /* Set frame length */
  147. max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
  148. EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len);
  149. falcon_write(efx, &reg, XM_RX_PARAM_REG);
  150. EFX_POPULATE_DWORD_2(reg,
  151. XM_MAX_TX_FRM_SIZE, max_frame_len,
  152. XM_TX_JUMBO_MODE, 1);
  153. falcon_write(efx, &reg, XM_TX_PARAM_REG);
  154. EFX_POPULATE_DWORD_2(reg,
  155. XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
  156. XM_DIS_FCNTL, !rx_fc);
  157. falcon_write(efx, &reg, XM_FC_REG);
  158. /* Set MAC address */
  159. EFX_POPULATE_DWORD_4(reg,
  160. XM_ADR_0, efx->net_dev->dev_addr[0],
  161. XM_ADR_1, efx->net_dev->dev_addr[1],
  162. XM_ADR_2, efx->net_dev->dev_addr[2],
  163. XM_ADR_3, efx->net_dev->dev_addr[3]);
  164. falcon_write(efx, &reg, XM_ADR_LO_REG);
  165. EFX_POPULATE_DWORD_2(reg,
  166. XM_ADR_4, efx->net_dev->dev_addr[4],
  167. XM_ADR_5, efx->net_dev->dev_addr[5]);
  168. falcon_write(efx, &reg, XM_ADR_HI_REG);
  169. }
  170. static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
  171. {
  172. efx_oword_t reg;
  173. bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
  174. bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
  175. bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
  176. /* XGXS block is flaky and will need to be reset if moving
  177. * into our out of XGMII, XGXS or XAUI loopbacks. */
  178. if (EFX_WORKAROUND_5147(efx)) {
  179. bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
  180. bool reset_xgxs;
  181. falcon_read(efx, &reg, XX_CORE_STAT_REG);
  182. old_xgxs_loopback = EFX_OWORD_FIELD(reg, XX_XGXS_LB_EN);
  183. old_xgmii_loopback = EFX_OWORD_FIELD(reg, XX_XGMII_LB_EN);
  184. falcon_read(efx, &reg, XX_SD_CTL_REG);
  185. old_xaui_loopback = EFX_OWORD_FIELD(reg, XX_LPBKA);
  186. /* The PHY driver may have turned XAUI off */
  187. reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
  188. (xaui_loopback != old_xaui_loopback) ||
  189. (xgmii_loopback != old_xgmii_loopback));
  190. if (reset_xgxs)
  191. falcon_reset_xaui(efx);
  192. }
  193. falcon_read(efx, &reg, XX_CORE_STAT_REG);
  194. EFX_SET_OWORD_FIELD(reg, XX_FORCE_SIG,
  195. (xgxs_loopback || xaui_loopback) ?
  196. XX_FORCE_SIG_DECODE_FORCED : 0);
  197. EFX_SET_OWORD_FIELD(reg, XX_XGXS_LB_EN, xgxs_loopback);
  198. EFX_SET_OWORD_FIELD(reg, XX_XGMII_LB_EN, xgmii_loopback);
  199. falcon_write(efx, &reg, XX_CORE_STAT_REG);
  200. falcon_read(efx, &reg, XX_SD_CTL_REG);
  201. EFX_SET_OWORD_FIELD(reg, XX_LPBKD, xaui_loopback);
  202. EFX_SET_OWORD_FIELD(reg, XX_LPBKC, xaui_loopback);
  203. EFX_SET_OWORD_FIELD(reg, XX_LPBKB, xaui_loopback);
  204. EFX_SET_OWORD_FIELD(reg, XX_LPBKA, xaui_loopback);
  205. falcon_write(efx, &reg, XX_SD_CTL_REG);
  206. }
  207. /* Try and bring the Falcon side of the Falcon-Phy XAUI link fails
  208. * to come back up. Bash it until it comes back up */
  209. static void falcon_check_xaui_link_up(struct efx_nic *efx, int tries)
  210. {
  211. efx->mac_up = falcon_xaui_link_ok(efx);
  212. if ((efx->loopback_mode == LOOPBACK_NETWORK) ||
  213. efx_phy_mode_disabled(efx->phy_mode))
  214. /* XAUI link is expected to be down */
  215. return;
  216. while (!efx->mac_up && tries) {
  217. EFX_LOG(efx, "bashing xaui\n");
  218. falcon_reset_xaui(efx);
  219. udelay(200);
  220. efx->mac_up = falcon_xaui_link_ok(efx);
  221. --tries;
  222. }
  223. }
  224. static void falcon_reconfigure_xmac(struct efx_nic *efx)
  225. {
  226. falcon_mask_status_intr(efx, false);
  227. falcon_reconfigure_xgxs_core(efx);
  228. falcon_reconfigure_xmac_core(efx);
  229. falcon_reconfigure_mac_wrapper(efx);
  230. falcon_check_xaui_link_up(efx, 5);
  231. falcon_mask_status_intr(efx, true);
  232. }
  233. static void falcon_update_stats_xmac(struct efx_nic *efx)
  234. {
  235. struct efx_mac_stats *mac_stats = &efx->mac_stats;
  236. int rc;
  237. rc = falcon_dma_stats(efx, XgDmaDone_offset);
  238. if (rc)
  239. return;
  240. /* Update MAC stats from DMAed values */
  241. FALCON_STAT(efx, XgRxOctets, rx_bytes);
  242. FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
  243. FALCON_STAT(efx, XgRxPkts, rx_packets);
  244. FALCON_STAT(efx, XgRxPktsOK, rx_good);
  245. FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
  246. FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
  247. FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
  248. FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
  249. FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
  250. FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
  251. FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
  252. FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
  253. FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
  254. FALCON_STAT(efx, XgRxAlignError, rx_align_error);
  255. FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
  256. FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
  257. FALCON_STAT(efx, XgRxControlPkts, rx_control);
  258. FALCON_STAT(efx, XgRxPausePkts, rx_pause);
  259. FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
  260. FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
  261. FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
  262. FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
  263. FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
  264. FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
  265. FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
  266. FALCON_STAT(efx, XgRxLengthError, rx_length_error);
  267. FALCON_STAT(efx, XgTxPkts, tx_packets);
  268. FALCON_STAT(efx, XgTxOctets, tx_bytes);
  269. FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
  270. FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
  271. FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
  272. FALCON_STAT(efx, XgTxControlPkts, tx_control);
  273. FALCON_STAT(efx, XgTxPausePkts, tx_pause);
  274. FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
  275. FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
  276. FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
  277. FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
  278. FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
  279. FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
  280. FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
  281. FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
  282. FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
  283. FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
  284. FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
  285. FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
  286. /* Update derived statistics */
  287. mac_stats->tx_good_bytes =
  288. (mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
  289. mac_stats->tx_control * 64);
  290. mac_stats->rx_bad_bytes =
  291. (mac_stats->rx_bytes - mac_stats->rx_good_bytes -
  292. mac_stats->rx_control * 64);
  293. }
  294. static void falcon_xmac_irq(struct efx_nic *efx)
  295. {
  296. /* The XGMII link has a transient fault, which indicates either:
  297. * - there's a transient xgmii fault
  298. * - falcon's end of the xaui link may need a kick
  299. * - the wire-side link may have gone down, but the lasi/poll()
  300. * hasn't noticed yet.
  301. *
  302. * We only want to even bother polling XAUI if we're confident it's
  303. * not (1) or (3). In both cases, the only reliable way to spot this
  304. * is to wait a bit. We do this here by forcing the mac link state
  305. * to down, and waiting for the mac poll to come round and check
  306. */
  307. efx->mac_up = false;
  308. }
  309. static void falcon_poll_xmac(struct efx_nic *efx)
  310. {
  311. if (!EFX_WORKAROUND_5147(efx) || !efx->link_up || efx->mac_up)
  312. return;
  313. falcon_mask_status_intr(efx, false);
  314. falcon_check_xaui_link_up(efx, 1);
  315. falcon_mask_status_intr(efx, true);
  316. }
  317. struct efx_mac_operations falcon_xmac_operations = {
  318. .reconfigure = falcon_reconfigure_xmac,
  319. .update_stats = falcon_update_stats_xmac,
  320. .irq = falcon_xmac_irq,
  321. .poll = falcon_poll_xmac,
  322. };