rrunner.c 42 KB

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  1. /*
  2. * rrunner.c: Linux driver for the Essential RoadRunner HIPPI board.
  3. *
  4. * Copyright (C) 1998-2002 by Jes Sorensen, <jes@wildopensource.com>.
  5. *
  6. * Thanks to Essential Communication for providing us with hardware
  7. * and very comprehensive documentation without which I would not have
  8. * been able to write this driver. A special thank you to John Gibbon
  9. * for sorting out the legal issues, with the NDA, allowing the code to
  10. * be released under the GPL.
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. *
  17. * Thanks to Jayaram Bhat from ODS/Essential for fixing some of the
  18. * stupid bugs in my code.
  19. *
  20. * Softnet support and various other patches from Val Henson of
  21. * ODS/Essential.
  22. *
  23. * PCI DMA mapping code partly based on work by Francois Romieu.
  24. */
  25. #define DEBUG 1
  26. #define RX_DMA_SKBUFF 1
  27. #define PKT_COPY_THRESHOLD 512
  28. #include <linux/module.h>
  29. #include <linux/types.h>
  30. #include <linux/errno.h>
  31. #include <linux/ioport.h>
  32. #include <linux/pci.h>
  33. #include <linux/kernel.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/hippidevice.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/init.h>
  38. #include <linux/delay.h>
  39. #include <linux/mm.h>
  40. #include <net/sock.h>
  41. #include <asm/system.h>
  42. #include <asm/cache.h>
  43. #include <asm/byteorder.h>
  44. #include <asm/io.h>
  45. #include <asm/irq.h>
  46. #include <asm/uaccess.h>
  47. #define rr_if_busy(dev) netif_queue_stopped(dev)
  48. #define rr_if_running(dev) netif_running(dev)
  49. #include "rrunner.h"
  50. #define RUN_AT(x) (jiffies + (x))
  51. MODULE_AUTHOR("Jes Sorensen <jes@wildopensource.com>");
  52. MODULE_DESCRIPTION("Essential RoadRunner HIPPI driver");
  53. MODULE_LICENSE("GPL");
  54. static char version[] __devinitdata = "rrunner.c: v0.50 11/11/2002 Jes Sorensen (jes@wildopensource.com)\n";
  55. static const struct net_device_ops rr_netdev_ops = {
  56. .ndo_open = rr_open,
  57. .ndo_stop = rr_close,
  58. .ndo_do_ioctl = rr_ioctl,
  59. .ndo_start_xmit = rr_start_xmit,
  60. .ndo_change_mtu = hippi_change_mtu,
  61. .ndo_set_mac_address = hippi_mac_addr,
  62. };
  63. /*
  64. * Implementation notes:
  65. *
  66. * The DMA engine only allows for DMA within physical 64KB chunks of
  67. * memory. The current approach of the driver (and stack) is to use
  68. * linear blocks of memory for the skbuffs. However, as the data block
  69. * is always the first part of the skb and skbs are 2^n aligned so we
  70. * are guarantted to get the whole block within one 64KB align 64KB
  71. * chunk.
  72. *
  73. * On the long term, relying on being able to allocate 64KB linear
  74. * chunks of memory is not feasible and the skb handling code and the
  75. * stack will need to know about I/O vectors or something similar.
  76. */
  77. static int __devinit rr_init_one(struct pci_dev *pdev,
  78. const struct pci_device_id *ent)
  79. {
  80. struct net_device *dev;
  81. static int version_disp;
  82. u8 pci_latency;
  83. struct rr_private *rrpriv;
  84. void *tmpptr;
  85. dma_addr_t ring_dma;
  86. int ret = -ENOMEM;
  87. dev = alloc_hippi_dev(sizeof(struct rr_private));
  88. if (!dev)
  89. goto out3;
  90. ret = pci_enable_device(pdev);
  91. if (ret) {
  92. ret = -ENODEV;
  93. goto out2;
  94. }
  95. rrpriv = netdev_priv(dev);
  96. SET_NETDEV_DEV(dev, &pdev->dev);
  97. if (pci_request_regions(pdev, "rrunner")) {
  98. ret = -EIO;
  99. goto out;
  100. }
  101. pci_set_drvdata(pdev, dev);
  102. rrpriv->pci_dev = pdev;
  103. spin_lock_init(&rrpriv->lock);
  104. dev->irq = pdev->irq;
  105. dev->netdev_ops = &rr_netdev_ops;
  106. dev->base_addr = pci_resource_start(pdev, 0);
  107. /* display version info if adapter is found */
  108. if (!version_disp) {
  109. /* set display flag to TRUE so that */
  110. /* we only display this string ONCE */
  111. version_disp = 1;
  112. printk(version);
  113. }
  114. pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
  115. if (pci_latency <= 0x58){
  116. pci_latency = 0x58;
  117. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, pci_latency);
  118. }
  119. pci_set_master(pdev);
  120. printk(KERN_INFO "%s: Essential RoadRunner serial HIPPI "
  121. "at 0x%08lx, irq %i, PCI latency %i\n", dev->name,
  122. dev->base_addr, dev->irq, pci_latency);
  123. /*
  124. * Remap the regs into kernel space.
  125. */
  126. rrpriv->regs = ioremap(dev->base_addr, 0x1000);
  127. if (!rrpriv->regs){
  128. printk(KERN_ERR "%s: Unable to map I/O register, "
  129. "RoadRunner will be disabled.\n", dev->name);
  130. ret = -EIO;
  131. goto out;
  132. }
  133. tmpptr = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
  134. rrpriv->tx_ring = tmpptr;
  135. rrpriv->tx_ring_dma = ring_dma;
  136. if (!tmpptr) {
  137. ret = -ENOMEM;
  138. goto out;
  139. }
  140. tmpptr = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
  141. rrpriv->rx_ring = tmpptr;
  142. rrpriv->rx_ring_dma = ring_dma;
  143. if (!tmpptr) {
  144. ret = -ENOMEM;
  145. goto out;
  146. }
  147. tmpptr = pci_alloc_consistent(pdev, EVT_RING_SIZE, &ring_dma);
  148. rrpriv->evt_ring = tmpptr;
  149. rrpriv->evt_ring_dma = ring_dma;
  150. if (!tmpptr) {
  151. ret = -ENOMEM;
  152. goto out;
  153. }
  154. /*
  155. * Don't access any register before this point!
  156. */
  157. #ifdef __BIG_ENDIAN
  158. writel(readl(&rrpriv->regs->HostCtrl) | NO_SWAP,
  159. &rrpriv->regs->HostCtrl);
  160. #endif
  161. /*
  162. * Need to add a case for little-endian 64-bit hosts here.
  163. */
  164. rr_init(dev);
  165. dev->base_addr = 0;
  166. ret = register_netdev(dev);
  167. if (ret)
  168. goto out;
  169. return 0;
  170. out:
  171. if (rrpriv->rx_ring)
  172. pci_free_consistent(pdev, RX_TOTAL_SIZE, rrpriv->rx_ring,
  173. rrpriv->rx_ring_dma);
  174. if (rrpriv->tx_ring)
  175. pci_free_consistent(pdev, TX_TOTAL_SIZE, rrpriv->tx_ring,
  176. rrpriv->tx_ring_dma);
  177. if (rrpriv->regs)
  178. iounmap(rrpriv->regs);
  179. if (pdev) {
  180. pci_release_regions(pdev);
  181. pci_set_drvdata(pdev, NULL);
  182. }
  183. out2:
  184. free_netdev(dev);
  185. out3:
  186. return ret;
  187. }
  188. static void __devexit rr_remove_one (struct pci_dev *pdev)
  189. {
  190. struct net_device *dev = pci_get_drvdata(pdev);
  191. if (dev) {
  192. struct rr_private *rr = netdev_priv(dev);
  193. if (!(readl(&rr->regs->HostCtrl) & NIC_HALTED)){
  194. printk(KERN_ERR "%s: trying to unload running NIC\n",
  195. dev->name);
  196. writel(HALT_NIC, &rr->regs->HostCtrl);
  197. }
  198. pci_free_consistent(pdev, EVT_RING_SIZE, rr->evt_ring,
  199. rr->evt_ring_dma);
  200. pci_free_consistent(pdev, RX_TOTAL_SIZE, rr->rx_ring,
  201. rr->rx_ring_dma);
  202. pci_free_consistent(pdev, TX_TOTAL_SIZE, rr->tx_ring,
  203. rr->tx_ring_dma);
  204. unregister_netdev(dev);
  205. iounmap(rr->regs);
  206. free_netdev(dev);
  207. pci_release_regions(pdev);
  208. pci_disable_device(pdev);
  209. pci_set_drvdata(pdev, NULL);
  210. }
  211. }
  212. /*
  213. * Commands are considered to be slow, thus there is no reason to
  214. * inline this.
  215. */
  216. static void rr_issue_cmd(struct rr_private *rrpriv, struct cmd *cmd)
  217. {
  218. struct rr_regs __iomem *regs;
  219. u32 idx;
  220. regs = rrpriv->regs;
  221. /*
  222. * This is temporary - it will go away in the final version.
  223. * We probably also want to make this function inline.
  224. */
  225. if (readl(&regs->HostCtrl) & NIC_HALTED){
  226. printk("issuing command for halted NIC, code 0x%x, "
  227. "HostCtrl %08x\n", cmd->code, readl(&regs->HostCtrl));
  228. if (readl(&regs->Mode) & FATAL_ERR)
  229. printk("error codes Fail1 %02x, Fail2 %02x\n",
  230. readl(&regs->Fail1), readl(&regs->Fail2));
  231. }
  232. idx = rrpriv->info->cmd_ctrl.pi;
  233. writel(*(u32*)(cmd), &regs->CmdRing[idx]);
  234. wmb();
  235. idx = (idx - 1) % CMD_RING_ENTRIES;
  236. rrpriv->info->cmd_ctrl.pi = idx;
  237. wmb();
  238. if (readl(&regs->Mode) & FATAL_ERR)
  239. printk("error code %02x\n", readl(&regs->Fail1));
  240. }
  241. /*
  242. * Reset the board in a sensible manner. The NIC is already halted
  243. * when we get here and a spin-lock is held.
  244. */
  245. static int rr_reset(struct net_device *dev)
  246. {
  247. struct rr_private *rrpriv;
  248. struct rr_regs __iomem *regs;
  249. u32 start_pc;
  250. int i;
  251. rrpriv = netdev_priv(dev);
  252. regs = rrpriv->regs;
  253. rr_load_firmware(dev);
  254. writel(0x01000000, &regs->TX_state);
  255. writel(0xff800000, &regs->RX_state);
  256. writel(0, &regs->AssistState);
  257. writel(CLEAR_INTA, &regs->LocalCtrl);
  258. writel(0x01, &regs->BrkPt);
  259. writel(0, &regs->Timer);
  260. writel(0, &regs->TimerRef);
  261. writel(RESET_DMA, &regs->DmaReadState);
  262. writel(RESET_DMA, &regs->DmaWriteState);
  263. writel(0, &regs->DmaWriteHostHi);
  264. writel(0, &regs->DmaWriteHostLo);
  265. writel(0, &regs->DmaReadHostHi);
  266. writel(0, &regs->DmaReadHostLo);
  267. writel(0, &regs->DmaReadLen);
  268. writel(0, &regs->DmaWriteLen);
  269. writel(0, &regs->DmaWriteLcl);
  270. writel(0, &regs->DmaWriteIPchecksum);
  271. writel(0, &regs->DmaReadLcl);
  272. writel(0, &regs->DmaReadIPchecksum);
  273. writel(0, &regs->PciState);
  274. #if (BITS_PER_LONG == 64) && defined __LITTLE_ENDIAN
  275. writel(SWAP_DATA | PTR64BIT | PTR_WD_SWAP, &regs->Mode);
  276. #elif (BITS_PER_LONG == 64)
  277. writel(SWAP_DATA | PTR64BIT | PTR_WD_NOSWAP, &regs->Mode);
  278. #else
  279. writel(SWAP_DATA | PTR32BIT | PTR_WD_NOSWAP, &regs->Mode);
  280. #endif
  281. #if 0
  282. /*
  283. * Don't worry, this is just black magic.
  284. */
  285. writel(0xdf000, &regs->RxBase);
  286. writel(0xdf000, &regs->RxPrd);
  287. writel(0xdf000, &regs->RxCon);
  288. writel(0xce000, &regs->TxBase);
  289. writel(0xce000, &regs->TxPrd);
  290. writel(0xce000, &regs->TxCon);
  291. writel(0, &regs->RxIndPro);
  292. writel(0, &regs->RxIndCon);
  293. writel(0, &regs->RxIndRef);
  294. writel(0, &regs->TxIndPro);
  295. writel(0, &regs->TxIndCon);
  296. writel(0, &regs->TxIndRef);
  297. writel(0xcc000, &regs->pad10[0]);
  298. writel(0, &regs->DrCmndPro);
  299. writel(0, &regs->DrCmndCon);
  300. writel(0, &regs->DwCmndPro);
  301. writel(0, &regs->DwCmndCon);
  302. writel(0, &regs->DwCmndRef);
  303. writel(0, &regs->DrDataPro);
  304. writel(0, &regs->DrDataCon);
  305. writel(0, &regs->DrDataRef);
  306. writel(0, &regs->DwDataPro);
  307. writel(0, &regs->DwDataCon);
  308. writel(0, &regs->DwDataRef);
  309. #endif
  310. writel(0xffffffff, &regs->MbEvent);
  311. writel(0, &regs->Event);
  312. writel(0, &regs->TxPi);
  313. writel(0, &regs->IpRxPi);
  314. writel(0, &regs->EvtCon);
  315. writel(0, &regs->EvtPrd);
  316. rrpriv->info->evt_ctrl.pi = 0;
  317. for (i = 0; i < CMD_RING_ENTRIES; i++)
  318. writel(0, &regs->CmdRing[i]);
  319. /*
  320. * Why 32 ? is this not cache line size dependent?
  321. */
  322. writel(RBURST_64|WBURST_64, &regs->PciState);
  323. wmb();
  324. start_pc = rr_read_eeprom_word(rrpriv,
  325. offsetof(struct eeprom, rncd_info.FwStart));
  326. #if (DEBUG > 1)
  327. printk("%s: Executing firmware at address 0x%06x\n",
  328. dev->name, start_pc);
  329. #endif
  330. writel(start_pc + 0x800, &regs->Pc);
  331. wmb();
  332. udelay(5);
  333. writel(start_pc, &regs->Pc);
  334. wmb();
  335. return 0;
  336. }
  337. /*
  338. * Read a string from the EEPROM.
  339. */
  340. static unsigned int rr_read_eeprom(struct rr_private *rrpriv,
  341. unsigned long offset,
  342. unsigned char *buf,
  343. unsigned long length)
  344. {
  345. struct rr_regs __iomem *regs = rrpriv->regs;
  346. u32 misc, io, host, i;
  347. io = readl(&regs->ExtIo);
  348. writel(0, &regs->ExtIo);
  349. misc = readl(&regs->LocalCtrl);
  350. writel(0, &regs->LocalCtrl);
  351. host = readl(&regs->HostCtrl);
  352. writel(host | HALT_NIC, &regs->HostCtrl);
  353. mb();
  354. for (i = 0; i < length; i++){
  355. writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase);
  356. mb();
  357. buf[i] = (readl(&regs->WinData) >> 24) & 0xff;
  358. mb();
  359. }
  360. writel(host, &regs->HostCtrl);
  361. writel(misc, &regs->LocalCtrl);
  362. writel(io, &regs->ExtIo);
  363. mb();
  364. return i;
  365. }
  366. /*
  367. * Shortcut to read one word (4 bytes) out of the EEPROM and convert
  368. * it to our CPU byte-order.
  369. */
  370. static u32 rr_read_eeprom_word(struct rr_private *rrpriv,
  371. size_t offset)
  372. {
  373. __be32 word;
  374. if ((rr_read_eeprom(rrpriv, offset,
  375. (unsigned char *)&word, 4) == 4))
  376. return be32_to_cpu(word);
  377. return 0;
  378. }
  379. /*
  380. * Write a string to the EEPROM.
  381. *
  382. * This is only called when the firmware is not running.
  383. */
  384. static unsigned int write_eeprom(struct rr_private *rrpriv,
  385. unsigned long offset,
  386. unsigned char *buf,
  387. unsigned long length)
  388. {
  389. struct rr_regs __iomem *regs = rrpriv->regs;
  390. u32 misc, io, data, i, j, ready, error = 0;
  391. io = readl(&regs->ExtIo);
  392. writel(0, &regs->ExtIo);
  393. misc = readl(&regs->LocalCtrl);
  394. writel(ENABLE_EEPROM_WRITE, &regs->LocalCtrl);
  395. mb();
  396. for (i = 0; i < length; i++){
  397. writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase);
  398. mb();
  399. data = buf[i] << 24;
  400. /*
  401. * Only try to write the data if it is not the same
  402. * value already.
  403. */
  404. if ((readl(&regs->WinData) & 0xff000000) != data){
  405. writel(data, &regs->WinData);
  406. ready = 0;
  407. j = 0;
  408. mb();
  409. while(!ready){
  410. udelay(20);
  411. if ((readl(&regs->WinData) & 0xff000000) ==
  412. data)
  413. ready = 1;
  414. mb();
  415. if (j++ > 5000){
  416. printk("data mismatch: %08x, "
  417. "WinData %08x\n", data,
  418. readl(&regs->WinData));
  419. ready = 1;
  420. error = 1;
  421. }
  422. }
  423. }
  424. }
  425. writel(misc, &regs->LocalCtrl);
  426. writel(io, &regs->ExtIo);
  427. mb();
  428. return error;
  429. }
  430. static int __devinit rr_init(struct net_device *dev)
  431. {
  432. struct rr_private *rrpriv;
  433. struct rr_regs __iomem *regs;
  434. u32 sram_size, rev;
  435. rrpriv = netdev_priv(dev);
  436. regs = rrpriv->regs;
  437. rev = readl(&regs->FwRev);
  438. rrpriv->fw_rev = rev;
  439. if (rev > 0x00020024)
  440. printk(" Firmware revision: %i.%i.%i\n", (rev >> 16),
  441. ((rev >> 8) & 0xff), (rev & 0xff));
  442. else if (rev >= 0x00020000) {
  443. printk(" Firmware revision: %i.%i.%i (2.0.37 or "
  444. "later is recommended)\n", (rev >> 16),
  445. ((rev >> 8) & 0xff), (rev & 0xff));
  446. }else{
  447. printk(" Firmware revision too old: %i.%i.%i, please "
  448. "upgrade to 2.0.37 or later.\n",
  449. (rev >> 16), ((rev >> 8) & 0xff), (rev & 0xff));
  450. }
  451. #if (DEBUG > 2)
  452. printk(" Maximum receive rings %i\n", readl(&regs->MaxRxRng));
  453. #endif
  454. /*
  455. * Read the hardware address from the eeprom. The HW address
  456. * is not really necessary for HIPPI but awfully convenient.
  457. * The pointer arithmetic to put it in dev_addr is ugly, but
  458. * Donald Becker does it this way for the GigE version of this
  459. * card and it's shorter and more portable than any
  460. * other method I've seen. -VAL
  461. */
  462. *(__be16 *)(dev->dev_addr) =
  463. htons(rr_read_eeprom_word(rrpriv, offsetof(struct eeprom, manf.BoardULA)));
  464. *(__be32 *)(dev->dev_addr+2) =
  465. htonl(rr_read_eeprom_word(rrpriv, offsetof(struct eeprom, manf.BoardULA[4])));
  466. printk(" MAC: %pM\n", dev->dev_addr);
  467. sram_size = rr_read_eeprom_word(rrpriv, 8);
  468. printk(" SRAM size 0x%06x\n", sram_size);
  469. return 0;
  470. }
  471. static int rr_init1(struct net_device *dev)
  472. {
  473. struct rr_private *rrpriv;
  474. struct rr_regs __iomem *regs;
  475. unsigned long myjif, flags;
  476. struct cmd cmd;
  477. u32 hostctrl;
  478. int ecode = 0;
  479. short i;
  480. rrpriv = netdev_priv(dev);
  481. regs = rrpriv->regs;
  482. spin_lock_irqsave(&rrpriv->lock, flags);
  483. hostctrl = readl(&regs->HostCtrl);
  484. writel(hostctrl | HALT_NIC | RR_CLEAR_INT, &regs->HostCtrl);
  485. wmb();
  486. if (hostctrl & PARITY_ERR){
  487. printk("%s: Parity error halting NIC - this is serious!\n",
  488. dev->name);
  489. spin_unlock_irqrestore(&rrpriv->lock, flags);
  490. ecode = -EFAULT;
  491. goto error;
  492. }
  493. set_rxaddr(regs, rrpriv->rx_ctrl_dma);
  494. set_infoaddr(regs, rrpriv->info_dma);
  495. rrpriv->info->evt_ctrl.entry_size = sizeof(struct event);
  496. rrpriv->info->evt_ctrl.entries = EVT_RING_ENTRIES;
  497. rrpriv->info->evt_ctrl.mode = 0;
  498. rrpriv->info->evt_ctrl.pi = 0;
  499. set_rraddr(&rrpriv->info->evt_ctrl.rngptr, rrpriv->evt_ring_dma);
  500. rrpriv->info->cmd_ctrl.entry_size = sizeof(struct cmd);
  501. rrpriv->info->cmd_ctrl.entries = CMD_RING_ENTRIES;
  502. rrpriv->info->cmd_ctrl.mode = 0;
  503. rrpriv->info->cmd_ctrl.pi = 15;
  504. for (i = 0; i < CMD_RING_ENTRIES; i++) {
  505. writel(0, &regs->CmdRing[i]);
  506. }
  507. for (i = 0; i < TX_RING_ENTRIES; i++) {
  508. rrpriv->tx_ring[i].size = 0;
  509. set_rraddr(&rrpriv->tx_ring[i].addr, 0);
  510. rrpriv->tx_skbuff[i] = NULL;
  511. }
  512. rrpriv->info->tx_ctrl.entry_size = sizeof(struct tx_desc);
  513. rrpriv->info->tx_ctrl.entries = TX_RING_ENTRIES;
  514. rrpriv->info->tx_ctrl.mode = 0;
  515. rrpriv->info->tx_ctrl.pi = 0;
  516. set_rraddr(&rrpriv->info->tx_ctrl.rngptr, rrpriv->tx_ring_dma);
  517. /*
  518. * Set dirty_tx before we start receiving interrupts, otherwise
  519. * the interrupt handler might think it is supposed to process
  520. * tx ints before we are up and running, which may cause a null
  521. * pointer access in the int handler.
  522. */
  523. rrpriv->tx_full = 0;
  524. rrpriv->cur_rx = 0;
  525. rrpriv->dirty_rx = rrpriv->dirty_tx = 0;
  526. rr_reset(dev);
  527. /* Tuning values */
  528. writel(0x5000, &regs->ConRetry);
  529. writel(0x100, &regs->ConRetryTmr);
  530. writel(0x500000, &regs->ConTmout);
  531. writel(0x60, &regs->IntrTmr);
  532. writel(0x500000, &regs->TxDataMvTimeout);
  533. writel(0x200000, &regs->RxDataMvTimeout);
  534. writel(0x80, &regs->WriteDmaThresh);
  535. writel(0x80, &regs->ReadDmaThresh);
  536. rrpriv->fw_running = 0;
  537. wmb();
  538. hostctrl &= ~(HALT_NIC | INVALID_INST_B | PARITY_ERR);
  539. writel(hostctrl, &regs->HostCtrl);
  540. wmb();
  541. spin_unlock_irqrestore(&rrpriv->lock, flags);
  542. for (i = 0; i < RX_RING_ENTRIES; i++) {
  543. struct sk_buff *skb;
  544. dma_addr_t addr;
  545. rrpriv->rx_ring[i].mode = 0;
  546. skb = alloc_skb(dev->mtu + HIPPI_HLEN, GFP_ATOMIC);
  547. if (!skb) {
  548. printk(KERN_WARNING "%s: Unable to allocate memory "
  549. "for receive ring - halting NIC\n", dev->name);
  550. ecode = -ENOMEM;
  551. goto error;
  552. }
  553. rrpriv->rx_skbuff[i] = skb;
  554. addr = pci_map_single(rrpriv->pci_dev, skb->data,
  555. dev->mtu + HIPPI_HLEN, PCI_DMA_FROMDEVICE);
  556. /*
  557. * Sanity test to see if we conflict with the DMA
  558. * limitations of the Roadrunner.
  559. */
  560. if ((((unsigned long)skb->data) & 0xfff) > ~65320)
  561. printk("skb alloc error\n");
  562. set_rraddr(&rrpriv->rx_ring[i].addr, addr);
  563. rrpriv->rx_ring[i].size = dev->mtu + HIPPI_HLEN;
  564. }
  565. rrpriv->rx_ctrl[4].entry_size = sizeof(struct rx_desc);
  566. rrpriv->rx_ctrl[4].entries = RX_RING_ENTRIES;
  567. rrpriv->rx_ctrl[4].mode = 8;
  568. rrpriv->rx_ctrl[4].pi = 0;
  569. wmb();
  570. set_rraddr(&rrpriv->rx_ctrl[4].rngptr, rrpriv->rx_ring_dma);
  571. udelay(1000);
  572. /*
  573. * Now start the FirmWare.
  574. */
  575. cmd.code = C_START_FW;
  576. cmd.ring = 0;
  577. cmd.index = 0;
  578. rr_issue_cmd(rrpriv, &cmd);
  579. /*
  580. * Give the FirmWare time to chew on the `get running' command.
  581. */
  582. myjif = jiffies + 5 * HZ;
  583. while (time_before(jiffies, myjif) && !rrpriv->fw_running)
  584. cpu_relax();
  585. netif_start_queue(dev);
  586. return ecode;
  587. error:
  588. /*
  589. * We might have gotten here because we are out of memory,
  590. * make sure we release everything we allocated before failing
  591. */
  592. for (i = 0; i < RX_RING_ENTRIES; i++) {
  593. struct sk_buff *skb = rrpriv->rx_skbuff[i];
  594. if (skb) {
  595. pci_unmap_single(rrpriv->pci_dev,
  596. rrpriv->rx_ring[i].addr.addrlo,
  597. dev->mtu + HIPPI_HLEN,
  598. PCI_DMA_FROMDEVICE);
  599. rrpriv->rx_ring[i].size = 0;
  600. set_rraddr(&rrpriv->rx_ring[i].addr, 0);
  601. dev_kfree_skb(skb);
  602. rrpriv->rx_skbuff[i] = NULL;
  603. }
  604. }
  605. return ecode;
  606. }
  607. /*
  608. * All events are considered to be slow (RX/TX ints do not generate
  609. * events) and are handled here, outside the main interrupt handler,
  610. * to reduce the size of the handler.
  611. */
  612. static u32 rr_handle_event(struct net_device *dev, u32 prodidx, u32 eidx)
  613. {
  614. struct rr_private *rrpriv;
  615. struct rr_regs __iomem *regs;
  616. u32 tmp;
  617. rrpriv = netdev_priv(dev);
  618. regs = rrpriv->regs;
  619. while (prodidx != eidx){
  620. switch (rrpriv->evt_ring[eidx].code){
  621. case E_NIC_UP:
  622. tmp = readl(&regs->FwRev);
  623. printk(KERN_INFO "%s: Firmware revision %i.%i.%i "
  624. "up and running\n", dev->name,
  625. (tmp >> 16), ((tmp >> 8) & 0xff), (tmp & 0xff));
  626. rrpriv->fw_running = 1;
  627. writel(RX_RING_ENTRIES - 1, &regs->IpRxPi);
  628. wmb();
  629. break;
  630. case E_LINK_ON:
  631. printk(KERN_INFO "%s: Optical link ON\n", dev->name);
  632. break;
  633. case E_LINK_OFF:
  634. printk(KERN_INFO "%s: Optical link OFF\n", dev->name);
  635. break;
  636. case E_RX_IDLE:
  637. printk(KERN_WARNING "%s: RX data not moving\n",
  638. dev->name);
  639. goto drop;
  640. case E_WATCHDOG:
  641. printk(KERN_INFO "%s: The watchdog is here to see "
  642. "us\n", dev->name);
  643. break;
  644. case E_INTERN_ERR:
  645. printk(KERN_ERR "%s: HIPPI Internal NIC error\n",
  646. dev->name);
  647. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  648. &regs->HostCtrl);
  649. wmb();
  650. break;
  651. case E_HOST_ERR:
  652. printk(KERN_ERR "%s: Host software error\n",
  653. dev->name);
  654. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  655. &regs->HostCtrl);
  656. wmb();
  657. break;
  658. /*
  659. * TX events.
  660. */
  661. case E_CON_REJ:
  662. printk(KERN_WARNING "%s: Connection rejected\n",
  663. dev->name);
  664. dev->stats.tx_aborted_errors++;
  665. break;
  666. case E_CON_TMOUT:
  667. printk(KERN_WARNING "%s: Connection timeout\n",
  668. dev->name);
  669. break;
  670. case E_DISC_ERR:
  671. printk(KERN_WARNING "%s: HIPPI disconnect error\n",
  672. dev->name);
  673. dev->stats.tx_aborted_errors++;
  674. break;
  675. case E_INT_PRTY:
  676. printk(KERN_ERR "%s: HIPPI Internal Parity error\n",
  677. dev->name);
  678. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  679. &regs->HostCtrl);
  680. wmb();
  681. break;
  682. case E_TX_IDLE:
  683. printk(KERN_WARNING "%s: Transmitter idle\n",
  684. dev->name);
  685. break;
  686. case E_TX_LINK_DROP:
  687. printk(KERN_WARNING "%s: Link lost during transmit\n",
  688. dev->name);
  689. dev->stats.tx_aborted_errors++;
  690. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  691. &regs->HostCtrl);
  692. wmb();
  693. break;
  694. case E_TX_INV_RNG:
  695. printk(KERN_ERR "%s: Invalid send ring block\n",
  696. dev->name);
  697. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  698. &regs->HostCtrl);
  699. wmb();
  700. break;
  701. case E_TX_INV_BUF:
  702. printk(KERN_ERR "%s: Invalid send buffer address\n",
  703. dev->name);
  704. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  705. &regs->HostCtrl);
  706. wmb();
  707. break;
  708. case E_TX_INV_DSC:
  709. printk(KERN_ERR "%s: Invalid descriptor address\n",
  710. dev->name);
  711. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  712. &regs->HostCtrl);
  713. wmb();
  714. break;
  715. /*
  716. * RX events.
  717. */
  718. case E_RX_RNG_OUT:
  719. printk(KERN_INFO "%s: Receive ring full\n", dev->name);
  720. break;
  721. case E_RX_PAR_ERR:
  722. printk(KERN_WARNING "%s: Receive parity error\n",
  723. dev->name);
  724. goto drop;
  725. case E_RX_LLRC_ERR:
  726. printk(KERN_WARNING "%s: Receive LLRC error\n",
  727. dev->name);
  728. goto drop;
  729. case E_PKT_LN_ERR:
  730. printk(KERN_WARNING "%s: Receive packet length "
  731. "error\n", dev->name);
  732. goto drop;
  733. case E_DTA_CKSM_ERR:
  734. printk(KERN_WARNING "%s: Data checksum error\n",
  735. dev->name);
  736. goto drop;
  737. case E_SHT_BST:
  738. printk(KERN_WARNING "%s: Unexpected short burst "
  739. "error\n", dev->name);
  740. goto drop;
  741. case E_STATE_ERR:
  742. printk(KERN_WARNING "%s: Recv. state transition"
  743. " error\n", dev->name);
  744. goto drop;
  745. case E_UNEXP_DATA:
  746. printk(KERN_WARNING "%s: Unexpected data error\n",
  747. dev->name);
  748. goto drop;
  749. case E_LST_LNK_ERR:
  750. printk(KERN_WARNING "%s: Link lost error\n",
  751. dev->name);
  752. goto drop;
  753. case E_FRM_ERR:
  754. printk(KERN_WARNING "%s: Framming Error\n",
  755. dev->name);
  756. goto drop;
  757. case E_FLG_SYN_ERR:
  758. printk(KERN_WARNING "%s: Flag sync. lost during "
  759. "packet\n", dev->name);
  760. goto drop;
  761. case E_RX_INV_BUF:
  762. printk(KERN_ERR "%s: Invalid receive buffer "
  763. "address\n", dev->name);
  764. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  765. &regs->HostCtrl);
  766. wmb();
  767. break;
  768. case E_RX_INV_DSC:
  769. printk(KERN_ERR "%s: Invalid receive descriptor "
  770. "address\n", dev->name);
  771. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  772. &regs->HostCtrl);
  773. wmb();
  774. break;
  775. case E_RNG_BLK:
  776. printk(KERN_ERR "%s: Invalid ring block\n",
  777. dev->name);
  778. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  779. &regs->HostCtrl);
  780. wmb();
  781. break;
  782. drop:
  783. /* Label packet to be dropped.
  784. * Actual dropping occurs in rx
  785. * handling.
  786. *
  787. * The index of packet we get to drop is
  788. * the index of the packet following
  789. * the bad packet. -kbf
  790. */
  791. {
  792. u16 index = rrpriv->evt_ring[eidx].index;
  793. index = (index + (RX_RING_ENTRIES - 1)) %
  794. RX_RING_ENTRIES;
  795. rrpriv->rx_ring[index].mode |=
  796. (PACKET_BAD | PACKET_END);
  797. }
  798. break;
  799. default:
  800. printk(KERN_WARNING "%s: Unhandled event 0x%02x\n",
  801. dev->name, rrpriv->evt_ring[eidx].code);
  802. }
  803. eidx = (eidx + 1) % EVT_RING_ENTRIES;
  804. }
  805. rrpriv->info->evt_ctrl.pi = eidx;
  806. wmb();
  807. return eidx;
  808. }
  809. static void rx_int(struct net_device *dev, u32 rxlimit, u32 index)
  810. {
  811. struct rr_private *rrpriv = netdev_priv(dev);
  812. struct rr_regs __iomem *regs = rrpriv->regs;
  813. do {
  814. struct rx_desc *desc;
  815. u32 pkt_len;
  816. desc = &(rrpriv->rx_ring[index]);
  817. pkt_len = desc->size;
  818. #if (DEBUG > 2)
  819. printk("index %i, rxlimit %i\n", index, rxlimit);
  820. printk("len %x, mode %x\n", pkt_len, desc->mode);
  821. #endif
  822. if ( (rrpriv->rx_ring[index].mode & PACKET_BAD) == PACKET_BAD){
  823. dev->stats.rx_dropped++;
  824. goto defer;
  825. }
  826. if (pkt_len > 0){
  827. struct sk_buff *skb, *rx_skb;
  828. rx_skb = rrpriv->rx_skbuff[index];
  829. if (pkt_len < PKT_COPY_THRESHOLD) {
  830. skb = alloc_skb(pkt_len, GFP_ATOMIC);
  831. if (skb == NULL){
  832. printk(KERN_WARNING "%s: Unable to allocate skb (%i bytes), deferring packet\n", dev->name, pkt_len);
  833. dev->stats.rx_dropped++;
  834. goto defer;
  835. } else {
  836. pci_dma_sync_single_for_cpu(rrpriv->pci_dev,
  837. desc->addr.addrlo,
  838. pkt_len,
  839. PCI_DMA_FROMDEVICE);
  840. memcpy(skb_put(skb, pkt_len),
  841. rx_skb->data, pkt_len);
  842. pci_dma_sync_single_for_device(rrpriv->pci_dev,
  843. desc->addr.addrlo,
  844. pkt_len,
  845. PCI_DMA_FROMDEVICE);
  846. }
  847. }else{
  848. struct sk_buff *newskb;
  849. newskb = alloc_skb(dev->mtu + HIPPI_HLEN,
  850. GFP_ATOMIC);
  851. if (newskb){
  852. dma_addr_t addr;
  853. pci_unmap_single(rrpriv->pci_dev,
  854. desc->addr.addrlo, dev->mtu +
  855. HIPPI_HLEN, PCI_DMA_FROMDEVICE);
  856. skb = rx_skb;
  857. skb_put(skb, pkt_len);
  858. rrpriv->rx_skbuff[index] = newskb;
  859. addr = pci_map_single(rrpriv->pci_dev,
  860. newskb->data,
  861. dev->mtu + HIPPI_HLEN,
  862. PCI_DMA_FROMDEVICE);
  863. set_rraddr(&desc->addr, addr);
  864. } else {
  865. printk("%s: Out of memory, deferring "
  866. "packet\n", dev->name);
  867. dev->stats.rx_dropped++;
  868. goto defer;
  869. }
  870. }
  871. skb->protocol = hippi_type_trans(skb, dev);
  872. netif_rx(skb); /* send it up */
  873. dev->stats.rx_packets++;
  874. dev->stats.rx_bytes += pkt_len;
  875. }
  876. defer:
  877. desc->mode = 0;
  878. desc->size = dev->mtu + HIPPI_HLEN;
  879. if ((index & 7) == 7)
  880. writel(index, &regs->IpRxPi);
  881. index = (index + 1) % RX_RING_ENTRIES;
  882. } while(index != rxlimit);
  883. rrpriv->cur_rx = index;
  884. wmb();
  885. }
  886. static irqreturn_t rr_interrupt(int irq, void *dev_id)
  887. {
  888. struct rr_private *rrpriv;
  889. struct rr_regs __iomem *regs;
  890. struct net_device *dev = (struct net_device *)dev_id;
  891. u32 prodidx, rxindex, eidx, txcsmr, rxlimit, txcon;
  892. rrpriv = netdev_priv(dev);
  893. regs = rrpriv->regs;
  894. if (!(readl(&regs->HostCtrl) & RR_INT))
  895. return IRQ_NONE;
  896. spin_lock(&rrpriv->lock);
  897. prodidx = readl(&regs->EvtPrd);
  898. txcsmr = (prodidx >> 8) & 0xff;
  899. rxlimit = (prodidx >> 16) & 0xff;
  900. prodidx &= 0xff;
  901. #if (DEBUG > 2)
  902. printk("%s: interrupt, prodidx = %i, eidx = %i\n", dev->name,
  903. prodidx, rrpriv->info->evt_ctrl.pi);
  904. #endif
  905. /*
  906. * Order here is important. We must handle events
  907. * before doing anything else in order to catch
  908. * such things as LLRC errors, etc -kbf
  909. */
  910. eidx = rrpriv->info->evt_ctrl.pi;
  911. if (prodidx != eidx)
  912. eidx = rr_handle_event(dev, prodidx, eidx);
  913. rxindex = rrpriv->cur_rx;
  914. if (rxindex != rxlimit)
  915. rx_int(dev, rxlimit, rxindex);
  916. txcon = rrpriv->dirty_tx;
  917. if (txcsmr != txcon) {
  918. do {
  919. /* Due to occational firmware TX producer/consumer out
  920. * of sync. error need to check entry in ring -kbf
  921. */
  922. if(rrpriv->tx_skbuff[txcon]){
  923. struct tx_desc *desc;
  924. struct sk_buff *skb;
  925. desc = &(rrpriv->tx_ring[txcon]);
  926. skb = rrpriv->tx_skbuff[txcon];
  927. dev->stats.tx_packets++;
  928. dev->stats.tx_bytes += skb->len;
  929. pci_unmap_single(rrpriv->pci_dev,
  930. desc->addr.addrlo, skb->len,
  931. PCI_DMA_TODEVICE);
  932. dev_kfree_skb_irq(skb);
  933. rrpriv->tx_skbuff[txcon] = NULL;
  934. desc->size = 0;
  935. set_rraddr(&rrpriv->tx_ring[txcon].addr, 0);
  936. desc->mode = 0;
  937. }
  938. txcon = (txcon + 1) % TX_RING_ENTRIES;
  939. } while (txcsmr != txcon);
  940. wmb();
  941. rrpriv->dirty_tx = txcon;
  942. if (rrpriv->tx_full && rr_if_busy(dev) &&
  943. (((rrpriv->info->tx_ctrl.pi + 1) % TX_RING_ENTRIES)
  944. != rrpriv->dirty_tx)){
  945. rrpriv->tx_full = 0;
  946. netif_wake_queue(dev);
  947. }
  948. }
  949. eidx |= ((txcsmr << 8) | (rxlimit << 16));
  950. writel(eidx, &regs->EvtCon);
  951. wmb();
  952. spin_unlock(&rrpriv->lock);
  953. return IRQ_HANDLED;
  954. }
  955. static inline void rr_raz_tx(struct rr_private *rrpriv,
  956. struct net_device *dev)
  957. {
  958. int i;
  959. for (i = 0; i < TX_RING_ENTRIES; i++) {
  960. struct sk_buff *skb = rrpriv->tx_skbuff[i];
  961. if (skb) {
  962. struct tx_desc *desc = &(rrpriv->tx_ring[i]);
  963. pci_unmap_single(rrpriv->pci_dev, desc->addr.addrlo,
  964. skb->len, PCI_DMA_TODEVICE);
  965. desc->size = 0;
  966. set_rraddr(&desc->addr, 0);
  967. dev_kfree_skb(skb);
  968. rrpriv->tx_skbuff[i] = NULL;
  969. }
  970. }
  971. }
  972. static inline void rr_raz_rx(struct rr_private *rrpriv,
  973. struct net_device *dev)
  974. {
  975. int i;
  976. for (i = 0; i < RX_RING_ENTRIES; i++) {
  977. struct sk_buff *skb = rrpriv->rx_skbuff[i];
  978. if (skb) {
  979. struct rx_desc *desc = &(rrpriv->rx_ring[i]);
  980. pci_unmap_single(rrpriv->pci_dev, desc->addr.addrlo,
  981. dev->mtu + HIPPI_HLEN, PCI_DMA_FROMDEVICE);
  982. desc->size = 0;
  983. set_rraddr(&desc->addr, 0);
  984. dev_kfree_skb(skb);
  985. rrpriv->rx_skbuff[i] = NULL;
  986. }
  987. }
  988. }
  989. static void rr_timer(unsigned long data)
  990. {
  991. struct net_device *dev = (struct net_device *)data;
  992. struct rr_private *rrpriv = netdev_priv(dev);
  993. struct rr_regs __iomem *regs = rrpriv->regs;
  994. unsigned long flags;
  995. if (readl(&regs->HostCtrl) & NIC_HALTED){
  996. printk("%s: Restarting nic\n", dev->name);
  997. memset(rrpriv->rx_ctrl, 0, 256 * sizeof(struct ring_ctrl));
  998. memset(rrpriv->info, 0, sizeof(struct rr_info));
  999. wmb();
  1000. rr_raz_tx(rrpriv, dev);
  1001. rr_raz_rx(rrpriv, dev);
  1002. if (rr_init1(dev)) {
  1003. spin_lock_irqsave(&rrpriv->lock, flags);
  1004. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,
  1005. &regs->HostCtrl);
  1006. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1007. }
  1008. }
  1009. rrpriv->timer.expires = RUN_AT(5*HZ);
  1010. add_timer(&rrpriv->timer);
  1011. }
  1012. static int rr_open(struct net_device *dev)
  1013. {
  1014. struct rr_private *rrpriv = netdev_priv(dev);
  1015. struct pci_dev *pdev = rrpriv->pci_dev;
  1016. struct rr_regs __iomem *regs;
  1017. int ecode = 0;
  1018. unsigned long flags;
  1019. dma_addr_t dma_addr;
  1020. regs = rrpriv->regs;
  1021. if (rrpriv->fw_rev < 0x00020000) {
  1022. printk(KERN_WARNING "%s: trying to configure device with "
  1023. "obsolete firmware\n", dev->name);
  1024. ecode = -EBUSY;
  1025. goto error;
  1026. }
  1027. rrpriv->rx_ctrl = pci_alloc_consistent(pdev,
  1028. 256 * sizeof(struct ring_ctrl),
  1029. &dma_addr);
  1030. if (!rrpriv->rx_ctrl) {
  1031. ecode = -ENOMEM;
  1032. goto error;
  1033. }
  1034. rrpriv->rx_ctrl_dma = dma_addr;
  1035. memset(rrpriv->rx_ctrl, 0, 256*sizeof(struct ring_ctrl));
  1036. rrpriv->info = pci_alloc_consistent(pdev, sizeof(struct rr_info),
  1037. &dma_addr);
  1038. if (!rrpriv->info) {
  1039. ecode = -ENOMEM;
  1040. goto error;
  1041. }
  1042. rrpriv->info_dma = dma_addr;
  1043. memset(rrpriv->info, 0, sizeof(struct rr_info));
  1044. wmb();
  1045. spin_lock_irqsave(&rrpriv->lock, flags);
  1046. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl);
  1047. readl(&regs->HostCtrl);
  1048. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1049. if (request_irq(dev->irq, rr_interrupt, IRQF_SHARED, dev->name, dev)) {
  1050. printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
  1051. dev->name, dev->irq);
  1052. ecode = -EAGAIN;
  1053. goto error;
  1054. }
  1055. if ((ecode = rr_init1(dev)))
  1056. goto error;
  1057. /* Set the timer to switch to check for link beat and perhaps switch
  1058. to an alternate media type. */
  1059. init_timer(&rrpriv->timer);
  1060. rrpriv->timer.expires = RUN_AT(5*HZ); /* 5 sec. watchdog */
  1061. rrpriv->timer.data = (unsigned long)dev;
  1062. rrpriv->timer.function = &rr_timer; /* timer handler */
  1063. add_timer(&rrpriv->timer);
  1064. netif_start_queue(dev);
  1065. return ecode;
  1066. error:
  1067. spin_lock_irqsave(&rrpriv->lock, flags);
  1068. writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl);
  1069. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1070. if (rrpriv->info) {
  1071. pci_free_consistent(pdev, sizeof(struct rr_info), rrpriv->info,
  1072. rrpriv->info_dma);
  1073. rrpriv->info = NULL;
  1074. }
  1075. if (rrpriv->rx_ctrl) {
  1076. pci_free_consistent(pdev, sizeof(struct ring_ctrl),
  1077. rrpriv->rx_ctrl, rrpriv->rx_ctrl_dma);
  1078. rrpriv->rx_ctrl = NULL;
  1079. }
  1080. netif_stop_queue(dev);
  1081. return ecode;
  1082. }
  1083. static void rr_dump(struct net_device *dev)
  1084. {
  1085. struct rr_private *rrpriv;
  1086. struct rr_regs __iomem *regs;
  1087. u32 index, cons;
  1088. short i;
  1089. int len;
  1090. rrpriv = netdev_priv(dev);
  1091. regs = rrpriv->regs;
  1092. printk("%s: dumping NIC TX rings\n", dev->name);
  1093. printk("RxPrd %08x, TxPrd %02x, EvtPrd %08x, TxPi %02x, TxCtrlPi %02x\n",
  1094. readl(&regs->RxPrd), readl(&regs->TxPrd),
  1095. readl(&regs->EvtPrd), readl(&regs->TxPi),
  1096. rrpriv->info->tx_ctrl.pi);
  1097. printk("Error code 0x%x\n", readl(&regs->Fail1));
  1098. index = (((readl(&regs->EvtPrd) >> 8) & 0xff ) - 1) % EVT_RING_ENTRIES;
  1099. cons = rrpriv->dirty_tx;
  1100. printk("TX ring index %i, TX consumer %i\n",
  1101. index, cons);
  1102. if (rrpriv->tx_skbuff[index]){
  1103. len = min_t(int, 0x80, rrpriv->tx_skbuff[index]->len);
  1104. printk("skbuff for index %i is valid - dumping data (0x%x bytes - DMA len 0x%x)\n", index, len, rrpriv->tx_ring[index].size);
  1105. for (i = 0; i < len; i++){
  1106. if (!(i & 7))
  1107. printk("\n");
  1108. printk("%02x ", (unsigned char) rrpriv->tx_skbuff[index]->data[i]);
  1109. }
  1110. printk("\n");
  1111. }
  1112. if (rrpriv->tx_skbuff[cons]){
  1113. len = min_t(int, 0x80, rrpriv->tx_skbuff[cons]->len);
  1114. printk("skbuff for cons %i is valid - dumping data (0x%x bytes - skbuff len 0x%x)\n", cons, len, rrpriv->tx_skbuff[cons]->len);
  1115. printk("mode 0x%x, size 0x%x,\n phys %08Lx, skbuff-addr %08lx, truesize 0x%x\n",
  1116. rrpriv->tx_ring[cons].mode,
  1117. rrpriv->tx_ring[cons].size,
  1118. (unsigned long long) rrpriv->tx_ring[cons].addr.addrlo,
  1119. (unsigned long)rrpriv->tx_skbuff[cons]->data,
  1120. (unsigned int)rrpriv->tx_skbuff[cons]->truesize);
  1121. for (i = 0; i < len; i++){
  1122. if (!(i & 7))
  1123. printk("\n");
  1124. printk("%02x ", (unsigned char)rrpriv->tx_ring[cons].size);
  1125. }
  1126. printk("\n");
  1127. }
  1128. printk("dumping TX ring info:\n");
  1129. for (i = 0; i < TX_RING_ENTRIES; i++)
  1130. printk("mode 0x%x, size 0x%x, phys-addr %08Lx\n",
  1131. rrpriv->tx_ring[i].mode,
  1132. rrpriv->tx_ring[i].size,
  1133. (unsigned long long) rrpriv->tx_ring[i].addr.addrlo);
  1134. }
  1135. static int rr_close(struct net_device *dev)
  1136. {
  1137. struct rr_private *rrpriv;
  1138. struct rr_regs __iomem *regs;
  1139. unsigned long flags;
  1140. u32 tmp;
  1141. short i;
  1142. netif_stop_queue(dev);
  1143. rrpriv = netdev_priv(dev);
  1144. regs = rrpriv->regs;
  1145. /*
  1146. * Lock to make sure we are not cleaning up while another CPU
  1147. * is handling interrupts.
  1148. */
  1149. spin_lock_irqsave(&rrpriv->lock, flags);
  1150. tmp = readl(&regs->HostCtrl);
  1151. if (tmp & NIC_HALTED){
  1152. printk("%s: NIC already halted\n", dev->name);
  1153. rr_dump(dev);
  1154. }else{
  1155. tmp |= HALT_NIC | RR_CLEAR_INT;
  1156. writel(tmp, &regs->HostCtrl);
  1157. readl(&regs->HostCtrl);
  1158. }
  1159. rrpriv->fw_running = 0;
  1160. del_timer_sync(&rrpriv->timer);
  1161. writel(0, &regs->TxPi);
  1162. writel(0, &regs->IpRxPi);
  1163. writel(0, &regs->EvtCon);
  1164. writel(0, &regs->EvtPrd);
  1165. for (i = 0; i < CMD_RING_ENTRIES; i++)
  1166. writel(0, &regs->CmdRing[i]);
  1167. rrpriv->info->tx_ctrl.entries = 0;
  1168. rrpriv->info->cmd_ctrl.pi = 0;
  1169. rrpriv->info->evt_ctrl.pi = 0;
  1170. rrpriv->rx_ctrl[4].entries = 0;
  1171. rr_raz_tx(rrpriv, dev);
  1172. rr_raz_rx(rrpriv, dev);
  1173. pci_free_consistent(rrpriv->pci_dev, 256 * sizeof(struct ring_ctrl),
  1174. rrpriv->rx_ctrl, rrpriv->rx_ctrl_dma);
  1175. rrpriv->rx_ctrl = NULL;
  1176. pci_free_consistent(rrpriv->pci_dev, sizeof(struct rr_info),
  1177. rrpriv->info, rrpriv->info_dma);
  1178. rrpriv->info = NULL;
  1179. free_irq(dev->irq, dev);
  1180. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1181. return 0;
  1182. }
  1183. static int rr_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1184. {
  1185. struct rr_private *rrpriv = netdev_priv(dev);
  1186. struct rr_regs __iomem *regs = rrpriv->regs;
  1187. struct hippi_cb *hcb = (struct hippi_cb *) skb->cb;
  1188. struct ring_ctrl *txctrl;
  1189. unsigned long flags;
  1190. u32 index, len = skb->len;
  1191. u32 *ifield;
  1192. struct sk_buff *new_skb;
  1193. if (readl(&regs->Mode) & FATAL_ERR)
  1194. printk("error codes Fail1 %02x, Fail2 %02x\n",
  1195. readl(&regs->Fail1), readl(&regs->Fail2));
  1196. /*
  1197. * We probably need to deal with tbusy here to prevent overruns.
  1198. */
  1199. if (skb_headroom(skb) < 8){
  1200. printk("incoming skb too small - reallocating\n");
  1201. if (!(new_skb = dev_alloc_skb(len + 8))) {
  1202. dev_kfree_skb(skb);
  1203. netif_wake_queue(dev);
  1204. return -EBUSY;
  1205. }
  1206. skb_reserve(new_skb, 8);
  1207. skb_put(new_skb, len);
  1208. skb_copy_from_linear_data(skb, new_skb->data, len);
  1209. dev_kfree_skb(skb);
  1210. skb = new_skb;
  1211. }
  1212. ifield = (u32 *)skb_push(skb, 8);
  1213. ifield[0] = 0;
  1214. ifield[1] = hcb->ifield;
  1215. /*
  1216. * We don't need the lock before we are actually going to start
  1217. * fiddling with the control blocks.
  1218. */
  1219. spin_lock_irqsave(&rrpriv->lock, flags);
  1220. txctrl = &rrpriv->info->tx_ctrl;
  1221. index = txctrl->pi;
  1222. rrpriv->tx_skbuff[index] = skb;
  1223. set_rraddr(&rrpriv->tx_ring[index].addr, pci_map_single(
  1224. rrpriv->pci_dev, skb->data, len + 8, PCI_DMA_TODEVICE));
  1225. rrpriv->tx_ring[index].size = len + 8; /* include IFIELD */
  1226. rrpriv->tx_ring[index].mode = PACKET_START | PACKET_END;
  1227. txctrl->pi = (index + 1) % TX_RING_ENTRIES;
  1228. wmb();
  1229. writel(txctrl->pi, &regs->TxPi);
  1230. if (txctrl->pi == rrpriv->dirty_tx){
  1231. rrpriv->tx_full = 1;
  1232. netif_stop_queue(dev);
  1233. }
  1234. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1235. dev->trans_start = jiffies;
  1236. return 0;
  1237. }
  1238. /*
  1239. * Read the firmware out of the EEPROM and put it into the SRAM
  1240. * (or from user space - later)
  1241. *
  1242. * This operation requires the NIC to be halted and is performed with
  1243. * interrupts disabled and with the spinlock hold.
  1244. */
  1245. static int rr_load_firmware(struct net_device *dev)
  1246. {
  1247. struct rr_private *rrpriv;
  1248. struct rr_regs __iomem *regs;
  1249. size_t eptr, segptr;
  1250. int i, j;
  1251. u32 localctrl, sptr, len, tmp;
  1252. u32 p2len, p2size, nr_seg, revision, io, sram_size;
  1253. rrpriv = netdev_priv(dev);
  1254. regs = rrpriv->regs;
  1255. if (dev->flags & IFF_UP)
  1256. return -EBUSY;
  1257. if (!(readl(&regs->HostCtrl) & NIC_HALTED)){
  1258. printk("%s: Trying to load firmware to a running NIC.\n",
  1259. dev->name);
  1260. return -EBUSY;
  1261. }
  1262. localctrl = readl(&regs->LocalCtrl);
  1263. writel(0, &regs->LocalCtrl);
  1264. writel(0, &regs->EvtPrd);
  1265. writel(0, &regs->RxPrd);
  1266. writel(0, &regs->TxPrd);
  1267. /*
  1268. * First wipe the entire SRAM, otherwise we might run into all
  1269. * kinds of trouble ... sigh, this took almost all afternoon
  1270. * to track down ;-(
  1271. */
  1272. io = readl(&regs->ExtIo);
  1273. writel(0, &regs->ExtIo);
  1274. sram_size = rr_read_eeprom_word(rrpriv, 8);
  1275. for (i = 200; i < sram_size / 4; i++){
  1276. writel(i * 4, &regs->WinBase);
  1277. mb();
  1278. writel(0, &regs->WinData);
  1279. mb();
  1280. }
  1281. writel(io, &regs->ExtIo);
  1282. mb();
  1283. eptr = rr_read_eeprom_word(rrpriv,
  1284. offsetof(struct eeprom, rncd_info.AddrRunCodeSegs));
  1285. eptr = ((eptr & 0x1fffff) >> 3);
  1286. p2len = rr_read_eeprom_word(rrpriv, 0x83*4);
  1287. p2len = (p2len << 2);
  1288. p2size = rr_read_eeprom_word(rrpriv, 0x84*4);
  1289. p2size = ((p2size & 0x1fffff) >> 3);
  1290. if ((eptr < p2size) || (eptr > (p2size + p2len))){
  1291. printk("%s: eptr is invalid\n", dev->name);
  1292. goto out;
  1293. }
  1294. revision = rr_read_eeprom_word(rrpriv,
  1295. offsetof(struct eeprom, manf.HeaderFmt));
  1296. if (revision != 1){
  1297. printk("%s: invalid firmware format (%i)\n",
  1298. dev->name, revision);
  1299. goto out;
  1300. }
  1301. nr_seg = rr_read_eeprom_word(rrpriv, eptr);
  1302. eptr +=4;
  1303. #if (DEBUG > 1)
  1304. printk("%s: nr_seg %i\n", dev->name, nr_seg);
  1305. #endif
  1306. for (i = 0; i < nr_seg; i++){
  1307. sptr = rr_read_eeprom_word(rrpriv, eptr);
  1308. eptr += 4;
  1309. len = rr_read_eeprom_word(rrpriv, eptr);
  1310. eptr += 4;
  1311. segptr = rr_read_eeprom_word(rrpriv, eptr);
  1312. segptr = ((segptr & 0x1fffff) >> 3);
  1313. eptr += 4;
  1314. #if (DEBUG > 1)
  1315. printk("%s: segment %i, sram address %06x, length %04x, segptr %06x\n",
  1316. dev->name, i, sptr, len, segptr);
  1317. #endif
  1318. for (j = 0; j < len; j++){
  1319. tmp = rr_read_eeprom_word(rrpriv, segptr);
  1320. writel(sptr, &regs->WinBase);
  1321. mb();
  1322. writel(tmp, &regs->WinData);
  1323. mb();
  1324. segptr += 4;
  1325. sptr += 4;
  1326. }
  1327. }
  1328. out:
  1329. writel(localctrl, &regs->LocalCtrl);
  1330. mb();
  1331. return 0;
  1332. }
  1333. static int rr_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  1334. {
  1335. struct rr_private *rrpriv;
  1336. unsigned char *image, *oldimage;
  1337. unsigned long flags;
  1338. unsigned int i;
  1339. int error = -EOPNOTSUPP;
  1340. rrpriv = netdev_priv(dev);
  1341. switch(cmd){
  1342. case SIOCRRGFW:
  1343. if (!capable(CAP_SYS_RAWIO)){
  1344. return -EPERM;
  1345. }
  1346. image = kmalloc(EEPROM_WORDS * sizeof(u32), GFP_KERNEL);
  1347. if (!image){
  1348. printk(KERN_ERR "%s: Unable to allocate memory "
  1349. "for EEPROM image\n", dev->name);
  1350. return -ENOMEM;
  1351. }
  1352. if (rrpriv->fw_running){
  1353. printk("%s: Firmware already running\n", dev->name);
  1354. error = -EPERM;
  1355. goto gf_out;
  1356. }
  1357. spin_lock_irqsave(&rrpriv->lock, flags);
  1358. i = rr_read_eeprom(rrpriv, 0, image, EEPROM_BYTES);
  1359. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1360. if (i != EEPROM_BYTES){
  1361. printk(KERN_ERR "%s: Error reading EEPROM\n",
  1362. dev->name);
  1363. error = -EFAULT;
  1364. goto gf_out;
  1365. }
  1366. error = copy_to_user(rq->ifr_data, image, EEPROM_BYTES);
  1367. if (error)
  1368. error = -EFAULT;
  1369. gf_out:
  1370. kfree(image);
  1371. return error;
  1372. case SIOCRRPFW:
  1373. if (!capable(CAP_SYS_RAWIO)){
  1374. return -EPERM;
  1375. }
  1376. image = kmalloc(EEPROM_WORDS * sizeof(u32), GFP_KERNEL);
  1377. oldimage = kmalloc(EEPROM_WORDS * sizeof(u32), GFP_KERNEL);
  1378. if (!image || !oldimage) {
  1379. printk(KERN_ERR "%s: Unable to allocate memory "
  1380. "for EEPROM image\n", dev->name);
  1381. error = -ENOMEM;
  1382. goto wf_out;
  1383. }
  1384. error = copy_from_user(image, rq->ifr_data, EEPROM_BYTES);
  1385. if (error) {
  1386. error = -EFAULT;
  1387. goto wf_out;
  1388. }
  1389. if (rrpriv->fw_running){
  1390. printk("%s: Firmware already running\n", dev->name);
  1391. error = -EPERM;
  1392. goto wf_out;
  1393. }
  1394. printk("%s: Updating EEPROM firmware\n", dev->name);
  1395. spin_lock_irqsave(&rrpriv->lock, flags);
  1396. error = write_eeprom(rrpriv, 0, image, EEPROM_BYTES);
  1397. if (error)
  1398. printk(KERN_ERR "%s: Error writing EEPROM\n",
  1399. dev->name);
  1400. i = rr_read_eeprom(rrpriv, 0, oldimage, EEPROM_BYTES);
  1401. spin_unlock_irqrestore(&rrpriv->lock, flags);
  1402. if (i != EEPROM_BYTES)
  1403. printk(KERN_ERR "%s: Error reading back EEPROM "
  1404. "image\n", dev->name);
  1405. error = memcmp(image, oldimage, EEPROM_BYTES);
  1406. if (error){
  1407. printk(KERN_ERR "%s: Error verifying EEPROM image\n",
  1408. dev->name);
  1409. error = -EFAULT;
  1410. }
  1411. wf_out:
  1412. kfree(oldimage);
  1413. kfree(image);
  1414. return error;
  1415. case SIOCRRID:
  1416. return put_user(0x52523032, (int __user *)rq->ifr_data);
  1417. default:
  1418. return error;
  1419. }
  1420. }
  1421. static struct pci_device_id rr_pci_tbl[] = {
  1422. { PCI_VENDOR_ID_ESSENTIAL, PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER,
  1423. PCI_ANY_ID, PCI_ANY_ID, },
  1424. { 0,}
  1425. };
  1426. MODULE_DEVICE_TABLE(pci, rr_pci_tbl);
  1427. static struct pci_driver rr_driver = {
  1428. .name = "rrunner",
  1429. .id_table = rr_pci_tbl,
  1430. .probe = rr_init_one,
  1431. .remove = __devexit_p(rr_remove_one),
  1432. };
  1433. static int __init rr_init_module(void)
  1434. {
  1435. return pci_register_driver(&rr_driver);
  1436. }
  1437. static void __exit rr_cleanup_module(void)
  1438. {
  1439. pci_unregister_driver(&rr_driver);
  1440. }
  1441. module_init(rr_init_module);
  1442. module_exit(rr_cleanup_module);