marvell.c 13 KB

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  1. /*
  2. * drivers/net/phy/marvell.c
  3. *
  4. * Driver for Marvell PHYs
  5. *
  6. * Author: Andy Fleming
  7. *
  8. * Copyright (c) 2004 Freescale Semiconductor, Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. *
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/string.h>
  18. #include <linux/errno.h>
  19. #include <linux/unistd.h>
  20. #include <linux/slab.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/init.h>
  23. #include <linux/delay.h>
  24. #include <linux/netdevice.h>
  25. #include <linux/etherdevice.h>
  26. #include <linux/skbuff.h>
  27. #include <linux/spinlock.h>
  28. #include <linux/mm.h>
  29. #include <linux/module.h>
  30. #include <linux/mii.h>
  31. #include <linux/ethtool.h>
  32. #include <linux/phy.h>
  33. #include <asm/io.h>
  34. #include <asm/irq.h>
  35. #include <asm/uaccess.h>
  36. #define MII_M1011_IEVENT 0x13
  37. #define MII_M1011_IEVENT_CLEAR 0x0000
  38. #define MII_M1011_IMASK 0x12
  39. #define MII_M1011_IMASK_INIT 0x6400
  40. #define MII_M1011_IMASK_CLEAR 0x0000
  41. #define MII_M1011_PHY_SCR 0x10
  42. #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
  43. #define MII_M1145_PHY_EXT_CR 0x14
  44. #define MII_M1145_RGMII_RX_DELAY 0x0080
  45. #define MII_M1145_RGMII_TX_DELAY 0x0002
  46. #define M1145_DEV_FLAGS_RESISTANCE 0x00000001
  47. #define MII_M1111_PHY_LED_CONTROL 0x18
  48. #define MII_M1111_PHY_LED_DIRECT 0x4100
  49. #define MII_M1111_PHY_LED_COMBINE 0x411c
  50. #define MII_M1111_PHY_EXT_CR 0x14
  51. #define MII_M1111_RX_DELAY 0x80
  52. #define MII_M1111_TX_DELAY 0x2
  53. #define MII_M1111_PHY_EXT_SR 0x1b
  54. #define MII_M1111_HWCFG_MODE_MASK 0xf
  55. #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
  56. #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
  57. #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
  58. #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
  59. #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
  60. #define MII_M1111_COPPER 0
  61. #define MII_M1111_FIBER 1
  62. #define MII_88E1121_PHY_LED_CTRL 16
  63. #define MII_88E1121_PHY_LED_PAGE 3
  64. #define MII_88E1121_PHY_LED_DEF 0x0030
  65. #define MII_88E1121_PHY_PAGE 22
  66. #define MII_M1011_PHY_STATUS 0x11
  67. #define MII_M1011_PHY_STATUS_1000 0x8000
  68. #define MII_M1011_PHY_STATUS_100 0x4000
  69. #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
  70. #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
  71. #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
  72. #define MII_M1011_PHY_STATUS_LINK 0x0400
  73. MODULE_DESCRIPTION("Marvell PHY driver");
  74. MODULE_AUTHOR("Andy Fleming");
  75. MODULE_LICENSE("GPL");
  76. static int marvell_ack_interrupt(struct phy_device *phydev)
  77. {
  78. int err;
  79. /* Clear the interrupts by reading the reg */
  80. err = phy_read(phydev, MII_M1011_IEVENT);
  81. if (err < 0)
  82. return err;
  83. return 0;
  84. }
  85. static int marvell_config_intr(struct phy_device *phydev)
  86. {
  87. int err;
  88. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  89. err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
  90. else
  91. err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
  92. return err;
  93. }
  94. static int marvell_config_aneg(struct phy_device *phydev)
  95. {
  96. int err;
  97. /* The Marvell PHY has an errata which requires
  98. * that certain registers get written in order
  99. * to restart autonegotiation */
  100. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  101. if (err < 0)
  102. return err;
  103. err = phy_write(phydev, 0x1d, 0x1f);
  104. if (err < 0)
  105. return err;
  106. err = phy_write(phydev, 0x1e, 0x200c);
  107. if (err < 0)
  108. return err;
  109. err = phy_write(phydev, 0x1d, 0x5);
  110. if (err < 0)
  111. return err;
  112. err = phy_write(phydev, 0x1e, 0);
  113. if (err < 0)
  114. return err;
  115. err = phy_write(phydev, 0x1e, 0x100);
  116. if (err < 0)
  117. return err;
  118. err = phy_write(phydev, MII_M1011_PHY_SCR,
  119. MII_M1011_PHY_SCR_AUTO_CROSS);
  120. if (err < 0)
  121. return err;
  122. err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
  123. MII_M1111_PHY_LED_DIRECT);
  124. if (err < 0)
  125. return err;
  126. err = genphy_config_aneg(phydev);
  127. return err;
  128. }
  129. static int m88e1121_config_aneg(struct phy_device *phydev)
  130. {
  131. int err, temp;
  132. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  133. if (err < 0)
  134. return err;
  135. err = phy_write(phydev, MII_M1011_PHY_SCR,
  136. MII_M1011_PHY_SCR_AUTO_CROSS);
  137. if (err < 0)
  138. return err;
  139. temp = phy_read(phydev, MII_88E1121_PHY_PAGE);
  140. phy_write(phydev, MII_88E1121_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
  141. phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF);
  142. phy_write(phydev, MII_88E1121_PHY_PAGE, temp);
  143. err = genphy_config_aneg(phydev);
  144. return err;
  145. }
  146. static int m88e1111_config_init(struct phy_device *phydev)
  147. {
  148. int err;
  149. int temp;
  150. /* Enable Fiber/Copper auto selection */
  151. temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
  152. temp &= ~MII_M1111_HWCFG_FIBER_COPPER_AUTO;
  153. phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
  154. temp = phy_read(phydev, MII_BMCR);
  155. temp |= BMCR_RESET;
  156. phy_write(phydev, MII_BMCR, temp);
  157. if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
  158. (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
  159. (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
  160. (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
  161. temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
  162. if (temp < 0)
  163. return temp;
  164. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
  165. temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
  166. } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
  167. temp &= ~MII_M1111_TX_DELAY;
  168. temp |= MII_M1111_RX_DELAY;
  169. } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
  170. temp &= ~MII_M1111_RX_DELAY;
  171. temp |= MII_M1111_TX_DELAY;
  172. }
  173. err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
  174. if (err < 0)
  175. return err;
  176. temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
  177. if (temp < 0)
  178. return temp;
  179. temp &= ~(MII_M1111_HWCFG_MODE_MASK);
  180. if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
  181. temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
  182. else
  183. temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
  184. err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
  185. if (err < 0)
  186. return err;
  187. }
  188. if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
  189. temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
  190. if (temp < 0)
  191. return temp;
  192. temp &= ~(MII_M1111_HWCFG_MODE_MASK);
  193. temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
  194. err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
  195. if (err < 0)
  196. return err;
  197. }
  198. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  199. if (err < 0)
  200. return err;
  201. return 0;
  202. }
  203. static int m88e1118_config_aneg(struct phy_device *phydev)
  204. {
  205. int err;
  206. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  207. if (err < 0)
  208. return err;
  209. err = phy_write(phydev, MII_M1011_PHY_SCR,
  210. MII_M1011_PHY_SCR_AUTO_CROSS);
  211. if (err < 0)
  212. return err;
  213. err = genphy_config_aneg(phydev);
  214. return 0;
  215. }
  216. static int m88e1118_config_init(struct phy_device *phydev)
  217. {
  218. int err;
  219. /* Change address */
  220. err = phy_write(phydev, 0x16, 0x0002);
  221. if (err < 0)
  222. return err;
  223. /* Enable 1000 Mbit */
  224. err = phy_write(phydev, 0x15, 0x1070);
  225. if (err < 0)
  226. return err;
  227. /* Change address */
  228. err = phy_write(phydev, 0x16, 0x0003);
  229. if (err < 0)
  230. return err;
  231. /* Adjust LED Control */
  232. err = phy_write(phydev, 0x10, 0x021e);
  233. if (err < 0)
  234. return err;
  235. /* Reset address */
  236. err = phy_write(phydev, 0x16, 0x0);
  237. if (err < 0)
  238. return err;
  239. err = phy_write(phydev, MII_BMCR, BMCR_RESET);
  240. if (err < 0)
  241. return err;
  242. return 0;
  243. }
  244. static int m88e1145_config_init(struct phy_device *phydev)
  245. {
  246. int err;
  247. /* Take care of errata E0 & E1 */
  248. err = phy_write(phydev, 0x1d, 0x001b);
  249. if (err < 0)
  250. return err;
  251. err = phy_write(phydev, 0x1e, 0x418f);
  252. if (err < 0)
  253. return err;
  254. err = phy_write(phydev, 0x1d, 0x0016);
  255. if (err < 0)
  256. return err;
  257. err = phy_write(phydev, 0x1e, 0xa2da);
  258. if (err < 0)
  259. return err;
  260. if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
  261. int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
  262. if (temp < 0)
  263. return temp;
  264. temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
  265. err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
  266. if (err < 0)
  267. return err;
  268. if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) {
  269. err = phy_write(phydev, 0x1d, 0x0012);
  270. if (err < 0)
  271. return err;
  272. temp = phy_read(phydev, 0x1e);
  273. if (temp < 0)
  274. return temp;
  275. temp &= 0xf03f;
  276. temp |= 2 << 9; /* 36 ohm */
  277. temp |= 2 << 6; /* 39 ohm */
  278. err = phy_write(phydev, 0x1e, temp);
  279. if (err < 0)
  280. return err;
  281. err = phy_write(phydev, 0x1d, 0x3);
  282. if (err < 0)
  283. return err;
  284. err = phy_write(phydev, 0x1e, 0x8000);
  285. if (err < 0)
  286. return err;
  287. }
  288. }
  289. return 0;
  290. }
  291. /* marvell_read_status
  292. *
  293. * Generic status code does not detect Fiber correctly!
  294. * Description:
  295. * Check the link, then figure out the current state
  296. * by comparing what we advertise with what the link partner
  297. * advertises. Start by checking the gigabit possibilities,
  298. * then move on to 10/100.
  299. */
  300. static int marvell_read_status(struct phy_device *phydev)
  301. {
  302. int adv;
  303. int err;
  304. int lpa;
  305. int status = 0;
  306. /* Update the link, but return if there
  307. * was an error */
  308. err = genphy_update_link(phydev);
  309. if (err)
  310. return err;
  311. if (AUTONEG_ENABLE == phydev->autoneg) {
  312. status = phy_read(phydev, MII_M1011_PHY_STATUS);
  313. if (status < 0)
  314. return status;
  315. lpa = phy_read(phydev, MII_LPA);
  316. if (lpa < 0)
  317. return lpa;
  318. adv = phy_read(phydev, MII_ADVERTISE);
  319. if (adv < 0)
  320. return adv;
  321. lpa &= adv;
  322. if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
  323. phydev->duplex = DUPLEX_FULL;
  324. else
  325. phydev->duplex = DUPLEX_HALF;
  326. status = status & MII_M1011_PHY_STATUS_SPD_MASK;
  327. phydev->pause = phydev->asym_pause = 0;
  328. switch (status) {
  329. case MII_M1011_PHY_STATUS_1000:
  330. phydev->speed = SPEED_1000;
  331. break;
  332. case MII_M1011_PHY_STATUS_100:
  333. phydev->speed = SPEED_100;
  334. break;
  335. default:
  336. phydev->speed = SPEED_10;
  337. break;
  338. }
  339. if (phydev->duplex == DUPLEX_FULL) {
  340. phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
  341. phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
  342. }
  343. } else {
  344. int bmcr = phy_read(phydev, MII_BMCR);
  345. if (bmcr < 0)
  346. return bmcr;
  347. if (bmcr & BMCR_FULLDPLX)
  348. phydev->duplex = DUPLEX_FULL;
  349. else
  350. phydev->duplex = DUPLEX_HALF;
  351. if (bmcr & BMCR_SPEED1000)
  352. phydev->speed = SPEED_1000;
  353. else if (bmcr & BMCR_SPEED100)
  354. phydev->speed = SPEED_100;
  355. else
  356. phydev->speed = SPEED_10;
  357. phydev->pause = phydev->asym_pause = 0;
  358. }
  359. return 0;
  360. }
  361. static int m88e1121_did_interrupt(struct phy_device *phydev)
  362. {
  363. int imask;
  364. imask = phy_read(phydev, MII_M1011_IEVENT);
  365. if (imask & MII_M1011_IMASK_INIT)
  366. return 1;
  367. return 0;
  368. }
  369. static struct phy_driver marvell_drivers[] = {
  370. {
  371. .phy_id = 0x01410c60,
  372. .phy_id_mask = 0xfffffff0,
  373. .name = "Marvell 88E1101",
  374. .features = PHY_GBIT_FEATURES,
  375. .flags = PHY_HAS_INTERRUPT,
  376. .config_aneg = &marvell_config_aneg,
  377. .read_status = &genphy_read_status,
  378. .ack_interrupt = &marvell_ack_interrupt,
  379. .config_intr = &marvell_config_intr,
  380. .driver = { .owner = THIS_MODULE },
  381. },
  382. {
  383. .phy_id = 0x01410c90,
  384. .phy_id_mask = 0xfffffff0,
  385. .name = "Marvell 88E1112",
  386. .features = PHY_GBIT_FEATURES,
  387. .flags = PHY_HAS_INTERRUPT,
  388. .config_init = &m88e1111_config_init,
  389. .config_aneg = &marvell_config_aneg,
  390. .read_status = &genphy_read_status,
  391. .ack_interrupt = &marvell_ack_interrupt,
  392. .config_intr = &marvell_config_intr,
  393. .driver = { .owner = THIS_MODULE },
  394. },
  395. {
  396. .phy_id = 0x01410cc0,
  397. .phy_id_mask = 0xfffffff0,
  398. .name = "Marvell 88E1111",
  399. .features = PHY_GBIT_FEATURES,
  400. .flags = PHY_HAS_INTERRUPT,
  401. .config_init = &m88e1111_config_init,
  402. .config_aneg = &marvell_config_aneg,
  403. .read_status = &marvell_read_status,
  404. .ack_interrupt = &marvell_ack_interrupt,
  405. .config_intr = &marvell_config_intr,
  406. .driver = { .owner = THIS_MODULE },
  407. },
  408. {
  409. .phy_id = 0x01410e10,
  410. .phy_id_mask = 0xfffffff0,
  411. .name = "Marvell 88E1118",
  412. .features = PHY_GBIT_FEATURES,
  413. .flags = PHY_HAS_INTERRUPT,
  414. .config_init = &m88e1118_config_init,
  415. .config_aneg = &m88e1118_config_aneg,
  416. .read_status = &genphy_read_status,
  417. .ack_interrupt = &marvell_ack_interrupt,
  418. .config_intr = &marvell_config_intr,
  419. .driver = {.owner = THIS_MODULE,},
  420. },
  421. {
  422. .phy_id = 0x01410cb0,
  423. .phy_id_mask = 0xfffffff0,
  424. .name = "Marvell 88E1121R",
  425. .features = PHY_GBIT_FEATURES,
  426. .flags = PHY_HAS_INTERRUPT,
  427. .config_aneg = &m88e1121_config_aneg,
  428. .read_status = &marvell_read_status,
  429. .ack_interrupt = &marvell_ack_interrupt,
  430. .config_intr = &marvell_config_intr,
  431. .did_interrupt = &m88e1121_did_interrupt,
  432. .driver = { .owner = THIS_MODULE },
  433. },
  434. {
  435. .phy_id = 0x01410cd0,
  436. .phy_id_mask = 0xfffffff0,
  437. .name = "Marvell 88E1145",
  438. .features = PHY_GBIT_FEATURES,
  439. .flags = PHY_HAS_INTERRUPT,
  440. .config_init = &m88e1145_config_init,
  441. .config_aneg = &marvell_config_aneg,
  442. .read_status = &genphy_read_status,
  443. .ack_interrupt = &marvell_ack_interrupt,
  444. .config_intr = &marvell_config_intr,
  445. .driver = { .owner = THIS_MODULE },
  446. },
  447. {
  448. .phy_id = 0x01410e30,
  449. .phy_id_mask = 0xfffffff0,
  450. .name = "Marvell 88E1240",
  451. .features = PHY_GBIT_FEATURES,
  452. .flags = PHY_HAS_INTERRUPT,
  453. .config_init = &m88e1111_config_init,
  454. .config_aneg = &marvell_config_aneg,
  455. .read_status = &genphy_read_status,
  456. .ack_interrupt = &marvell_ack_interrupt,
  457. .config_intr = &marvell_config_intr,
  458. .driver = { .owner = THIS_MODULE },
  459. },
  460. };
  461. static int __init marvell_init(void)
  462. {
  463. int ret;
  464. int i;
  465. for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++) {
  466. ret = phy_driver_register(&marvell_drivers[i]);
  467. if (ret) {
  468. while (i-- > 0)
  469. phy_driver_unregister(&marvell_drivers[i]);
  470. return ret;
  471. }
  472. }
  473. return 0;
  474. }
  475. static void __exit marvell_exit(void)
  476. {
  477. int i;
  478. for (i = 0; i < ARRAY_SIZE(marvell_drivers); i++)
  479. phy_driver_unregister(&marvell_drivers[i]);
  480. }
  481. module_init(marvell_init);
  482. module_exit(marvell_exit);