et1011c.c 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113
  1. /*
  2. * drivers/net/phy/et1011c.c
  3. *
  4. * Driver for LSI ET1011C PHYs
  5. *
  6. * Author: Chaithrika U S
  7. *
  8. * Copyright (c) 2008 Texas Instruments
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. *
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/string.h>
  18. #include <linux/errno.h>
  19. #include <linux/unistd.h>
  20. #include <linux/slab.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/init.h>
  23. #include <linux/delay.h>
  24. #include <linux/netdevice.h>
  25. #include <linux/etherdevice.h>
  26. #include <linux/skbuff.h>
  27. #include <linux/spinlock.h>
  28. #include <linux/mm.h>
  29. #include <linux/module.h>
  30. #include <linux/mii.h>
  31. #include <linux/ethtool.h>
  32. #include <linux/phy.h>
  33. #include <linux/io.h>
  34. #include <linux/uaccess.h>
  35. #include <asm/irq.h>
  36. #define ET1011C_STATUS_REG (0x1A)
  37. #define ET1011C_CONFIG_REG (0x16)
  38. #define ET1011C_SPEED_MASK (0x0300)
  39. #define ET1011C_GIGABIT_SPEED (0x0200)
  40. #define ET1011C_TX_FIFO_MASK (0x3000)
  41. #define ET1011C_TX_FIFO_DEPTH_8 (0x0000)
  42. #define ET1011C_TX_FIFO_DEPTH_16 (0x1000)
  43. #define ET1011C_INTERFACE_MASK (0x0007)
  44. #define ET1011C_GMII_INTERFACE (0x0002)
  45. #define ET1011C_SYS_CLK_EN (0x01 << 4)
  46. MODULE_DESCRIPTION("LSI ET1011C PHY driver");
  47. MODULE_AUTHOR("Chaithrika U S");
  48. MODULE_LICENSE("GPL");
  49. static int et1011c_config_aneg(struct phy_device *phydev)
  50. {
  51. int ctl = 0;
  52. ctl = phy_read(phydev, MII_BMCR);
  53. if (ctl < 0)
  54. return ctl;
  55. ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 |
  56. BMCR_ANENABLE);
  57. /* First clear the PHY */
  58. phy_write(phydev, MII_BMCR, ctl | BMCR_RESET);
  59. return genphy_config_aneg(phydev);
  60. }
  61. static int et1011c_read_status(struct phy_device *phydev)
  62. {
  63. int ret;
  64. u32 val;
  65. static int speed;
  66. ret = genphy_read_status(phydev);
  67. if (speed != phydev->speed) {
  68. speed = phydev->speed;
  69. val = phy_read(phydev, ET1011C_STATUS_REG);
  70. if ((val & ET1011C_SPEED_MASK) ==
  71. ET1011C_GIGABIT_SPEED) {
  72. val = phy_read(phydev, ET1011C_CONFIG_REG);
  73. val &= ~ET1011C_TX_FIFO_MASK;
  74. phy_write(phydev, ET1011C_CONFIG_REG, val\
  75. | ET1011C_GMII_INTERFACE\
  76. | ET1011C_SYS_CLK_EN\
  77. | ET1011C_TX_FIFO_DEPTH_16);
  78. }
  79. }
  80. return ret;
  81. }
  82. static struct phy_driver et1011c_driver = {
  83. .phy_id = 0x0282f014,
  84. .name = "ET1011C",
  85. .phy_id_mask = 0xfffffff0,
  86. .features = (PHY_BASIC_FEATURES | SUPPORTED_1000baseT_Full),
  87. .flags = PHY_POLL,
  88. .config_aneg = et1011c_config_aneg,
  89. .read_status = et1011c_read_status,
  90. .driver = { .owner = THIS_MODULE,},
  91. };
  92. static int __init et1011c_init(void)
  93. {
  94. return phy_driver_register(&et1011c_driver);
  95. }
  96. static void __exit et1011c_exit(void)
  97. {
  98. phy_driver_unregister(&et1011c_driver);
  99. }
  100. module_init(et1011c_init);
  101. module_exit(et1011c_exit);