netxen_nic_init.c 29 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176
  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #include <linux/netdevice.h>
  31. #include <linux/delay.h>
  32. #include "netxen_nic.h"
  33. #include "netxen_nic_hw.h"
  34. #include "netxen_nic_phan_reg.h"
  35. struct crb_addr_pair {
  36. u32 addr;
  37. u32 data;
  38. };
  39. #define NETXEN_MAX_CRB_XFORM 60
  40. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  41. #define NETXEN_ADDR_ERROR (0xffffffff)
  42. #define crb_addr_transform(name) \
  43. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  44. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  45. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  46. static void
  47. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  48. struct nx_host_rds_ring *rds_ring);
  49. static void crb_addr_transform_setup(void)
  50. {
  51. crb_addr_transform(XDMA);
  52. crb_addr_transform(TIMR);
  53. crb_addr_transform(SRE);
  54. crb_addr_transform(SQN3);
  55. crb_addr_transform(SQN2);
  56. crb_addr_transform(SQN1);
  57. crb_addr_transform(SQN0);
  58. crb_addr_transform(SQS3);
  59. crb_addr_transform(SQS2);
  60. crb_addr_transform(SQS1);
  61. crb_addr_transform(SQS0);
  62. crb_addr_transform(RPMX7);
  63. crb_addr_transform(RPMX6);
  64. crb_addr_transform(RPMX5);
  65. crb_addr_transform(RPMX4);
  66. crb_addr_transform(RPMX3);
  67. crb_addr_transform(RPMX2);
  68. crb_addr_transform(RPMX1);
  69. crb_addr_transform(RPMX0);
  70. crb_addr_transform(ROMUSB);
  71. crb_addr_transform(SN);
  72. crb_addr_transform(QMN);
  73. crb_addr_transform(QMS);
  74. crb_addr_transform(PGNI);
  75. crb_addr_transform(PGND);
  76. crb_addr_transform(PGN3);
  77. crb_addr_transform(PGN2);
  78. crb_addr_transform(PGN1);
  79. crb_addr_transform(PGN0);
  80. crb_addr_transform(PGSI);
  81. crb_addr_transform(PGSD);
  82. crb_addr_transform(PGS3);
  83. crb_addr_transform(PGS2);
  84. crb_addr_transform(PGS1);
  85. crb_addr_transform(PGS0);
  86. crb_addr_transform(PS);
  87. crb_addr_transform(PH);
  88. crb_addr_transform(NIU);
  89. crb_addr_transform(I2Q);
  90. crb_addr_transform(EG);
  91. crb_addr_transform(MN);
  92. crb_addr_transform(MS);
  93. crb_addr_transform(CAS2);
  94. crb_addr_transform(CAS1);
  95. crb_addr_transform(CAS0);
  96. crb_addr_transform(CAM);
  97. crb_addr_transform(C2C1);
  98. crb_addr_transform(C2C0);
  99. crb_addr_transform(SMB);
  100. crb_addr_transform(OCM0);
  101. crb_addr_transform(I2C0);
  102. }
  103. int netxen_init_firmware(struct netxen_adapter *adapter)
  104. {
  105. u32 state = 0, loops = 0, err = 0;
  106. /* Window 1 call */
  107. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  108. if (state == PHAN_INITIALIZE_ACK)
  109. return 0;
  110. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  111. msleep(1);
  112. /* Window 1 call */
  113. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  114. loops++;
  115. }
  116. if (loops >= 2000) {
  117. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  118. state);
  119. err = -EIO;
  120. return err;
  121. }
  122. /* Window 1 call */
  123. adapter->pci_write_normalize(adapter,
  124. CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  125. adapter->pci_write_normalize(adapter,
  126. CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  127. adapter->pci_write_normalize(adapter,
  128. CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  129. adapter->pci_write_normalize(adapter,
  130. CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  131. return err;
  132. }
  133. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  134. {
  135. struct netxen_recv_context *recv_ctx;
  136. struct nx_host_rds_ring *rds_ring;
  137. struct netxen_rx_buffer *rx_buf;
  138. int i, ring;
  139. recv_ctx = &adapter->recv_ctx;
  140. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  141. rds_ring = &recv_ctx->rds_rings[ring];
  142. for (i = 0; i < rds_ring->num_desc; ++i) {
  143. rx_buf = &(rds_ring->rx_buf_arr[i]);
  144. if (rx_buf->state == NETXEN_BUFFER_FREE)
  145. continue;
  146. pci_unmap_single(adapter->pdev,
  147. rx_buf->dma,
  148. rds_ring->dma_size,
  149. PCI_DMA_FROMDEVICE);
  150. if (rx_buf->skb != NULL)
  151. dev_kfree_skb_any(rx_buf->skb);
  152. }
  153. }
  154. }
  155. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  156. {
  157. struct netxen_cmd_buffer *cmd_buf;
  158. struct netxen_skb_frag *buffrag;
  159. int i, j;
  160. cmd_buf = adapter->cmd_buf_arr;
  161. for (i = 0; i < adapter->num_txd; i++) {
  162. buffrag = cmd_buf->frag_array;
  163. if (buffrag->dma) {
  164. pci_unmap_single(adapter->pdev, buffrag->dma,
  165. buffrag->length, PCI_DMA_TODEVICE);
  166. buffrag->dma = 0ULL;
  167. }
  168. for (j = 0; j < cmd_buf->frag_count; j++) {
  169. buffrag++;
  170. if (buffrag->dma) {
  171. pci_unmap_page(adapter->pdev, buffrag->dma,
  172. buffrag->length,
  173. PCI_DMA_TODEVICE);
  174. buffrag->dma = 0ULL;
  175. }
  176. }
  177. if (cmd_buf->skb) {
  178. dev_kfree_skb_any(cmd_buf->skb);
  179. cmd_buf->skb = NULL;
  180. }
  181. cmd_buf++;
  182. }
  183. }
  184. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  185. {
  186. struct netxen_recv_context *recv_ctx;
  187. struct nx_host_rds_ring *rds_ring;
  188. int ring;
  189. recv_ctx = &adapter->recv_ctx;
  190. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  191. rds_ring = &recv_ctx->rds_rings[ring];
  192. if (rds_ring->rx_buf_arr) {
  193. vfree(rds_ring->rx_buf_arr);
  194. rds_ring->rx_buf_arr = NULL;
  195. }
  196. }
  197. if (adapter->cmd_buf_arr)
  198. vfree(adapter->cmd_buf_arr);
  199. return;
  200. }
  201. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  202. {
  203. struct netxen_recv_context *recv_ctx;
  204. struct nx_host_rds_ring *rds_ring;
  205. struct nx_host_sds_ring *sds_ring;
  206. struct netxen_rx_buffer *rx_buf;
  207. int ring, i, num_rx_bufs;
  208. struct netxen_cmd_buffer *cmd_buf_arr;
  209. struct net_device *netdev = adapter->netdev;
  210. cmd_buf_arr =
  211. (struct netxen_cmd_buffer *)vmalloc(TX_BUFF_RINGSIZE(adapter));
  212. if (cmd_buf_arr == NULL) {
  213. printk(KERN_ERR "%s: Failed to allocate cmd buffer ring\n",
  214. netdev->name);
  215. return -ENOMEM;
  216. }
  217. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(adapter));
  218. adapter->cmd_buf_arr = cmd_buf_arr;
  219. recv_ctx = &adapter->recv_ctx;
  220. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  221. rds_ring = &recv_ctx->rds_rings[ring];
  222. switch (ring) {
  223. case RCV_RING_NORMAL:
  224. rds_ring->num_desc = adapter->num_rxd;
  225. if (adapter->ahw.cut_through) {
  226. rds_ring->dma_size =
  227. NX_CT_DEFAULT_RX_BUF_LEN;
  228. rds_ring->skb_size =
  229. NX_CT_DEFAULT_RX_BUF_LEN;
  230. } else {
  231. rds_ring->dma_size = RX_DMA_MAP_LEN;
  232. rds_ring->skb_size =
  233. MAX_RX_BUFFER_LENGTH;
  234. }
  235. break;
  236. case RCV_RING_JUMBO:
  237. rds_ring->num_desc = adapter->num_jumbo_rxd;
  238. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  239. rds_ring->dma_size =
  240. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  241. else
  242. rds_ring->dma_size =
  243. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  244. rds_ring->skb_size =
  245. rds_ring->dma_size + NET_IP_ALIGN;
  246. break;
  247. case RCV_RING_LRO:
  248. rds_ring->num_desc = adapter->num_lro_rxd;
  249. rds_ring->dma_size = RX_LRO_DMA_MAP_LEN;
  250. rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
  251. break;
  252. }
  253. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  254. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  255. if (rds_ring->rx_buf_arr == NULL) {
  256. printk(KERN_ERR "%s: Failed to allocate "
  257. "rx buffer ring %d\n",
  258. netdev->name, ring);
  259. /* free whatever was already allocated */
  260. goto err_out;
  261. }
  262. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  263. INIT_LIST_HEAD(&rds_ring->free_list);
  264. /*
  265. * Now go through all of them, set reference handles
  266. * and put them in the queues.
  267. */
  268. num_rx_bufs = rds_ring->num_desc;
  269. rx_buf = rds_ring->rx_buf_arr;
  270. for (i = 0; i < num_rx_bufs; i++) {
  271. list_add_tail(&rx_buf->list,
  272. &rds_ring->free_list);
  273. rx_buf->ref_handle = i;
  274. rx_buf->state = NETXEN_BUFFER_FREE;
  275. rx_buf++;
  276. }
  277. spin_lock_init(&rds_ring->lock);
  278. }
  279. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  280. sds_ring = &recv_ctx->sds_rings[ring];
  281. sds_ring->irq = adapter->msix_entries[ring].vector;
  282. sds_ring->clean_tx = (ring == 0);
  283. sds_ring->post_rxd = (ring == 0);
  284. sds_ring->adapter = adapter;
  285. sds_ring->num_desc = adapter->num_rxd;
  286. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  287. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  288. }
  289. return 0;
  290. err_out:
  291. netxen_free_sw_resources(adapter);
  292. return -ENOMEM;
  293. }
  294. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  295. {
  296. switch (adapter->ahw.port_type) {
  297. case NETXEN_NIC_GBE:
  298. adapter->enable_phy_interrupts =
  299. netxen_niu_gbe_enable_phy_interrupts;
  300. adapter->disable_phy_interrupts =
  301. netxen_niu_gbe_disable_phy_interrupts;
  302. adapter->macaddr_set = netxen_niu_macaddr_set;
  303. adapter->set_mtu = netxen_nic_set_mtu_gb;
  304. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  305. adapter->phy_read = netxen_niu_gbe_phy_read;
  306. adapter->phy_write = netxen_niu_gbe_phy_write;
  307. adapter->init_port = netxen_niu_gbe_init_port;
  308. adapter->stop_port = netxen_niu_disable_gbe_port;
  309. break;
  310. case NETXEN_NIC_XGBE:
  311. adapter->enable_phy_interrupts =
  312. netxen_niu_xgbe_enable_phy_interrupts;
  313. adapter->disable_phy_interrupts =
  314. netxen_niu_xgbe_disable_phy_interrupts;
  315. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  316. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  317. adapter->init_port = netxen_niu_xg_init_port;
  318. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  319. adapter->stop_port = netxen_niu_disable_xg_port;
  320. break;
  321. default:
  322. break;
  323. }
  324. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  325. adapter->set_mtu = nx_fw_cmd_set_mtu;
  326. adapter->set_promisc = netxen_p3_nic_set_promisc;
  327. }
  328. }
  329. /*
  330. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  331. * address to external PCI CRB address.
  332. */
  333. static u32 netxen_decode_crb_addr(u32 addr)
  334. {
  335. int i;
  336. u32 base_addr, offset, pci_base;
  337. crb_addr_transform_setup();
  338. pci_base = NETXEN_ADDR_ERROR;
  339. base_addr = addr & 0xfff00000;
  340. offset = addr & 0x000fffff;
  341. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  342. if (crb_addr_xform[i] == base_addr) {
  343. pci_base = i << 20;
  344. break;
  345. }
  346. }
  347. if (pci_base == NETXEN_ADDR_ERROR)
  348. return pci_base;
  349. else
  350. return (pci_base + offset);
  351. }
  352. static long rom_max_timeout = 100;
  353. static long rom_lock_timeout = 10000;
  354. static int rom_lock(struct netxen_adapter *adapter)
  355. {
  356. int iter;
  357. u32 done = 0;
  358. int timeout = 0;
  359. while (!done) {
  360. /* acquire semaphore2 from PCI HW block */
  361. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  362. &done);
  363. if (done == 1)
  364. break;
  365. if (timeout >= rom_lock_timeout)
  366. return -EIO;
  367. timeout++;
  368. /*
  369. * Yield CPU
  370. */
  371. if (!in_atomic())
  372. schedule();
  373. else {
  374. for (iter = 0; iter < 20; iter++)
  375. cpu_relax(); /*This a nop instr on i386 */
  376. }
  377. }
  378. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  379. return 0;
  380. }
  381. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  382. {
  383. long timeout = 0;
  384. long done = 0;
  385. cond_resched();
  386. while (done == 0) {
  387. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  388. done &= 2;
  389. timeout++;
  390. if (timeout >= rom_max_timeout) {
  391. printk("Timeout reached waiting for rom done");
  392. return -EIO;
  393. }
  394. }
  395. return 0;
  396. }
  397. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  398. {
  399. u32 val;
  400. /* release semaphore2 */
  401. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  402. }
  403. static int do_rom_fast_read(struct netxen_adapter *adapter,
  404. int addr, int *valp)
  405. {
  406. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  407. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  408. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  409. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  410. if (netxen_wait_rom_done(adapter)) {
  411. printk("Error waiting for rom done\n");
  412. return -EIO;
  413. }
  414. /* reset abyte_cnt and dummy_byte_cnt */
  415. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  416. udelay(10);
  417. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  418. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  419. return 0;
  420. }
  421. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  422. u8 *bytes, size_t size)
  423. {
  424. int addridx;
  425. int ret = 0;
  426. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  427. int v;
  428. ret = do_rom_fast_read(adapter, addridx, &v);
  429. if (ret != 0)
  430. break;
  431. *(__le32 *)bytes = cpu_to_le32(v);
  432. bytes += 4;
  433. }
  434. return ret;
  435. }
  436. int
  437. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  438. u8 *bytes, size_t size)
  439. {
  440. int ret;
  441. ret = rom_lock(adapter);
  442. if (ret < 0)
  443. return ret;
  444. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  445. netxen_rom_unlock(adapter);
  446. return ret;
  447. }
  448. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  449. {
  450. int ret;
  451. if (rom_lock(adapter) != 0)
  452. return -EIO;
  453. ret = do_rom_fast_read(adapter, addr, valp);
  454. netxen_rom_unlock(adapter);
  455. return ret;
  456. }
  457. #define NETXEN_BOARDTYPE 0x4008
  458. #define NETXEN_BOARDNUM 0x400c
  459. #define NETXEN_CHIPNUM 0x4010
  460. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  461. {
  462. int addr, val;
  463. int i, n, init_delay = 0;
  464. struct crb_addr_pair *buf;
  465. unsigned offset;
  466. u32 off;
  467. /* resetall */
  468. rom_lock(adapter);
  469. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  470. 0xffffffff);
  471. netxen_rom_unlock(adapter);
  472. if (verbose) {
  473. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  474. printk("P2 ROM board type: 0x%08x\n", val);
  475. else
  476. printk("Could not read board type\n");
  477. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  478. printk("P2 ROM board num: 0x%08x\n", val);
  479. else
  480. printk("Could not read board number\n");
  481. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  482. printk("P2 ROM chip num: 0x%08x\n", val);
  483. else
  484. printk("Could not read chip number\n");
  485. }
  486. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  487. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  488. (n != 0xcafecafe) ||
  489. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  490. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  491. "n: %08x\n", netxen_nic_driver_name, n);
  492. return -EIO;
  493. }
  494. offset = n & 0xffffU;
  495. n = (n >> 16) & 0xffffU;
  496. } else {
  497. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  498. !(n & 0x80000000)) {
  499. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  500. "n: %08x\n", netxen_nic_driver_name, n);
  501. return -EIO;
  502. }
  503. offset = 1;
  504. n &= ~0x80000000;
  505. }
  506. if (n < 1024) {
  507. if (verbose)
  508. printk(KERN_DEBUG "%s: %d CRB init values found"
  509. " in ROM.\n", netxen_nic_driver_name, n);
  510. } else {
  511. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  512. " initialized.\n", __func__, n);
  513. return -EIO;
  514. }
  515. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  516. if (buf == NULL) {
  517. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  518. netxen_nic_driver_name);
  519. return -ENOMEM;
  520. }
  521. for (i = 0; i < n; i++) {
  522. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  523. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  524. kfree(buf);
  525. return -EIO;
  526. }
  527. buf[i].addr = addr;
  528. buf[i].data = val;
  529. if (verbose)
  530. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  531. netxen_nic_driver_name,
  532. (u32)netxen_decode_crb_addr(addr), val);
  533. }
  534. for (i = 0; i < n; i++) {
  535. off = netxen_decode_crb_addr(buf[i].addr);
  536. if (off == NETXEN_ADDR_ERROR) {
  537. printk(KERN_ERR"CRB init value out of range %x\n",
  538. buf[i].addr);
  539. continue;
  540. }
  541. off += NETXEN_PCI_CRBSPACE;
  542. /* skipping cold reboot MAGIC */
  543. if (off == NETXEN_CAM_RAM(0x1fc))
  544. continue;
  545. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  546. /* do not reset PCI */
  547. if (off == (ROMUSB_GLB + 0xbc))
  548. continue;
  549. if (off == (ROMUSB_GLB + 0xa8))
  550. continue;
  551. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  552. continue;
  553. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  554. continue;
  555. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  556. continue;
  557. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  558. buf[i].data = 0x1020;
  559. /* skip the function enable register */
  560. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  561. continue;
  562. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  563. continue;
  564. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  565. continue;
  566. }
  567. if (off == NETXEN_ADDR_ERROR) {
  568. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  569. netxen_nic_driver_name, buf[i].addr);
  570. continue;
  571. }
  572. init_delay = 1;
  573. /* After writing this register, HW needs time for CRB */
  574. /* to quiet down (else crb_window returns 0xffffffff) */
  575. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  576. init_delay = 1000;
  577. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  578. /* hold xdma in reset also */
  579. buf[i].data = NETXEN_NIC_XDMA_RESET;
  580. buf[i].data = 0x8000ff;
  581. }
  582. }
  583. adapter->hw_write_wx(adapter, off, &buf[i].data, 4);
  584. msleep(init_delay);
  585. }
  586. kfree(buf);
  587. /* disable_peg_cache_all */
  588. /* unreset_net_cache */
  589. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  590. adapter->hw_read_wx(adapter,
  591. NETXEN_ROMUSB_GLB_SW_RESET, &val, 4);
  592. netxen_crb_writelit_adapter(adapter,
  593. NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  594. }
  595. /* p2dn replyCount */
  596. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  597. /* disable_peg_cache 0 */
  598. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  599. /* disable_peg_cache 1 */
  600. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  601. /* peg_clr_all */
  602. /* peg_clr 0 */
  603. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  604. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  605. /* peg_clr 1 */
  606. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  607. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  608. /* peg_clr 2 */
  609. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  610. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  611. /* peg_clr 3 */
  612. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  613. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  614. return 0;
  615. }
  616. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  617. {
  618. uint64_t addr;
  619. uint32_t hi;
  620. uint32_t lo;
  621. adapter->dummy_dma.addr =
  622. pci_alloc_consistent(adapter->pdev,
  623. NETXEN_HOST_DUMMY_DMA_SIZE,
  624. &adapter->dummy_dma.phys_addr);
  625. if (adapter->dummy_dma.addr == NULL) {
  626. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  627. __func__);
  628. return -ENOMEM;
  629. }
  630. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  631. hi = (addr >> 32) & 0xffffffff;
  632. lo = addr & 0xffffffff;
  633. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  634. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  635. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  636. uint32_t temp = 0;
  637. adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, &temp, 4);
  638. }
  639. return 0;
  640. }
  641. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  642. {
  643. int i = 100;
  644. if (!adapter->dummy_dma.addr)
  645. return;
  646. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  647. do {
  648. if (dma_watchdog_shutdown_request(adapter) == 1)
  649. break;
  650. msleep(50);
  651. if (dma_watchdog_shutdown_poll_result(adapter) == 1)
  652. break;
  653. } while (--i);
  654. }
  655. if (i) {
  656. pci_free_consistent(adapter->pdev,
  657. NETXEN_HOST_DUMMY_DMA_SIZE,
  658. adapter->dummy_dma.addr,
  659. adapter->dummy_dma.phys_addr);
  660. adapter->dummy_dma.addr = NULL;
  661. } else {
  662. printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
  663. adapter->netdev->name);
  664. }
  665. }
  666. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  667. {
  668. u32 val = 0;
  669. int retries = 60;
  670. if (!pegtune_val) {
  671. do {
  672. val = adapter->pci_read_normalize(adapter,
  673. CRB_CMDPEG_STATE);
  674. if (val == PHAN_INITIALIZE_COMPLETE ||
  675. val == PHAN_INITIALIZE_ACK)
  676. return 0;
  677. msleep(500);
  678. } while (--retries);
  679. if (!retries) {
  680. pegtune_val = adapter->pci_read_normalize(adapter,
  681. NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
  682. printk(KERN_WARNING "netxen_phantom_init: init failed, "
  683. "pegtune_val=%x\n", pegtune_val);
  684. return -1;
  685. }
  686. }
  687. return 0;
  688. }
  689. int netxen_receive_peg_ready(struct netxen_adapter *adapter)
  690. {
  691. u32 val = 0;
  692. int retries = 2000;
  693. do {
  694. val = adapter->pci_read_normalize(adapter, CRB_RCVPEG_STATE);
  695. if (val == PHAN_PEG_RCV_INITIALIZED)
  696. return 0;
  697. msleep(10);
  698. } while (--retries);
  699. if (!retries) {
  700. printk(KERN_ERR "Receive Peg initialization not "
  701. "complete, state: 0x%x.\n", val);
  702. return -EIO;
  703. }
  704. return 0;
  705. }
  706. static int
  707. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  708. struct nx_host_rds_ring *rds_ring,
  709. struct netxen_rx_buffer *buffer)
  710. {
  711. struct sk_buff *skb;
  712. dma_addr_t dma;
  713. struct pci_dev *pdev = adapter->pdev;
  714. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  715. if (!buffer->skb)
  716. return 1;
  717. skb = buffer->skb;
  718. if (!adapter->ahw.cut_through)
  719. skb_reserve(skb, 2);
  720. dma = pci_map_single(pdev, skb->data,
  721. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  722. if (pci_dma_mapping_error(pdev, dma)) {
  723. dev_kfree_skb_any(skb);
  724. buffer->skb = NULL;
  725. return 1;
  726. }
  727. buffer->skb = skb;
  728. buffer->dma = dma;
  729. buffer->state = NETXEN_BUFFER_BUSY;
  730. return 0;
  731. }
  732. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  733. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  734. {
  735. struct netxen_rx_buffer *buffer;
  736. struct sk_buff *skb;
  737. buffer = &rds_ring->rx_buf_arr[index];
  738. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  739. PCI_DMA_FROMDEVICE);
  740. skb = buffer->skb;
  741. if (!skb)
  742. goto no_skb;
  743. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  744. adapter->stats.csummed++;
  745. skb->ip_summed = CHECKSUM_UNNECESSARY;
  746. } else
  747. skb->ip_summed = CHECKSUM_NONE;
  748. skb->dev = adapter->netdev;
  749. buffer->skb = NULL;
  750. no_skb:
  751. buffer->state = NETXEN_BUFFER_FREE;
  752. return skb;
  753. }
  754. static struct netxen_rx_buffer *
  755. netxen_process_rcv(struct netxen_adapter *adapter,
  756. int ring, int index, int length, int cksum, int pkt_offset)
  757. {
  758. struct net_device *netdev = adapter->netdev;
  759. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  760. struct netxen_rx_buffer *buffer;
  761. struct sk_buff *skb;
  762. struct nx_host_rds_ring *rds_ring = &recv_ctx->rds_rings[ring];
  763. if (unlikely(index > rds_ring->num_desc))
  764. return NULL;
  765. buffer = &rds_ring->rx_buf_arr[index];
  766. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  767. if (!skb)
  768. return buffer;
  769. if (length > rds_ring->skb_size)
  770. skb_put(skb, rds_ring->skb_size);
  771. else
  772. skb_put(skb, length);
  773. if (pkt_offset)
  774. skb_pull(skb, pkt_offset);
  775. skb->protocol = eth_type_trans(skb, netdev);
  776. netif_receive_skb(skb);
  777. adapter->stats.no_rcv++;
  778. adapter->stats.rxbytes += length;
  779. return buffer;
  780. }
  781. #define netxen_merge_rx_buffers(list, head) \
  782. do { list_splice_tail_init(list, head); } while (0);
  783. int
  784. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  785. {
  786. struct netxen_adapter *adapter = sds_ring->adapter;
  787. struct list_head *cur;
  788. struct status_desc *desc;
  789. struct netxen_rx_buffer *rxbuf;
  790. u32 consumer = sds_ring->consumer;
  791. int count = 0;
  792. u64 sts_data;
  793. int opcode, ring, index, length, cksum, pkt_offset;
  794. while (count < max) {
  795. desc = &sds_ring->desc_head[consumer];
  796. sts_data = le64_to_cpu(desc->status_desc_data);
  797. if (!(sts_data & STATUS_OWNER_HOST))
  798. break;
  799. ring = netxen_get_sts_type(sts_data);
  800. if (ring > RCV_RING_JUMBO)
  801. continue;
  802. opcode = netxen_get_sts_opcode(sts_data);
  803. index = netxen_get_sts_refhandle(sts_data);
  804. length = netxen_get_sts_totallength(sts_data);
  805. cksum = netxen_get_sts_status(sts_data);
  806. pkt_offset = netxen_get_sts_pkt_offset(sts_data);
  807. rxbuf = netxen_process_rcv(adapter, ring, index,
  808. length, cksum, pkt_offset);
  809. if (rxbuf)
  810. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  811. desc->status_desc_data = cpu_to_le64(STATUS_OWNER_PHANTOM);
  812. consumer = get_next_index(consumer, sds_ring->num_desc);
  813. count++;
  814. }
  815. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  816. struct nx_host_rds_ring *rds_ring =
  817. &adapter->recv_ctx.rds_rings[ring];
  818. if (!list_empty(&sds_ring->free_list[ring])) {
  819. list_for_each(cur, &sds_ring->free_list[ring]) {
  820. rxbuf = list_entry(cur,
  821. struct netxen_rx_buffer, list);
  822. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  823. }
  824. spin_lock(&rds_ring->lock);
  825. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  826. &rds_ring->free_list);
  827. spin_unlock(&rds_ring->lock);
  828. }
  829. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  830. }
  831. if (count) {
  832. sds_ring->consumer = consumer;
  833. adapter->pci_write_normalize(adapter,
  834. sds_ring->crb_sts_consumer, consumer);
  835. }
  836. return count;
  837. }
  838. /* Process Command status ring */
  839. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  840. {
  841. u32 last_consumer, consumer;
  842. int count = 0, i;
  843. struct netxen_cmd_buffer *buffer;
  844. struct pci_dev *pdev = adapter->pdev;
  845. struct net_device *netdev = adapter->netdev;
  846. struct netxen_skb_frag *frag;
  847. int done = 0;
  848. if (!spin_trylock(&adapter->tx_clean_lock))
  849. return 1;
  850. last_consumer = adapter->last_cmd_consumer;
  851. barrier(); /* cmd_consumer can change underneath */
  852. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  853. while (last_consumer != consumer) {
  854. buffer = &adapter->cmd_buf_arr[last_consumer];
  855. if (buffer->skb) {
  856. frag = &buffer->frag_array[0];
  857. pci_unmap_single(pdev, frag->dma, frag->length,
  858. PCI_DMA_TODEVICE);
  859. frag->dma = 0ULL;
  860. for (i = 1; i < buffer->frag_count; i++) {
  861. frag++; /* Get the next frag */
  862. pci_unmap_page(pdev, frag->dma, frag->length,
  863. PCI_DMA_TODEVICE);
  864. frag->dma = 0ULL;
  865. }
  866. adapter->stats.xmitfinished++;
  867. dev_kfree_skb_any(buffer->skb);
  868. buffer->skb = NULL;
  869. }
  870. last_consumer = get_next_index(last_consumer,
  871. adapter->num_txd);
  872. if (++count >= MAX_STATUS_HANDLE)
  873. break;
  874. }
  875. if (count) {
  876. adapter->last_cmd_consumer = last_consumer;
  877. smp_mb();
  878. if (netif_queue_stopped(netdev) && netif_running(netdev)) {
  879. netif_tx_lock(netdev);
  880. netif_wake_queue(netdev);
  881. smp_mb();
  882. netif_tx_unlock(netdev);
  883. }
  884. }
  885. /*
  886. * If everything is freed up to consumer then check if the ring is full
  887. * If the ring is full then check if more needs to be freed and
  888. * schedule the call back again.
  889. *
  890. * This happens when there are 2 CPUs. One could be freeing and the
  891. * other filling it. If the ring is full when we get out of here and
  892. * the card has already interrupted the host then the host can miss the
  893. * interrupt.
  894. *
  895. * There is still a possible race condition and the host could miss an
  896. * interrupt. The card has to take care of this.
  897. */
  898. barrier(); /* cmd_consumer can change underneath */
  899. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  900. done = (last_consumer == consumer);
  901. spin_unlock(&adapter->tx_clean_lock);
  902. return (done);
  903. }
  904. void
  905. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  906. struct nx_host_rds_ring *rds_ring)
  907. {
  908. struct rcv_desc *pdesc;
  909. struct netxen_rx_buffer *buffer;
  910. int producer, count = 0;
  911. netxen_ctx_msg msg = 0;
  912. struct list_head *head;
  913. producer = rds_ring->producer;
  914. spin_lock(&rds_ring->lock);
  915. head = &rds_ring->free_list;
  916. while (!list_empty(head)) {
  917. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  918. if (!buffer->skb) {
  919. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  920. break;
  921. }
  922. count++;
  923. list_del(&buffer->list);
  924. /* make a rcv descriptor */
  925. pdesc = &rds_ring->desc_head[producer];
  926. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  927. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  928. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  929. producer = get_next_index(producer, rds_ring->num_desc);
  930. }
  931. spin_unlock(&rds_ring->lock);
  932. if (count) {
  933. rds_ring->producer = producer;
  934. adapter->pci_write_normalize(adapter,
  935. rds_ring->crb_rcv_producer,
  936. (producer-1) & (rds_ring->num_desc-1));
  937. if (adapter->fw_major < 4) {
  938. /*
  939. * Write a doorbell msg to tell phanmon of change in
  940. * receive ring producer
  941. * Only for firmware version < 4.0.0
  942. */
  943. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  944. netxen_set_msg_privid(msg);
  945. netxen_set_msg_count(msg,
  946. ((producer - 1) &
  947. (rds_ring->num_desc - 1)));
  948. netxen_set_msg_ctxid(msg, adapter->portnum);
  949. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  950. writel(msg,
  951. DB_NORMALIZE(adapter,
  952. NETXEN_RCV_PRODUCER_OFFSET));
  953. }
  954. }
  955. }
  956. static void
  957. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  958. struct nx_host_rds_ring *rds_ring)
  959. {
  960. struct rcv_desc *pdesc;
  961. struct netxen_rx_buffer *buffer;
  962. int producer, count = 0;
  963. struct list_head *head;
  964. producer = rds_ring->producer;
  965. if (!spin_trylock(&rds_ring->lock))
  966. return;
  967. head = &rds_ring->free_list;
  968. while (!list_empty(head)) {
  969. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  970. if (!buffer->skb) {
  971. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  972. break;
  973. }
  974. count++;
  975. list_del(&buffer->list);
  976. /* make a rcv descriptor */
  977. pdesc = &rds_ring->desc_head[producer];
  978. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  979. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  980. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  981. producer = get_next_index(producer, rds_ring->num_desc);
  982. }
  983. if (count) {
  984. rds_ring->producer = producer;
  985. adapter->pci_write_normalize(adapter,
  986. rds_ring->crb_rcv_producer,
  987. (producer - 1) & (rds_ring->num_desc - 1));
  988. wmb();
  989. }
  990. spin_unlock(&rds_ring->lock);
  991. }
  992. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  993. {
  994. memset(&adapter->stats, 0, sizeof(adapter->stats));
  995. return;
  996. }