en_rx.c 30 KB

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  1. /*
  2. * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. */
  33. #include <linux/mlx4/cq.h>
  34. #include <linux/mlx4/qp.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/if_ether.h>
  37. #include <linux/if_vlan.h>
  38. #include <linux/vmalloc.h>
  39. #include "mlx4_en.h"
  40. static void *get_wqe(struct mlx4_en_rx_ring *ring, int n)
  41. {
  42. int offset = n << ring->srq.wqe_shift;
  43. return ring->buf + offset;
  44. }
  45. static void mlx4_en_srq_event(struct mlx4_srq *srq, enum mlx4_event type)
  46. {
  47. return;
  48. }
  49. static int mlx4_en_get_frag_header(struct skb_frag_struct *frags, void **mac_hdr,
  50. void **ip_hdr, void **tcpudp_hdr,
  51. u64 *hdr_flags, void *priv)
  52. {
  53. *mac_hdr = page_address(frags->page) + frags->page_offset;
  54. *ip_hdr = *mac_hdr + ETH_HLEN;
  55. *tcpudp_hdr = (struct tcphdr *)(*ip_hdr + sizeof(struct iphdr));
  56. *hdr_flags = LRO_IPV4 | LRO_TCP;
  57. return 0;
  58. }
  59. static int mlx4_en_alloc_frag(struct mlx4_en_priv *priv,
  60. struct mlx4_en_rx_desc *rx_desc,
  61. struct skb_frag_struct *skb_frags,
  62. struct mlx4_en_rx_alloc *ring_alloc,
  63. int i)
  64. {
  65. struct mlx4_en_dev *mdev = priv->mdev;
  66. struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
  67. struct mlx4_en_rx_alloc *page_alloc = &ring_alloc[i];
  68. struct page *page;
  69. dma_addr_t dma;
  70. if (page_alloc->offset == frag_info->last_offset) {
  71. /* Allocate new page */
  72. page = alloc_pages(GFP_ATOMIC | __GFP_COMP, MLX4_EN_ALLOC_ORDER);
  73. if (!page)
  74. return -ENOMEM;
  75. skb_frags[i].page = page_alloc->page;
  76. skb_frags[i].page_offset = page_alloc->offset;
  77. page_alloc->page = page;
  78. page_alloc->offset = frag_info->frag_align;
  79. } else {
  80. page = page_alloc->page;
  81. get_page(page);
  82. skb_frags[i].page = page;
  83. skb_frags[i].page_offset = page_alloc->offset;
  84. page_alloc->offset += frag_info->frag_stride;
  85. }
  86. dma = pci_map_single(mdev->pdev, page_address(skb_frags[i].page) +
  87. skb_frags[i].page_offset, frag_info->frag_size,
  88. PCI_DMA_FROMDEVICE);
  89. rx_desc->data[i].addr = cpu_to_be64(dma);
  90. return 0;
  91. }
  92. static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
  93. struct mlx4_en_rx_ring *ring)
  94. {
  95. struct mlx4_en_rx_alloc *page_alloc;
  96. int i;
  97. for (i = 0; i < priv->num_frags; i++) {
  98. page_alloc = &ring->page_alloc[i];
  99. page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
  100. MLX4_EN_ALLOC_ORDER);
  101. if (!page_alloc->page)
  102. goto out;
  103. page_alloc->offset = priv->frag_info[i].frag_align;
  104. mlx4_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n",
  105. i, page_alloc->page);
  106. }
  107. return 0;
  108. out:
  109. while (i--) {
  110. page_alloc = &ring->page_alloc[i];
  111. put_page(page_alloc->page);
  112. page_alloc->page = NULL;
  113. }
  114. return -ENOMEM;
  115. }
  116. static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
  117. struct mlx4_en_rx_ring *ring)
  118. {
  119. struct mlx4_en_rx_alloc *page_alloc;
  120. int i;
  121. for (i = 0; i < priv->num_frags; i++) {
  122. page_alloc = &ring->page_alloc[i];
  123. mlx4_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
  124. i, page_count(page_alloc->page));
  125. put_page(page_alloc->page);
  126. page_alloc->page = NULL;
  127. }
  128. }
  129. static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
  130. struct mlx4_en_rx_ring *ring, int index)
  131. {
  132. struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
  133. struct skb_frag_struct *skb_frags = ring->rx_info +
  134. (index << priv->log_rx_info);
  135. int possible_frags;
  136. int i;
  137. /* Pre-link descriptor */
  138. rx_desc->next.next_wqe_index = cpu_to_be16((index + 1) & ring->size_mask);
  139. /* Set size and memtype fields */
  140. for (i = 0; i < priv->num_frags; i++) {
  141. skb_frags[i].size = priv->frag_info[i].frag_size;
  142. rx_desc->data[i].byte_count =
  143. cpu_to_be32(priv->frag_info[i].frag_size);
  144. rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
  145. }
  146. /* If the number of used fragments does not fill up the ring stride,
  147. * remaining (unused) fragments must be padded with null address/size
  148. * and a special memory key */
  149. possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
  150. for (i = priv->num_frags; i < possible_frags; i++) {
  151. rx_desc->data[i].byte_count = 0;
  152. rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
  153. rx_desc->data[i].addr = 0;
  154. }
  155. }
  156. static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
  157. struct mlx4_en_rx_ring *ring, int index)
  158. {
  159. struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
  160. struct skb_frag_struct *skb_frags = ring->rx_info +
  161. (index << priv->log_rx_info);
  162. int i;
  163. for (i = 0; i < priv->num_frags; i++)
  164. if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, ring->page_alloc, i))
  165. goto err;
  166. return 0;
  167. err:
  168. while (i--)
  169. put_page(skb_frags[i].page);
  170. return -ENOMEM;
  171. }
  172. static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
  173. {
  174. *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
  175. }
  176. static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
  177. {
  178. struct mlx4_en_dev *mdev = priv->mdev;
  179. struct mlx4_en_rx_ring *ring;
  180. int ring_ind;
  181. int buf_ind;
  182. for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
  183. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  184. ring = &priv->rx_ring[ring_ind];
  185. if (mlx4_en_prepare_rx_desc(priv, ring,
  186. ring->actual_size)) {
  187. if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
  188. mlx4_err(mdev, "Failed to allocate "
  189. "enough rx buffers\n");
  190. return -ENOMEM;
  191. } else {
  192. if (netif_msg_rx_err(priv))
  193. mlx4_warn(mdev,
  194. "Only %d buffers allocated\n",
  195. ring->actual_size);
  196. goto out;
  197. }
  198. }
  199. ring->actual_size++;
  200. ring->prod++;
  201. }
  202. }
  203. out:
  204. return 0;
  205. }
  206. static int mlx4_en_fill_rx_buf(struct net_device *dev,
  207. struct mlx4_en_rx_ring *ring)
  208. {
  209. struct mlx4_en_priv *priv = netdev_priv(dev);
  210. int num = 0;
  211. int err;
  212. while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
  213. err = mlx4_en_prepare_rx_desc(priv, ring, ring->prod &
  214. ring->size_mask);
  215. if (err) {
  216. if (netif_msg_rx_err(priv))
  217. mlx4_warn(priv->mdev,
  218. "Failed preparing rx descriptor\n");
  219. priv->port_stats.rx_alloc_failed++;
  220. break;
  221. }
  222. ++num;
  223. ++ring->prod;
  224. }
  225. if ((u32) (ring->prod - ring->cons) == ring->size)
  226. ring->full = 1;
  227. return num;
  228. }
  229. static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
  230. struct mlx4_en_rx_ring *ring)
  231. {
  232. struct mlx4_en_dev *mdev = priv->mdev;
  233. struct skb_frag_struct *skb_frags;
  234. struct mlx4_en_rx_desc *rx_desc;
  235. dma_addr_t dma;
  236. int index;
  237. int nr;
  238. mlx4_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
  239. ring->cons, ring->prod);
  240. /* Unmap and free Rx buffers */
  241. BUG_ON((u32) (ring->prod - ring->cons) > ring->size);
  242. while (ring->cons != ring->prod) {
  243. index = ring->cons & ring->size_mask;
  244. rx_desc = ring->buf + (index << ring->log_stride);
  245. skb_frags = ring->rx_info + (index << priv->log_rx_info);
  246. mlx4_dbg(DRV, priv, "Processing descriptor:%d\n", index);
  247. for (nr = 0; nr < priv->num_frags; nr++) {
  248. mlx4_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
  249. dma = be64_to_cpu(rx_desc->data[nr].addr);
  250. mlx4_dbg(DRV, priv, "Unmaping buffer at dma:0x%llx\n", (u64) dma);
  251. pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size,
  252. PCI_DMA_FROMDEVICE);
  253. put_page(skb_frags[nr].page);
  254. }
  255. ++ring->cons;
  256. }
  257. }
  258. void mlx4_en_rx_refill(struct work_struct *work)
  259. {
  260. struct delayed_work *delay = to_delayed_work(work);
  261. struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
  262. refill_task);
  263. struct mlx4_en_dev *mdev = priv->mdev;
  264. struct net_device *dev = priv->dev;
  265. struct mlx4_en_rx_ring *ring;
  266. int need_refill = 0;
  267. int i;
  268. mutex_lock(&mdev->state_lock);
  269. if (!mdev->device_up || !priv->port_up)
  270. goto out;
  271. /* We only get here if there are no receive buffers, so we can't race
  272. * with Rx interrupts while filling buffers */
  273. for (i = 0; i < priv->rx_ring_num; i++) {
  274. ring = &priv->rx_ring[i];
  275. if (ring->need_refill) {
  276. if (mlx4_en_fill_rx_buf(dev, ring)) {
  277. ring->need_refill = 0;
  278. mlx4_en_update_rx_prod_db(ring);
  279. } else
  280. need_refill = 1;
  281. }
  282. }
  283. if (need_refill)
  284. queue_delayed_work(mdev->workqueue, &priv->refill_task, HZ);
  285. out:
  286. mutex_unlock(&mdev->state_lock);
  287. }
  288. int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
  289. struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
  290. {
  291. struct mlx4_en_dev *mdev = priv->mdev;
  292. int err;
  293. int tmp;
  294. /* Sanity check SRQ size before proceeding */
  295. if (size >= mdev->dev->caps.max_srq_wqes)
  296. return -EINVAL;
  297. ring->prod = 0;
  298. ring->cons = 0;
  299. ring->size = size;
  300. ring->size_mask = size - 1;
  301. ring->stride = stride;
  302. ring->log_stride = ffs(ring->stride) - 1;
  303. ring->buf_size = ring->size * ring->stride;
  304. tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
  305. sizeof(struct skb_frag_struct));
  306. ring->rx_info = vmalloc(tmp);
  307. if (!ring->rx_info) {
  308. mlx4_err(mdev, "Failed allocating rx_info ring\n");
  309. return -ENOMEM;
  310. }
  311. mlx4_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
  312. ring->rx_info, tmp);
  313. err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
  314. ring->buf_size, 2 * PAGE_SIZE);
  315. if (err)
  316. goto err_ring;
  317. err = mlx4_en_map_buffer(&ring->wqres.buf);
  318. if (err) {
  319. mlx4_err(mdev, "Failed to map RX buffer\n");
  320. goto err_hwq;
  321. }
  322. ring->buf = ring->wqres.buf.direct.buf;
  323. /* Configure lro mngr */
  324. memset(&ring->lro, 0, sizeof(struct net_lro_mgr));
  325. ring->lro.dev = priv->dev;
  326. ring->lro.features = LRO_F_NAPI;
  327. ring->lro.frag_align_pad = NET_IP_ALIGN;
  328. ring->lro.ip_summed = CHECKSUM_UNNECESSARY;
  329. ring->lro.ip_summed_aggr = CHECKSUM_UNNECESSARY;
  330. ring->lro.max_desc = mdev->profile.num_lro;
  331. ring->lro.max_aggr = MAX_SKB_FRAGS;
  332. ring->lro.lro_arr = kzalloc(mdev->profile.num_lro *
  333. sizeof(struct net_lro_desc),
  334. GFP_KERNEL);
  335. if (!ring->lro.lro_arr) {
  336. mlx4_err(mdev, "Failed to allocate lro array\n");
  337. goto err_map;
  338. }
  339. ring->lro.get_frag_header = mlx4_en_get_frag_header;
  340. return 0;
  341. err_map:
  342. mlx4_en_unmap_buffer(&ring->wqres.buf);
  343. err_hwq:
  344. mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
  345. err_ring:
  346. vfree(ring->rx_info);
  347. ring->rx_info = NULL;
  348. return err;
  349. }
  350. int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
  351. {
  352. struct mlx4_en_dev *mdev = priv->mdev;
  353. struct mlx4_wqe_srq_next_seg *next;
  354. struct mlx4_en_rx_ring *ring;
  355. int i;
  356. int ring_ind;
  357. int err;
  358. int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
  359. DS_SIZE * priv->num_frags);
  360. int max_gs = (stride - sizeof(struct mlx4_wqe_srq_next_seg)) / DS_SIZE;
  361. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  362. ring = &priv->rx_ring[ring_ind];
  363. ring->prod = 0;
  364. ring->cons = 0;
  365. ring->actual_size = 0;
  366. ring->cqn = priv->rx_cq[ring_ind].mcq.cqn;
  367. ring->stride = stride;
  368. ring->log_stride = ffs(ring->stride) - 1;
  369. ring->buf_size = ring->size * ring->stride;
  370. memset(ring->buf, 0, ring->buf_size);
  371. mlx4_en_update_rx_prod_db(ring);
  372. /* Initailize all descriptors */
  373. for (i = 0; i < ring->size; i++)
  374. mlx4_en_init_rx_desc(priv, ring, i);
  375. /* Initialize page allocators */
  376. err = mlx4_en_init_allocator(priv, ring);
  377. if (err) {
  378. mlx4_err(mdev, "Failed initializing ring allocator\n");
  379. goto err_allocator;
  380. }
  381. /* Fill Rx buffers */
  382. ring->full = 0;
  383. }
  384. err = mlx4_en_fill_rx_buffers(priv);
  385. if (err)
  386. goto err_buffers;
  387. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  388. ring = &priv->rx_ring[ring_ind];
  389. mlx4_en_update_rx_prod_db(ring);
  390. /* Configure SRQ representing the ring */
  391. ring->srq.max = ring->size;
  392. ring->srq.max_gs = max_gs;
  393. ring->srq.wqe_shift = ilog2(ring->stride);
  394. for (i = 0; i < ring->srq.max; ++i) {
  395. next = get_wqe(ring, i);
  396. next->next_wqe_index =
  397. cpu_to_be16((i + 1) & (ring->srq.max - 1));
  398. }
  399. err = mlx4_srq_alloc(mdev->dev, mdev->priv_pdn, &ring->wqres.mtt,
  400. ring->wqres.db.dma, &ring->srq);
  401. if (err){
  402. mlx4_err(mdev, "Failed to allocate srq\n");
  403. goto err_srq;
  404. }
  405. ring->srq.event = mlx4_en_srq_event;
  406. }
  407. return 0;
  408. err_srq:
  409. while (ring_ind >= 0) {
  410. ring = &priv->rx_ring[ring_ind];
  411. mlx4_srq_free(mdev->dev, &ring->srq);
  412. ring_ind--;
  413. }
  414. err_buffers:
  415. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
  416. mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]);
  417. ring_ind = priv->rx_ring_num - 1;
  418. err_allocator:
  419. while (ring_ind >= 0) {
  420. mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]);
  421. ring_ind--;
  422. }
  423. return err;
  424. }
  425. void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
  426. struct mlx4_en_rx_ring *ring)
  427. {
  428. struct mlx4_en_dev *mdev = priv->mdev;
  429. kfree(ring->lro.lro_arr);
  430. mlx4_en_unmap_buffer(&ring->wqres.buf);
  431. mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
  432. vfree(ring->rx_info);
  433. ring->rx_info = NULL;
  434. }
  435. void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
  436. struct mlx4_en_rx_ring *ring)
  437. {
  438. struct mlx4_en_dev *mdev = priv->mdev;
  439. mlx4_srq_free(mdev->dev, &ring->srq);
  440. mlx4_en_free_rx_buf(priv, ring);
  441. mlx4_en_destroy_allocator(priv, ring);
  442. }
  443. /* Unmap a completed descriptor and free unused pages */
  444. static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
  445. struct mlx4_en_rx_desc *rx_desc,
  446. struct skb_frag_struct *skb_frags,
  447. struct skb_frag_struct *skb_frags_rx,
  448. struct mlx4_en_rx_alloc *page_alloc,
  449. int length)
  450. {
  451. struct mlx4_en_dev *mdev = priv->mdev;
  452. struct mlx4_en_frag_info *frag_info;
  453. int nr;
  454. dma_addr_t dma;
  455. /* Collect used fragments while replacing them in the HW descirptors */
  456. for (nr = 0; nr < priv->num_frags; nr++) {
  457. frag_info = &priv->frag_info[nr];
  458. if (length <= frag_info->frag_prefix_size)
  459. break;
  460. /* Save page reference in skb */
  461. skb_frags_rx[nr].page = skb_frags[nr].page;
  462. skb_frags_rx[nr].size = skb_frags[nr].size;
  463. skb_frags_rx[nr].page_offset = skb_frags[nr].page_offset;
  464. dma = be64_to_cpu(rx_desc->data[nr].addr);
  465. /* Allocate a replacement page */
  466. if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, page_alloc, nr))
  467. goto fail;
  468. /* Unmap buffer */
  469. pci_unmap_single(mdev->pdev, dma, skb_frags[nr].size,
  470. PCI_DMA_FROMDEVICE);
  471. }
  472. /* Adjust size of last fragment to match actual length */
  473. skb_frags_rx[nr - 1].size = length -
  474. priv->frag_info[nr - 1].frag_prefix_size;
  475. return nr;
  476. fail:
  477. /* Drop all accumulated fragments (which have already been replaced in
  478. * the descriptor) of this packet; remaining fragments are reused... */
  479. while (nr > 0) {
  480. nr--;
  481. put_page(skb_frags_rx[nr].page);
  482. }
  483. return 0;
  484. }
  485. static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
  486. struct mlx4_en_rx_desc *rx_desc,
  487. struct skb_frag_struct *skb_frags,
  488. struct mlx4_en_rx_alloc *page_alloc,
  489. unsigned int length)
  490. {
  491. struct mlx4_en_dev *mdev = priv->mdev;
  492. struct sk_buff *skb;
  493. void *va;
  494. int used_frags;
  495. dma_addr_t dma;
  496. skb = dev_alloc_skb(SMALL_PACKET_SIZE + NET_IP_ALIGN);
  497. if (!skb) {
  498. mlx4_dbg(RX_ERR, priv, "Failed allocating skb\n");
  499. return NULL;
  500. }
  501. skb->dev = priv->dev;
  502. skb_reserve(skb, NET_IP_ALIGN);
  503. skb->len = length;
  504. skb->truesize = length + sizeof(struct sk_buff);
  505. /* Get pointer to first fragment so we could copy the headers into the
  506. * (linear part of the) skb */
  507. va = page_address(skb_frags[0].page) + skb_frags[0].page_offset;
  508. if (length <= SMALL_PACKET_SIZE) {
  509. /* We are copying all relevant data to the skb - temporarily
  510. * synch buffers for the copy */
  511. dma = be64_to_cpu(rx_desc->data[0].addr);
  512. dma_sync_single_range_for_cpu(&mdev->pdev->dev, dma, 0,
  513. length, DMA_FROM_DEVICE);
  514. skb_copy_to_linear_data(skb, va, length);
  515. dma_sync_single_range_for_device(&mdev->pdev->dev, dma, 0,
  516. length, DMA_FROM_DEVICE);
  517. skb->tail += length;
  518. } else {
  519. /* Move relevant fragments to skb */
  520. used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, skb_frags,
  521. skb_shinfo(skb)->frags,
  522. page_alloc, length);
  523. skb_shinfo(skb)->nr_frags = used_frags;
  524. /* Copy headers into the skb linear buffer */
  525. memcpy(skb->data, va, HEADER_COPY_SIZE);
  526. skb->tail += HEADER_COPY_SIZE;
  527. /* Skip headers in first fragment */
  528. skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
  529. /* Adjust size of first fragment */
  530. skb_shinfo(skb)->frags[0].size -= HEADER_COPY_SIZE;
  531. skb->data_len = length - HEADER_COPY_SIZE;
  532. }
  533. return skb;
  534. }
  535. static void mlx4_en_copy_desc(struct mlx4_en_priv *priv,
  536. struct mlx4_en_rx_ring *ring,
  537. int from, int to, int num)
  538. {
  539. struct skb_frag_struct *skb_frags_from;
  540. struct skb_frag_struct *skb_frags_to;
  541. struct mlx4_en_rx_desc *rx_desc_from;
  542. struct mlx4_en_rx_desc *rx_desc_to;
  543. int from_index, to_index;
  544. int nr, i;
  545. for (i = 0; i < num; i++) {
  546. from_index = (from + i) & ring->size_mask;
  547. to_index = (to + i) & ring->size_mask;
  548. skb_frags_from = ring->rx_info + (from_index << priv->log_rx_info);
  549. skb_frags_to = ring->rx_info + (to_index << priv->log_rx_info);
  550. rx_desc_from = ring->buf + (from_index << ring->log_stride);
  551. rx_desc_to = ring->buf + (to_index << ring->log_stride);
  552. for (nr = 0; nr < priv->num_frags; nr++) {
  553. skb_frags_to[nr].page = skb_frags_from[nr].page;
  554. skb_frags_to[nr].page_offset = skb_frags_from[nr].page_offset;
  555. rx_desc_to->data[nr].addr = rx_desc_from->data[nr].addr;
  556. }
  557. }
  558. }
  559. int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
  560. {
  561. struct mlx4_en_priv *priv = netdev_priv(dev);
  562. struct mlx4_en_dev *mdev = priv->mdev;
  563. struct mlx4_cqe *cqe;
  564. struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring];
  565. struct skb_frag_struct *skb_frags;
  566. struct skb_frag_struct lro_frags[MLX4_EN_MAX_RX_FRAGS];
  567. struct mlx4_en_rx_desc *rx_desc;
  568. struct sk_buff *skb;
  569. int index;
  570. int nr;
  571. unsigned int length;
  572. int polled = 0;
  573. int ip_summed;
  574. if (!priv->port_up)
  575. return 0;
  576. /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
  577. * descriptor offset can be deduced from the CQE index instead of
  578. * reading 'cqe->index' */
  579. index = cq->mcq.cons_index & ring->size_mask;
  580. cqe = &cq->buf[index];
  581. /* Process all completed CQEs */
  582. while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
  583. cq->mcq.cons_index & cq->size)) {
  584. skb_frags = ring->rx_info + (index << priv->log_rx_info);
  585. rx_desc = ring->buf + (index << ring->log_stride);
  586. /*
  587. * make sure we read the CQE after we read the ownership bit
  588. */
  589. rmb();
  590. /* Drop packet on bad receive or bad checksum */
  591. if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
  592. MLX4_CQE_OPCODE_ERROR)) {
  593. mlx4_err(mdev, "CQE completed in error - vendor "
  594. "syndrom:%d syndrom:%d\n",
  595. ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome,
  596. ((struct mlx4_err_cqe *) cqe)->syndrome);
  597. goto next;
  598. }
  599. if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
  600. mlx4_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
  601. goto next;
  602. }
  603. /*
  604. * Packet is OK - process it.
  605. */
  606. length = be32_to_cpu(cqe->byte_cnt);
  607. ring->bytes += length;
  608. ring->packets++;
  609. if (likely(priv->rx_csum)) {
  610. if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
  611. (cqe->checksum == cpu_to_be16(0xffff))) {
  612. priv->port_stats.rx_chksum_good++;
  613. /* This packet is eligible for LRO if it is:
  614. * - DIX Ethernet (type interpretation)
  615. * - TCP/IP (v4)
  616. * - without IP options
  617. * - not an IP fragment */
  618. if (mlx4_en_can_lro(cqe->status) &&
  619. dev->features & NETIF_F_LRO) {
  620. nr = mlx4_en_complete_rx_desc(
  621. priv, rx_desc,
  622. skb_frags, lro_frags,
  623. ring->page_alloc, length);
  624. if (!nr)
  625. goto next;
  626. if (priv->vlgrp && (cqe->vlan_my_qpn &
  627. cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK))) {
  628. lro_vlan_hwaccel_receive_frags(
  629. &ring->lro, lro_frags,
  630. length, length,
  631. priv->vlgrp,
  632. be16_to_cpu(cqe->sl_vid),
  633. NULL, 0);
  634. } else
  635. lro_receive_frags(&ring->lro,
  636. lro_frags,
  637. length,
  638. length,
  639. NULL, 0);
  640. goto next;
  641. }
  642. /* LRO not possible, complete processing here */
  643. ip_summed = CHECKSUM_UNNECESSARY;
  644. INC_PERF_COUNTER(priv->pstats.lro_misses);
  645. } else {
  646. ip_summed = CHECKSUM_NONE;
  647. priv->port_stats.rx_chksum_none++;
  648. }
  649. } else {
  650. ip_summed = CHECKSUM_NONE;
  651. priv->port_stats.rx_chksum_none++;
  652. }
  653. skb = mlx4_en_rx_skb(priv, rx_desc, skb_frags,
  654. ring->page_alloc, length);
  655. if (!skb) {
  656. priv->stats.rx_dropped++;
  657. goto next;
  658. }
  659. skb->ip_summed = ip_summed;
  660. skb->protocol = eth_type_trans(skb, dev);
  661. skb_record_rx_queue(skb, cq->ring);
  662. /* Push it up the stack */
  663. if (priv->vlgrp && (be32_to_cpu(cqe->vlan_my_qpn) &
  664. MLX4_CQE_VLAN_PRESENT_MASK)) {
  665. vlan_hwaccel_receive_skb(skb, priv->vlgrp,
  666. be16_to_cpu(cqe->sl_vid));
  667. } else
  668. netif_receive_skb(skb);
  669. next:
  670. ++cq->mcq.cons_index;
  671. index = (cq->mcq.cons_index) & ring->size_mask;
  672. cqe = &cq->buf[index];
  673. if (++polled == budget) {
  674. /* We are here because we reached the NAPI budget -
  675. * flush only pending LRO sessions */
  676. lro_flush_all(&ring->lro);
  677. goto out;
  678. }
  679. }
  680. /* If CQ is empty flush all LRO sessions unconditionally */
  681. lro_flush_all(&ring->lro);
  682. out:
  683. AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
  684. mlx4_cq_set_ci(&cq->mcq);
  685. wmb(); /* ensure HW sees CQ consumer before we post new buffers */
  686. ring->cons = cq->mcq.cons_index;
  687. ring->prod += polled; /* Polled descriptors were realocated in place */
  688. if (unlikely(!ring->full)) {
  689. mlx4_en_copy_desc(priv, ring, ring->cons - polled,
  690. ring->prod - polled, polled);
  691. mlx4_en_fill_rx_buf(dev, ring);
  692. }
  693. mlx4_en_update_rx_prod_db(ring);
  694. return polled;
  695. }
  696. void mlx4_en_rx_irq(struct mlx4_cq *mcq)
  697. {
  698. struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
  699. struct mlx4_en_priv *priv = netdev_priv(cq->dev);
  700. if (priv->port_up)
  701. napi_schedule(&cq->napi);
  702. else
  703. mlx4_en_arm_cq(priv, cq);
  704. }
  705. /* Rx CQ polling - called by NAPI */
  706. int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
  707. {
  708. struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
  709. struct net_device *dev = cq->dev;
  710. struct mlx4_en_priv *priv = netdev_priv(dev);
  711. int done;
  712. done = mlx4_en_process_rx_cq(dev, cq, budget);
  713. /* If we used up all the quota - we're probably not done yet... */
  714. if (done == budget)
  715. INC_PERF_COUNTER(priv->pstats.napi_quota);
  716. else {
  717. /* Done for now */
  718. napi_complete(napi);
  719. mlx4_en_arm_cq(priv, cq);
  720. }
  721. return done;
  722. }
  723. /* Calculate the last offset position that accomodates a full fragment
  724. * (assuming fagment size = stride-align) */
  725. static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align)
  726. {
  727. u16 res = MLX4_EN_ALLOC_SIZE % stride;
  728. u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align;
  729. mlx4_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d "
  730. "res:%d offset:%d\n", stride, align, res, offset);
  731. return offset;
  732. }
  733. static int frag_sizes[] = {
  734. FRAG_SZ0,
  735. FRAG_SZ1,
  736. FRAG_SZ2,
  737. FRAG_SZ3
  738. };
  739. void mlx4_en_calc_rx_buf(struct net_device *dev)
  740. {
  741. struct mlx4_en_priv *priv = netdev_priv(dev);
  742. int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE;
  743. int buf_size = 0;
  744. int i = 0;
  745. while (buf_size < eff_mtu) {
  746. priv->frag_info[i].frag_size =
  747. (eff_mtu > buf_size + frag_sizes[i]) ?
  748. frag_sizes[i] : eff_mtu - buf_size;
  749. priv->frag_info[i].frag_prefix_size = buf_size;
  750. if (!i) {
  751. priv->frag_info[i].frag_align = NET_IP_ALIGN;
  752. priv->frag_info[i].frag_stride =
  753. ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
  754. } else {
  755. priv->frag_info[i].frag_align = 0;
  756. priv->frag_info[i].frag_stride =
  757. ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
  758. }
  759. priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset(
  760. priv, priv->frag_info[i].frag_stride,
  761. priv->frag_info[i].frag_align);
  762. buf_size += priv->frag_info[i].frag_size;
  763. i++;
  764. }
  765. priv->num_frags = i;
  766. priv->rx_skb_size = eff_mtu;
  767. priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct skb_frag_struct));
  768. mlx4_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
  769. "num_frags:%d):\n", eff_mtu, priv->num_frags);
  770. for (i = 0; i < priv->num_frags; i++) {
  771. mlx4_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d "
  772. "stride:%d last_offset:%d\n", i,
  773. priv->frag_info[i].frag_size,
  774. priv->frag_info[i].frag_prefix_size,
  775. priv->frag_info[i].frag_align,
  776. priv->frag_info[i].frag_stride,
  777. priv->frag_info[i].last_offset);
  778. }
  779. }
  780. /* RSS related functions */
  781. /* Calculate rss size and map each entry in rss table to rx ring */
  782. void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv,
  783. struct mlx4_en_rss_map *rss_map,
  784. int num_entries, int num_rings)
  785. {
  786. int i;
  787. rss_map->size = roundup_pow_of_two(num_entries);
  788. mlx4_dbg(DRV, priv, "Setting default RSS map of %d entires\n",
  789. rss_map->size);
  790. for (i = 0; i < rss_map->size; i++) {
  791. rss_map->map[i] = i % num_rings;
  792. mlx4_dbg(DRV, priv, "Entry %d ---> ring %d\n", i, rss_map->map[i]);
  793. }
  794. }
  795. static void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event)
  796. {
  797. return;
  798. }
  799. static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv,
  800. int qpn, int srqn, int cqn,
  801. enum mlx4_qp_state *state,
  802. struct mlx4_qp *qp)
  803. {
  804. struct mlx4_en_dev *mdev = priv->mdev;
  805. struct mlx4_qp_context *context;
  806. int err = 0;
  807. context = kmalloc(sizeof *context , GFP_KERNEL);
  808. if (!context) {
  809. mlx4_err(mdev, "Failed to allocate qp context\n");
  810. return -ENOMEM;
  811. }
  812. err = mlx4_qp_alloc(mdev->dev, qpn, qp);
  813. if (err) {
  814. mlx4_err(mdev, "Failed to allocate qp #%d\n", qpn);
  815. goto out;
  816. return err;
  817. }
  818. qp->event = mlx4_en_sqp_event;
  819. memset(context, 0, sizeof *context);
  820. mlx4_en_fill_qp_context(priv, 0, 0, 0, 0, qpn, cqn, srqn, context);
  821. err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, context, qp, state);
  822. if (err) {
  823. mlx4_qp_remove(mdev->dev, qp);
  824. mlx4_qp_free(mdev->dev, qp);
  825. }
  826. out:
  827. kfree(context);
  828. return err;
  829. }
  830. /* Allocate rx qp's and configure them according to rss map */
  831. int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
  832. {
  833. struct mlx4_en_dev *mdev = priv->mdev;
  834. struct mlx4_en_rss_map *rss_map = &priv->rss_map;
  835. struct mlx4_qp_context context;
  836. struct mlx4_en_rss_context *rss_context;
  837. void *ptr;
  838. int rss_xor = mdev->profile.rss_xor;
  839. u8 rss_mask = mdev->profile.rss_mask;
  840. int i, srqn, qpn, cqn;
  841. int err = 0;
  842. int good_qps = 0;
  843. mlx4_dbg(DRV, priv, "Configuring rss steering for port %u\n", priv->port);
  844. err = mlx4_qp_reserve_range(mdev->dev, rss_map->size,
  845. rss_map->size, &rss_map->base_qpn);
  846. if (err) {
  847. mlx4_err(mdev, "Failed reserving %d qps for port %u\n",
  848. rss_map->size, priv->port);
  849. return err;
  850. }
  851. for (i = 0; i < rss_map->size; i++) {
  852. cqn = priv->rx_ring[rss_map->map[i]].cqn;
  853. srqn = priv->rx_ring[rss_map->map[i]].srq.srqn;
  854. qpn = rss_map->base_qpn + i;
  855. err = mlx4_en_config_rss_qp(priv, qpn, srqn, cqn,
  856. &rss_map->state[i],
  857. &rss_map->qps[i]);
  858. if (err)
  859. goto rss_err;
  860. ++good_qps;
  861. }
  862. /* Configure RSS indirection qp */
  863. err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &priv->base_qpn);
  864. if (err) {
  865. mlx4_err(mdev, "Failed to reserve range for RSS "
  866. "indirection qp\n");
  867. goto rss_err;
  868. }
  869. err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
  870. if (err) {
  871. mlx4_err(mdev, "Failed to allocate RSS indirection QP\n");
  872. goto reserve_err;
  873. }
  874. rss_map->indir_qp.event = mlx4_en_sqp_event;
  875. mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
  876. priv->rx_ring[0].cqn, 0, &context);
  877. ptr = ((void *) &context) + 0x3c;
  878. rss_context = (struct mlx4_en_rss_context *) ptr;
  879. rss_context->base_qpn = cpu_to_be32(ilog2(rss_map->size) << 24 |
  880. (rss_map->base_qpn));
  881. rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
  882. rss_context->hash_fn = rss_xor & 0x3;
  883. rss_context->flags = rss_mask << 2;
  884. err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
  885. &rss_map->indir_qp, &rss_map->indir_state);
  886. if (err)
  887. goto indir_err;
  888. return 0;
  889. indir_err:
  890. mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
  891. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
  892. mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
  893. mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
  894. reserve_err:
  895. mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1);
  896. rss_err:
  897. for (i = 0; i < good_qps; i++) {
  898. mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
  899. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
  900. mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
  901. mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
  902. }
  903. mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, rss_map->size);
  904. return err;
  905. }
  906. void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
  907. {
  908. struct mlx4_en_dev *mdev = priv->mdev;
  909. struct mlx4_en_rss_map *rss_map = &priv->rss_map;
  910. int i;
  911. mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
  912. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
  913. mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
  914. mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
  915. mlx4_qp_release_range(mdev->dev, priv->base_qpn, 1);
  916. for (i = 0; i < rss_map->size; i++) {
  917. mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
  918. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
  919. mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
  920. mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
  921. }
  922. mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, rss_map->size);
  923. }