mipsnet.c 8.0 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. */
  6. #include <linux/init.h>
  7. #include <linux/io.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/netdevice.h>
  11. #include <linux/etherdevice.h>
  12. #include <linux/platform_device.h>
  13. #include <asm/mips-boards/simint.h>
  14. #define MIPSNET_VERSION "2007-11-17"
  15. /*
  16. * Net status/control block as seen by sw in the core.
  17. */
  18. struct mipsnet_regs {
  19. /*
  20. * Device info for probing, reads as MIPSNET%d where %d is some
  21. * form of version.
  22. */
  23. u64 devId; /*0x00 */
  24. /*
  25. * read only busy flag.
  26. * Set and cleared by the Net Device to indicate that an rx or a tx
  27. * is in progress.
  28. */
  29. u32 busy; /*0x08 */
  30. /*
  31. * Set by the Net Device.
  32. * The device will set it once data has been received.
  33. * The value is the number of bytes that should be read from
  34. * rxDataBuffer. The value will decrease till 0 until all the data
  35. * from rxDataBuffer has been read.
  36. */
  37. u32 rxDataCount; /*0x0c */
  38. #define MIPSNET_MAX_RXTX_DATACOUNT (1 << 16)
  39. /*
  40. * Settable from the MIPS core, cleared by the Net Device.
  41. * The core should set the number of bytes it wants to send,
  42. * then it should write those bytes of data to txDataBuffer.
  43. * The device will clear txDataCount has been processed (not
  44. * necessarily sent).
  45. */
  46. u32 txDataCount; /*0x10 */
  47. /*
  48. * Interrupt control
  49. *
  50. * Used to clear the interrupted generated by this dev.
  51. * Write a 1 to clear the interrupt. (except bit31).
  52. *
  53. * Bit0 is set if it was a tx-done interrupt.
  54. * Bit1 is set when new rx-data is available.
  55. * Until this bit is cleared there will be no other RXs.
  56. *
  57. * Bit31 is used for testing, it clears after a read.
  58. * Writing 1 to this bit will cause an interrupt to be generated.
  59. * To clear the test interrupt, write 0 to this register.
  60. */
  61. u32 interruptControl; /*0x14 */
  62. #define MIPSNET_INTCTL_TXDONE (1u << 0)
  63. #define MIPSNET_INTCTL_RXDONE (1u << 1)
  64. #define MIPSNET_INTCTL_TESTBIT (1u << 31)
  65. /*
  66. * Readonly core-specific interrupt info for the device to signal
  67. * the core. The meaning of the contents of this field might change.
  68. */
  69. /* XXX: the whole memIntf interrupt scheme is messy: the device
  70. * should have no control what so ever of what VPE/register set is
  71. * being used.
  72. * The MemIntf should only expose interrupt lines, and something in
  73. * the config should be responsible for the line<->core/vpe bindings.
  74. */
  75. u32 interruptInfo; /*0x18 */
  76. /*
  77. * This is where the received data is read out.
  78. * There is more data to read until rxDataReady is 0.
  79. * Only 1 byte at this regs offset is used.
  80. */
  81. u32 rxDataBuffer; /*0x1c */
  82. /*
  83. * This is where the data to transmit is written.
  84. * Data should be written for the amount specified in the
  85. * txDataCount register.
  86. * Only 1 byte at this regs offset is used.
  87. */
  88. u32 txDataBuffer; /*0x20 */
  89. };
  90. #define regaddr(dev, field) \
  91. (dev->base_addr + offsetof(struct mipsnet_regs, field))
  92. static char mipsnet_string[] = "mipsnet";
  93. /*
  94. * Copy data from the MIPSNET rx data port
  95. */
  96. static int ioiocpy_frommipsnet(struct net_device *dev, unsigned char *kdata,
  97. int len)
  98. {
  99. for (; len > 0; len--, kdata++)
  100. *kdata = inb(regaddr(dev, rxDataBuffer));
  101. return inl(regaddr(dev, rxDataCount));
  102. }
  103. static inline void mipsnet_put_todevice(struct net_device *dev,
  104. struct sk_buff *skb)
  105. {
  106. int count_to_go = skb->len;
  107. char *buf_ptr = skb->data;
  108. outl(skb->len, regaddr(dev, txDataCount));
  109. for (; count_to_go; buf_ptr++, count_to_go--)
  110. outb(*buf_ptr, regaddr(dev, txDataBuffer));
  111. dev->stats.tx_packets++;
  112. dev->stats.tx_bytes += skb->len;
  113. dev_kfree_skb(skb);
  114. }
  115. static int mipsnet_xmit(struct sk_buff *skb, struct net_device *dev)
  116. {
  117. /*
  118. * Only one packet at a time. Once TXDONE interrupt is serviced, the
  119. * queue will be restarted.
  120. */
  121. netif_stop_queue(dev);
  122. mipsnet_put_todevice(dev, skb);
  123. return 0;
  124. }
  125. static inline ssize_t mipsnet_get_fromdev(struct net_device *dev, size_t len)
  126. {
  127. struct sk_buff *skb;
  128. if (!len)
  129. return len;
  130. skb = dev_alloc_skb(len + NET_IP_ALIGN);
  131. if (!skb) {
  132. dev->stats.rx_dropped++;
  133. return -ENOMEM;
  134. }
  135. skb_reserve(skb, NET_IP_ALIGN);
  136. if (ioiocpy_frommipsnet(dev, skb_put(skb, len), len))
  137. return -EFAULT;
  138. skb->protocol = eth_type_trans(skb, dev);
  139. skb->ip_summed = CHECKSUM_UNNECESSARY;
  140. netif_rx(skb);
  141. dev->stats.rx_packets++;
  142. dev->stats.rx_bytes += len;
  143. return len;
  144. }
  145. static irqreturn_t mipsnet_interrupt(int irq, void *dev_id)
  146. {
  147. struct net_device *dev = dev_id;
  148. u32 int_flags;
  149. irqreturn_t ret = IRQ_NONE;
  150. if (irq != dev->irq)
  151. goto out_badirq;
  152. /* TESTBIT is cleared on read. */
  153. int_flags = inl(regaddr(dev, interruptControl));
  154. if (int_flags & MIPSNET_INTCTL_TESTBIT) {
  155. /* TESTBIT takes effect after a write with 0. */
  156. outl(0, regaddr(dev, interruptControl));
  157. ret = IRQ_HANDLED;
  158. } else if (int_flags & MIPSNET_INTCTL_TXDONE) {
  159. /* Only one packet at a time, we are done. */
  160. dev->stats.tx_packets++;
  161. netif_wake_queue(dev);
  162. outl(MIPSNET_INTCTL_TXDONE,
  163. regaddr(dev, interruptControl));
  164. ret = IRQ_HANDLED;
  165. } else if (int_flags & MIPSNET_INTCTL_RXDONE) {
  166. mipsnet_get_fromdev(dev, inl(regaddr(dev, rxDataCount)));
  167. outl(MIPSNET_INTCTL_RXDONE, regaddr(dev, interruptControl));
  168. ret = IRQ_HANDLED;
  169. }
  170. return ret;
  171. out_badirq:
  172. printk(KERN_INFO "%s: %s(): irq %d for unknown device\n",
  173. dev->name, __func__, irq);
  174. return ret;
  175. }
  176. static int mipsnet_open(struct net_device *dev)
  177. {
  178. int err;
  179. err = request_irq(dev->irq, &mipsnet_interrupt,
  180. IRQF_SHARED, dev->name, (void *) dev);
  181. if (err) {
  182. release_region(dev->base_addr, sizeof(struct mipsnet_regs));
  183. return err;
  184. }
  185. netif_start_queue(dev);
  186. /* test interrupt handler */
  187. outl(MIPSNET_INTCTL_TESTBIT, regaddr(dev, interruptControl));
  188. return 0;
  189. }
  190. static int mipsnet_close(struct net_device *dev)
  191. {
  192. netif_stop_queue(dev);
  193. free_irq(dev->irq, dev);
  194. return 0;
  195. }
  196. static void mipsnet_set_mclist(struct net_device *dev)
  197. {
  198. }
  199. static int __init mipsnet_probe(struct platform_device *dev)
  200. {
  201. struct net_device *netdev;
  202. int err;
  203. netdev = alloc_etherdev(0);
  204. if (!netdev) {
  205. err = -ENOMEM;
  206. goto out;
  207. }
  208. platform_set_drvdata(dev, netdev);
  209. netdev->open = mipsnet_open;
  210. netdev->stop = mipsnet_close;
  211. netdev->hard_start_xmit = mipsnet_xmit;
  212. netdev->set_multicast_list = mipsnet_set_mclist;
  213. /*
  214. * TODO: probe for these or load them from PARAM
  215. */
  216. netdev->base_addr = 0x4200;
  217. netdev->irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB0 +
  218. inl(regaddr(netdev, interruptInfo));
  219. /* Get the io region now, get irq on open() */
  220. if (!request_region(netdev->base_addr, sizeof(struct mipsnet_regs),
  221. "mipsnet")) {
  222. err = -EBUSY;
  223. goto out_free_netdev;
  224. }
  225. /*
  226. * Lacking any better mechanism to allocate a MAC address we use a
  227. * random one ...
  228. */
  229. random_ether_addr(netdev->dev_addr);
  230. err = register_netdev(netdev);
  231. if (err) {
  232. printk(KERN_ERR "MIPSNet: failed to register netdev.\n");
  233. goto out_free_region;
  234. }
  235. return 0;
  236. out_free_region:
  237. release_region(netdev->base_addr, sizeof(struct mipsnet_regs));
  238. out_free_netdev:
  239. free_netdev(netdev);
  240. out:
  241. return err;
  242. }
  243. static int __devexit mipsnet_device_remove(struct platform_device *device)
  244. {
  245. struct net_device *dev = platform_get_drvdata(device);
  246. unregister_netdev(dev);
  247. release_region(dev->base_addr, sizeof(struct mipsnet_regs));
  248. free_netdev(dev);
  249. platform_set_drvdata(device, NULL);
  250. return 0;
  251. }
  252. static struct platform_driver mipsnet_driver = {
  253. .driver = {
  254. .name = mipsnet_string,
  255. .owner = THIS_MODULE,
  256. },
  257. .probe = mipsnet_probe,
  258. .remove = __devexit_p(mipsnet_device_remove),
  259. };
  260. static int __init mipsnet_init_module(void)
  261. {
  262. int err;
  263. printk(KERN_INFO "MIPSNet Ethernet driver. Version: %s. "
  264. "(c)2005 MIPS Technologies, Inc.\n", MIPSNET_VERSION);
  265. err = platform_driver_register(&mipsnet_driver);
  266. if (err)
  267. printk(KERN_ERR "Driver registration failed\n");
  268. return err;
  269. }
  270. static void __exit mipsnet_exit_module(void)
  271. {
  272. platform_driver_unregister(&mipsnet_driver);
  273. }
  274. module_init(mipsnet_init_module);
  275. module_exit(mipsnet_exit_module);