mac-fec.c 12 KB

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  1. /*
  2. * Freescale Ethernet controllers
  3. *
  4. * Copyright (c) 2005 Intracom S.A.
  5. * by Pantelis Antoniou <panto@intracom.gr>
  6. *
  7. * 2005 (c) MontaVista Software, Inc.
  8. * Vitaly Bordug <vbordug@ru.mvista.com>
  9. *
  10. * This file is licensed under the terms of the GNU General Public License
  11. * version 2. This program is licensed "as is" without any warranty of any
  12. * kind, whether express or implied.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/kernel.h>
  16. #include <linux/types.h>
  17. #include <linux/string.h>
  18. #include <linux/ptrace.h>
  19. #include <linux/errno.h>
  20. #include <linux/ioport.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/etherdevice.h>
  27. #include <linux/skbuff.h>
  28. #include <linux/spinlock.h>
  29. #include <linux/mii.h>
  30. #include <linux/ethtool.h>
  31. #include <linux/bitops.h>
  32. #include <linux/fs.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/of_device.h>
  35. #include <asm/irq.h>
  36. #include <asm/uaccess.h>
  37. #ifdef CONFIG_8xx
  38. #include <asm/8xx_immap.h>
  39. #include <asm/pgtable.h>
  40. #include <asm/mpc8xx.h>
  41. #include <asm/cpm1.h>
  42. #endif
  43. #include "fs_enet.h"
  44. #include "fec.h"
  45. /*************************************************/
  46. #if defined(CONFIG_CPM1)
  47. /* for a CPM1 __raw_xxx's are sufficient */
  48. #define __fs_out32(addr, x) __raw_writel(x, addr)
  49. #define __fs_out16(addr, x) __raw_writew(x, addr)
  50. #define __fs_in32(addr) __raw_readl(addr)
  51. #define __fs_in16(addr) __raw_readw(addr)
  52. #else
  53. /* for others play it safe */
  54. #define __fs_out32(addr, x) out_be32(addr, x)
  55. #define __fs_out16(addr, x) out_be16(addr, x)
  56. #define __fs_in32(addr) in_be32(addr)
  57. #define __fs_in16(addr) in_be16(addr)
  58. #endif
  59. /* write */
  60. #define FW(_fecp, _reg, _v) __fs_out32(&(_fecp)->fec_ ## _reg, (_v))
  61. /* read */
  62. #define FR(_fecp, _reg) __fs_in32(&(_fecp)->fec_ ## _reg)
  63. /* set bits */
  64. #define FS(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) | (_v))
  65. /* clear bits */
  66. #define FC(_fecp, _reg, _v) FW(_fecp, _reg, FR(_fecp, _reg) & ~(_v))
  67. /*
  68. * Delay to wait for FEC reset command to complete (in us)
  69. */
  70. #define FEC_RESET_DELAY 50
  71. static int whack_reset(fec_t __iomem *fecp)
  72. {
  73. int i;
  74. FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET);
  75. for (i = 0; i < FEC_RESET_DELAY; i++) {
  76. if ((FR(fecp, ecntrl) & FEC_ECNTRL_RESET) == 0)
  77. return 0; /* OK */
  78. udelay(1);
  79. }
  80. return -1;
  81. }
  82. static int do_pd_setup(struct fs_enet_private *fep)
  83. {
  84. struct of_device *ofdev = to_of_device(fep->dev);
  85. fep->interrupt = of_irq_to_resource(ofdev->node, 0, NULL);
  86. if (fep->interrupt == NO_IRQ)
  87. return -EINVAL;
  88. fep->fec.fecp = of_iomap(ofdev->node, 0);
  89. if (!fep->fcc.fccp)
  90. return -EINVAL;
  91. return 0;
  92. }
  93. #define FEC_NAPI_RX_EVENT_MSK (FEC_ENET_RXF | FEC_ENET_RXB)
  94. #define FEC_RX_EVENT (FEC_ENET_RXF)
  95. #define FEC_TX_EVENT (FEC_ENET_TXF)
  96. #define FEC_ERR_EVENT_MSK (FEC_ENET_HBERR | FEC_ENET_BABR | \
  97. FEC_ENET_BABT | FEC_ENET_EBERR)
  98. static int setup_data(struct net_device *dev)
  99. {
  100. struct fs_enet_private *fep = netdev_priv(dev);
  101. if (do_pd_setup(fep) != 0)
  102. return -EINVAL;
  103. fep->fec.hthi = 0;
  104. fep->fec.htlo = 0;
  105. fep->ev_napi_rx = FEC_NAPI_RX_EVENT_MSK;
  106. fep->ev_rx = FEC_RX_EVENT;
  107. fep->ev_tx = FEC_TX_EVENT;
  108. fep->ev_err = FEC_ERR_EVENT_MSK;
  109. return 0;
  110. }
  111. static int allocate_bd(struct net_device *dev)
  112. {
  113. struct fs_enet_private *fep = netdev_priv(dev);
  114. const struct fs_platform_info *fpi = fep->fpi;
  115. fep->ring_base = (void __force __iomem *)dma_alloc_coherent(fep->dev,
  116. (fpi->tx_ring + fpi->rx_ring) *
  117. sizeof(cbd_t), &fep->ring_mem_addr,
  118. GFP_KERNEL);
  119. if (fep->ring_base == NULL)
  120. return -ENOMEM;
  121. return 0;
  122. }
  123. static void free_bd(struct net_device *dev)
  124. {
  125. struct fs_enet_private *fep = netdev_priv(dev);
  126. const struct fs_platform_info *fpi = fep->fpi;
  127. if(fep->ring_base)
  128. dma_free_coherent(fep->dev, (fpi->tx_ring + fpi->rx_ring)
  129. * sizeof(cbd_t),
  130. (void __force *)fep->ring_base,
  131. fep->ring_mem_addr);
  132. }
  133. static void cleanup_data(struct net_device *dev)
  134. {
  135. /* nothing */
  136. }
  137. static void set_promiscuous_mode(struct net_device *dev)
  138. {
  139. struct fs_enet_private *fep = netdev_priv(dev);
  140. fec_t __iomem *fecp = fep->fec.fecp;
  141. FS(fecp, r_cntrl, FEC_RCNTRL_PROM);
  142. }
  143. static void set_multicast_start(struct net_device *dev)
  144. {
  145. struct fs_enet_private *fep = netdev_priv(dev);
  146. fep->fec.hthi = 0;
  147. fep->fec.htlo = 0;
  148. }
  149. static void set_multicast_one(struct net_device *dev, const u8 *mac)
  150. {
  151. struct fs_enet_private *fep = netdev_priv(dev);
  152. int temp, hash_index, i, j;
  153. u32 crc, csrVal;
  154. u8 byte, msb;
  155. crc = 0xffffffff;
  156. for (i = 0; i < 6; i++) {
  157. byte = mac[i];
  158. for (j = 0; j < 8; j++) {
  159. msb = crc >> 31;
  160. crc <<= 1;
  161. if (msb ^ (byte & 0x1))
  162. crc ^= FEC_CRC_POLY;
  163. byte >>= 1;
  164. }
  165. }
  166. temp = (crc & 0x3f) >> 1;
  167. hash_index = ((temp & 0x01) << 4) |
  168. ((temp & 0x02) << 2) |
  169. ((temp & 0x04)) |
  170. ((temp & 0x08) >> 2) |
  171. ((temp & 0x10) >> 4);
  172. csrVal = 1 << hash_index;
  173. if (crc & 1)
  174. fep->fec.hthi |= csrVal;
  175. else
  176. fep->fec.htlo |= csrVal;
  177. }
  178. static void set_multicast_finish(struct net_device *dev)
  179. {
  180. struct fs_enet_private *fep = netdev_priv(dev);
  181. fec_t __iomem *fecp = fep->fec.fecp;
  182. /* if all multi or too many multicasts; just enable all */
  183. if ((dev->flags & IFF_ALLMULTI) != 0 ||
  184. dev->mc_count > FEC_MAX_MULTICAST_ADDRS) {
  185. fep->fec.hthi = 0xffffffffU;
  186. fep->fec.htlo = 0xffffffffU;
  187. }
  188. FC(fecp, r_cntrl, FEC_RCNTRL_PROM);
  189. FW(fecp, hash_table_high, fep->fec.hthi);
  190. FW(fecp, hash_table_low, fep->fec.htlo);
  191. }
  192. static void set_multicast_list(struct net_device *dev)
  193. {
  194. struct dev_mc_list *pmc;
  195. if ((dev->flags & IFF_PROMISC) == 0) {
  196. set_multicast_start(dev);
  197. for (pmc = dev->mc_list; pmc != NULL; pmc = pmc->next)
  198. set_multicast_one(dev, pmc->dmi_addr);
  199. set_multicast_finish(dev);
  200. } else
  201. set_promiscuous_mode(dev);
  202. }
  203. static void restart(struct net_device *dev)
  204. {
  205. #ifdef CONFIG_DUET
  206. immap_t *immap = fs_enet_immap;
  207. u32 cptr;
  208. #endif
  209. struct fs_enet_private *fep = netdev_priv(dev);
  210. fec_t __iomem *fecp = fep->fec.fecp;
  211. const struct fs_platform_info *fpi = fep->fpi;
  212. dma_addr_t rx_bd_base_phys, tx_bd_base_phys;
  213. int r;
  214. u32 addrhi, addrlo;
  215. struct mii_bus* mii = fep->phydev->bus;
  216. struct fec_info* fec_inf = mii->priv;
  217. r = whack_reset(fep->fec.fecp);
  218. if (r != 0)
  219. printk(KERN_ERR DRV_MODULE_NAME
  220. ": %s FEC Reset FAILED!\n", dev->name);
  221. /*
  222. * Set station address.
  223. */
  224. addrhi = ((u32) dev->dev_addr[0] << 24) |
  225. ((u32) dev->dev_addr[1] << 16) |
  226. ((u32) dev->dev_addr[2] << 8) |
  227. (u32) dev->dev_addr[3];
  228. addrlo = ((u32) dev->dev_addr[4] << 24) |
  229. ((u32) dev->dev_addr[5] << 16);
  230. FW(fecp, addr_low, addrhi);
  231. FW(fecp, addr_high, addrlo);
  232. /*
  233. * Reset all multicast.
  234. */
  235. FW(fecp, hash_table_high, fep->fec.hthi);
  236. FW(fecp, hash_table_low, fep->fec.htlo);
  237. /*
  238. * Set maximum receive buffer size.
  239. */
  240. FW(fecp, r_buff_size, PKT_MAXBLR_SIZE);
  241. FW(fecp, r_hash, PKT_MAXBUF_SIZE);
  242. /* get physical address */
  243. rx_bd_base_phys = fep->ring_mem_addr;
  244. tx_bd_base_phys = rx_bd_base_phys + sizeof(cbd_t) * fpi->rx_ring;
  245. /*
  246. * Set receive and transmit descriptor base.
  247. */
  248. FW(fecp, r_des_start, rx_bd_base_phys);
  249. FW(fecp, x_des_start, tx_bd_base_phys);
  250. fs_init_bds(dev);
  251. /*
  252. * Enable big endian and don't care about SDMA FC.
  253. */
  254. FW(fecp, fun_code, 0x78000000);
  255. /*
  256. * Set MII speed.
  257. */
  258. FW(fecp, mii_speed, fec_inf->mii_speed);
  259. /*
  260. * Clear any outstanding interrupt.
  261. */
  262. FW(fecp, ievent, 0xffc0);
  263. FW(fecp, ivec, (virq_to_hw(fep->interrupt) / 2) << 29);
  264. /*
  265. * adjust to speed (only for DUET & RMII)
  266. */
  267. #ifdef CONFIG_DUET
  268. if (fpi->use_rmii) {
  269. cptr = in_be32(&immap->im_cpm.cp_cptr);
  270. switch (fs_get_fec_index(fpi->fs_no)) {
  271. case 0:
  272. cptr |= 0x100;
  273. if (fep->speed == 10)
  274. cptr |= 0x0000010;
  275. else if (fep->speed == 100)
  276. cptr &= ~0x0000010;
  277. break;
  278. case 1:
  279. cptr |= 0x80;
  280. if (fep->speed == 10)
  281. cptr |= 0x0000008;
  282. else if (fep->speed == 100)
  283. cptr &= ~0x0000008;
  284. break;
  285. default:
  286. BUG(); /* should never happen */
  287. break;
  288. }
  289. out_be32(&immap->im_cpm.cp_cptr, cptr);
  290. }
  291. #endif
  292. FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
  293. /*
  294. * adjust to duplex mode
  295. */
  296. if (fep->phydev->duplex) {
  297. FC(fecp, r_cntrl, FEC_RCNTRL_DRT);
  298. FS(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */
  299. } else {
  300. FS(fecp, r_cntrl, FEC_RCNTRL_DRT);
  301. FC(fecp, x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */
  302. }
  303. /*
  304. * Enable interrupts we wish to service.
  305. */
  306. FW(fecp, imask, FEC_ENET_TXF | FEC_ENET_TXB |
  307. FEC_ENET_RXF | FEC_ENET_RXB);
  308. /*
  309. * And last, enable the transmit and receive processing.
  310. */
  311. FW(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
  312. FW(fecp, r_des_active, 0x01000000);
  313. }
  314. static void stop(struct net_device *dev)
  315. {
  316. struct fs_enet_private *fep = netdev_priv(dev);
  317. const struct fs_platform_info *fpi = fep->fpi;
  318. fec_t __iomem *fecp = fep->fec.fecp;
  319. struct fec_info* feci= fep->phydev->bus->priv;
  320. int i;
  321. if ((FR(fecp, ecntrl) & FEC_ECNTRL_ETHER_EN) == 0)
  322. return; /* already down */
  323. FW(fecp, x_cntrl, 0x01); /* Graceful transmit stop */
  324. for (i = 0; ((FR(fecp, ievent) & 0x10000000) == 0) &&
  325. i < FEC_RESET_DELAY; i++)
  326. udelay(1);
  327. if (i == FEC_RESET_DELAY)
  328. printk(KERN_WARNING DRV_MODULE_NAME
  329. ": %s FEC timeout on graceful transmit stop\n",
  330. dev->name);
  331. /*
  332. * Disable FEC. Let only MII interrupts.
  333. */
  334. FW(fecp, imask, 0);
  335. FC(fecp, ecntrl, FEC_ECNTRL_ETHER_EN);
  336. fs_cleanup_bds(dev);
  337. /* shut down FEC1? that's where the mii bus is */
  338. if (fpi->has_phy) {
  339. FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
  340. FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
  341. FW(fecp, ievent, FEC_ENET_MII);
  342. FW(fecp, mii_speed, feci->mii_speed);
  343. }
  344. }
  345. static void napi_clear_rx_event(struct net_device *dev)
  346. {
  347. struct fs_enet_private *fep = netdev_priv(dev);
  348. fec_t __iomem *fecp = fep->fec.fecp;
  349. FW(fecp, ievent, FEC_NAPI_RX_EVENT_MSK);
  350. }
  351. static void napi_enable_rx(struct net_device *dev)
  352. {
  353. struct fs_enet_private *fep = netdev_priv(dev);
  354. fec_t __iomem *fecp = fep->fec.fecp;
  355. FS(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
  356. }
  357. static void napi_disable_rx(struct net_device *dev)
  358. {
  359. struct fs_enet_private *fep = netdev_priv(dev);
  360. fec_t __iomem *fecp = fep->fec.fecp;
  361. FC(fecp, imask, FEC_NAPI_RX_EVENT_MSK);
  362. }
  363. static void rx_bd_done(struct net_device *dev)
  364. {
  365. struct fs_enet_private *fep = netdev_priv(dev);
  366. fec_t __iomem *fecp = fep->fec.fecp;
  367. FW(fecp, r_des_active, 0x01000000);
  368. }
  369. static void tx_kickstart(struct net_device *dev)
  370. {
  371. struct fs_enet_private *fep = netdev_priv(dev);
  372. fec_t __iomem *fecp = fep->fec.fecp;
  373. FW(fecp, x_des_active, 0x01000000);
  374. }
  375. static u32 get_int_events(struct net_device *dev)
  376. {
  377. struct fs_enet_private *fep = netdev_priv(dev);
  378. fec_t __iomem *fecp = fep->fec.fecp;
  379. return FR(fecp, ievent) & FR(fecp, imask);
  380. }
  381. static void clear_int_events(struct net_device *dev, u32 int_events)
  382. {
  383. struct fs_enet_private *fep = netdev_priv(dev);
  384. fec_t __iomem *fecp = fep->fec.fecp;
  385. FW(fecp, ievent, int_events);
  386. }
  387. static void ev_error(struct net_device *dev, u32 int_events)
  388. {
  389. printk(KERN_WARNING DRV_MODULE_NAME
  390. ": %s FEC ERROR(s) 0x%x\n", dev->name, int_events);
  391. }
  392. static int get_regs(struct net_device *dev, void *p, int *sizep)
  393. {
  394. struct fs_enet_private *fep = netdev_priv(dev);
  395. if (*sizep < sizeof(fec_t))
  396. return -EINVAL;
  397. memcpy_fromio(p, fep->fec.fecp, sizeof(fec_t));
  398. return 0;
  399. }
  400. static int get_regs_len(struct net_device *dev)
  401. {
  402. return sizeof(fec_t);
  403. }
  404. static void tx_restart(struct net_device *dev)
  405. {
  406. /* nothing */
  407. }
  408. /*************************************************************************/
  409. const struct fs_ops fs_fec_ops = {
  410. .setup_data = setup_data,
  411. .cleanup_data = cleanup_data,
  412. .set_multicast_list = set_multicast_list,
  413. .restart = restart,
  414. .stop = stop,
  415. .napi_clear_rx_event = napi_clear_rx_event,
  416. .napi_enable_rx = napi_enable_rx,
  417. .napi_disable_rx = napi_disable_rx,
  418. .rx_bd_done = rx_bd_done,
  419. .tx_kickstart = tx_kickstart,
  420. .get_int_events = get_int_events,
  421. .clear_int_events = clear_int_events,
  422. .ev_error = ev_error,
  423. .get_regs = get_regs,
  424. .get_regs_len = get_regs_len,
  425. .tx_restart = tx_restart,
  426. .allocate_bd = allocate_bd,
  427. .free_bd = free_bd,
  428. };