common.h 12 KB

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  1. /*****************************************************************************
  2. * *
  3. * File: common.h *
  4. * $Revision: 1.21 $ *
  5. * $Date: 2005/06/22 00:43:25 $ *
  6. * Description: *
  7. * part of the Chelsio 10Gb Ethernet Driver. *
  8. * *
  9. * This program is free software; you can redistribute it and/or modify *
  10. * it under the terms of the GNU General Public License, version 2, as *
  11. * published by the Free Software Foundation. *
  12. * *
  13. * You should have received a copy of the GNU General Public License along *
  14. * with this program; if not, write to the Free Software Foundation, Inc., *
  15. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
  16. * *
  17. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
  18. * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
  19. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
  20. * *
  21. * http://www.chelsio.com *
  22. * *
  23. * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
  24. * All rights reserved. *
  25. * *
  26. * Maintainers: maintainers@chelsio.com *
  27. * *
  28. * Authors: Dimitrios Michailidis <dm@chelsio.com> *
  29. * Tina Yang <tainay@chelsio.com> *
  30. * Felix Marti <felix@chelsio.com> *
  31. * Scott Bardone <sbardone@chelsio.com> *
  32. * Kurt Ottaway <kottaway@chelsio.com> *
  33. * Frank DiMambro <frank@chelsio.com> *
  34. * *
  35. * History: *
  36. * *
  37. ****************************************************************************/
  38. #ifndef _CXGB_COMMON_H_
  39. #define _CXGB_COMMON_H_
  40. #include <linux/module.h>
  41. #include <linux/netdevice.h>
  42. #include <linux/types.h>
  43. #include <linux/delay.h>
  44. #include <linux/pci.h>
  45. #include <linux/ethtool.h>
  46. #include <linux/if_vlan.h>
  47. #include <linux/mii.h>
  48. #include <linux/crc32.h>
  49. #include <linux/init.h>
  50. #include <asm/io.h>
  51. #include <linux/pci_ids.h>
  52. #define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver"
  53. #define DRV_NAME "cxgb"
  54. #define DRV_VERSION "2.2"
  55. #define PFX DRV_NAME ": "
  56. #define CH_ERR(fmt, ...) printk(KERN_ERR PFX fmt, ## __VA_ARGS__)
  57. #define CH_WARN(fmt, ...) printk(KERN_WARNING PFX fmt, ## __VA_ARGS__)
  58. #define CH_ALERT(fmt, ...) printk(KERN_ALERT PFX fmt, ## __VA_ARGS__)
  59. /*
  60. * More powerful macro that selectively prints messages based on msg_enable.
  61. * For info and debugging messages.
  62. */
  63. #define CH_MSG(adapter, level, category, fmt, ...) do { \
  64. if ((adapter)->msg_enable & NETIF_MSG_##category) \
  65. printk(KERN_##level PFX "%s: " fmt, (adapter)->name, \
  66. ## __VA_ARGS__); \
  67. } while (0)
  68. #ifdef DEBUG
  69. # define CH_DBG(adapter, category, fmt, ...) \
  70. CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__)
  71. #else
  72. # define CH_DBG(fmt, ...)
  73. #endif
  74. #define CH_DEVICE(devid, ssid, idx) \
  75. { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }
  76. #define SUPPORTED_PAUSE (1 << 13)
  77. #define SUPPORTED_LOOPBACK (1 << 15)
  78. #define ADVERTISED_PAUSE (1 << 13)
  79. #define ADVERTISED_ASYM_PAUSE (1 << 14)
  80. typedef struct adapter adapter_t;
  81. struct t1_rx_mode {
  82. struct net_device *dev;
  83. u32 idx;
  84. struct dev_mc_list *list;
  85. };
  86. #define t1_rx_mode_promisc(rm) (rm->dev->flags & IFF_PROMISC)
  87. #define t1_rx_mode_allmulti(rm) (rm->dev->flags & IFF_ALLMULTI)
  88. #define t1_rx_mode_mc_cnt(rm) (rm->dev->mc_count)
  89. static inline u8 *t1_get_next_mcaddr(struct t1_rx_mode *rm)
  90. {
  91. u8 *addr = NULL;
  92. if (rm->idx++ < rm->dev->mc_count) {
  93. addr = rm->list->dmi_addr;
  94. rm->list = rm->list->next;
  95. }
  96. return addr;
  97. }
  98. #define MAX_NPORTS 4
  99. #define PORT_MASK ((1 << MAX_NPORTS) - 1)
  100. #define NMTUS 8
  101. #define TCB_SIZE 128
  102. #define SPEED_INVALID 0xffff
  103. #define DUPLEX_INVALID 0xff
  104. enum {
  105. CHBT_BOARD_N110,
  106. CHBT_BOARD_N210,
  107. CHBT_BOARD_7500,
  108. CHBT_BOARD_8000,
  109. CHBT_BOARD_CHT101,
  110. CHBT_BOARD_CHT110,
  111. CHBT_BOARD_CHT210,
  112. CHBT_BOARD_CHT204,
  113. CHBT_BOARD_CHT204V,
  114. CHBT_BOARD_CHT204E,
  115. CHBT_BOARD_CHN204,
  116. CHBT_BOARD_COUGAR,
  117. CHBT_BOARD_6800,
  118. CHBT_BOARD_SIMUL,
  119. };
  120. enum {
  121. CHBT_TERM_FPGA,
  122. CHBT_TERM_T1,
  123. CHBT_TERM_T2,
  124. CHBT_TERM_T3
  125. };
  126. enum {
  127. CHBT_MAC_CHELSIO_A,
  128. CHBT_MAC_IXF1010,
  129. CHBT_MAC_PM3393,
  130. CHBT_MAC_VSC7321,
  131. CHBT_MAC_DUMMY
  132. };
  133. enum {
  134. CHBT_PHY_88E1041,
  135. CHBT_PHY_88E1111,
  136. CHBT_PHY_88X2010,
  137. CHBT_PHY_XPAK,
  138. CHBT_PHY_MY3126,
  139. CHBT_PHY_8244,
  140. CHBT_PHY_DUMMY
  141. };
  142. enum {
  143. PAUSE_RX = 1 << 0,
  144. PAUSE_TX = 1 << 1,
  145. PAUSE_AUTONEG = 1 << 2
  146. };
  147. /* Revisions of T1 chip */
  148. enum {
  149. TERM_T1A = 0,
  150. TERM_T1B = 1,
  151. TERM_T2 = 3
  152. };
  153. struct sge_params {
  154. unsigned int cmdQ_size[2];
  155. unsigned int freelQ_size[2];
  156. unsigned int large_buf_capacity;
  157. unsigned int rx_coalesce_usecs;
  158. unsigned int last_rx_coalesce_raw;
  159. unsigned int default_rx_coalesce_usecs;
  160. unsigned int sample_interval_usecs;
  161. unsigned int coalesce_enable;
  162. unsigned int polling;
  163. };
  164. struct chelsio_pci_params {
  165. unsigned short speed;
  166. unsigned char width;
  167. unsigned char is_pcix;
  168. };
  169. struct tp_params {
  170. unsigned int pm_size;
  171. unsigned int cm_size;
  172. unsigned int pm_rx_base;
  173. unsigned int pm_tx_base;
  174. unsigned int pm_rx_pg_size;
  175. unsigned int pm_tx_pg_size;
  176. unsigned int pm_rx_num_pgs;
  177. unsigned int pm_tx_num_pgs;
  178. unsigned int rx_coalescing_size;
  179. unsigned int use_5tuple_mode;
  180. };
  181. struct mc5_params {
  182. unsigned int mode; /* selects MC5 width */
  183. unsigned int nservers; /* size of server region */
  184. unsigned int nroutes; /* size of routing region */
  185. };
  186. /* Default MC5 region sizes */
  187. #define DEFAULT_SERVER_REGION_LEN 256
  188. #define DEFAULT_RT_REGION_LEN 1024
  189. struct adapter_params {
  190. struct sge_params sge;
  191. struct mc5_params mc5;
  192. struct tp_params tp;
  193. struct chelsio_pci_params pci;
  194. const struct board_info *brd_info;
  195. unsigned short mtus[NMTUS];
  196. unsigned int nports; /* # of ethernet ports */
  197. unsigned int stats_update_period;
  198. unsigned short chip_revision;
  199. unsigned char chip_version;
  200. unsigned char is_asic;
  201. unsigned char has_msi;
  202. };
  203. struct link_config {
  204. unsigned int supported; /* link capabilities */
  205. unsigned int advertising; /* advertised capabilities */
  206. unsigned short requested_speed; /* speed user has requested */
  207. unsigned short speed; /* actual link speed */
  208. unsigned char requested_duplex; /* duplex user has requested */
  209. unsigned char duplex; /* actual link duplex */
  210. unsigned char requested_fc; /* flow control user has requested */
  211. unsigned char fc; /* actual link flow control */
  212. unsigned char autoneg; /* autonegotiating? */
  213. };
  214. struct cmac;
  215. struct cphy;
  216. struct port_info {
  217. struct net_device *dev;
  218. struct cmac *mac;
  219. struct cphy *phy;
  220. struct link_config link_config;
  221. struct net_device_stats netstats;
  222. };
  223. struct sge;
  224. struct peespi;
  225. struct adapter {
  226. u8 __iomem *regs;
  227. struct pci_dev *pdev;
  228. unsigned long registered_device_map;
  229. unsigned long open_device_map;
  230. unsigned long flags;
  231. const char *name;
  232. int msg_enable;
  233. u32 mmio_len;
  234. struct work_struct ext_intr_handler_task;
  235. struct adapter_params params;
  236. struct vlan_group *vlan_grp;
  237. /* Terminator modules. */
  238. struct sge *sge;
  239. struct peespi *espi;
  240. struct petp *tp;
  241. struct napi_struct napi;
  242. struct port_info port[MAX_NPORTS];
  243. struct delayed_work stats_update_task;
  244. struct timer_list stats_update_timer;
  245. spinlock_t tpi_lock;
  246. spinlock_t work_lock;
  247. spinlock_t mac_lock;
  248. /* guards async operations */
  249. spinlock_t async_lock ____cacheline_aligned;
  250. u32 slow_intr_mask;
  251. int t1powersave;
  252. };
  253. enum { /* adapter flags */
  254. FULL_INIT_DONE = 1 << 0,
  255. TSO_CAPABLE = 1 << 2,
  256. TCP_CSUM_CAPABLE = 1 << 3,
  257. UDP_CSUM_CAPABLE = 1 << 4,
  258. VLAN_ACCEL_CAPABLE = 1 << 5,
  259. RX_CSUM_ENABLED = 1 << 6,
  260. };
  261. struct mdio_ops;
  262. struct gmac;
  263. struct gphy;
  264. struct board_info {
  265. unsigned char board;
  266. unsigned char port_number;
  267. unsigned long caps;
  268. unsigned char chip_term;
  269. unsigned char chip_mac;
  270. unsigned char chip_phy;
  271. unsigned int clock_core;
  272. unsigned int clock_mc3;
  273. unsigned int clock_mc4;
  274. unsigned int espi_nports;
  275. unsigned int clock_cspi;
  276. unsigned int clock_elmer0;
  277. unsigned char mdio_mdien;
  278. unsigned char mdio_mdiinv;
  279. unsigned char mdio_mdc;
  280. unsigned char mdio_phybaseaddr;
  281. const struct gmac *gmac;
  282. const struct gphy *gphy;
  283. const struct mdio_ops *mdio_ops;
  284. const char *desc;
  285. };
  286. static inline int t1_is_asic(const adapter_t *adapter)
  287. {
  288. return adapter->params.is_asic;
  289. }
  290. extern struct pci_device_id t1_pci_tbl[];
  291. static inline int adapter_matches_type(const adapter_t *adapter,
  292. int version, int revision)
  293. {
  294. return adapter->params.chip_version == version &&
  295. adapter->params.chip_revision == revision;
  296. }
  297. #define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B)
  298. #define is_T2(adap) adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2)
  299. /* Returns true if an adapter supports VLAN acceleration and TSO */
  300. static inline int vlan_tso_capable(const adapter_t *adapter)
  301. {
  302. return !t1_is_T1B(adapter);
  303. }
  304. #define for_each_port(adapter, iter) \
  305. for (iter = 0; iter < (adapter)->params.nports; ++iter)
  306. #define board_info(adapter) ((adapter)->params.brd_info)
  307. #define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full)
  308. static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
  309. {
  310. return board_info(adap)->clock_core / 1000000;
  311. }
  312. extern int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp);
  313. extern int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
  314. extern int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
  315. extern int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value);
  316. extern void t1_interrupts_enable(adapter_t *adapter);
  317. extern void t1_interrupts_disable(adapter_t *adapter);
  318. extern void t1_interrupts_clear(adapter_t *adapter);
  319. extern int t1_elmer0_ext_intr_handler(adapter_t *adapter);
  320. extern void t1_elmer0_ext_intr(adapter_t *adapter);
  321. extern int t1_slow_intr_handler(adapter_t *adapter);
  322. extern int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
  323. extern const struct board_info *t1_get_board_info(unsigned int board_id);
  324. extern const struct board_info *t1_get_board_info_from_ids(unsigned int devid,
  325. unsigned short ssid);
  326. extern int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data);
  327. extern int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
  328. struct adapter_params *p);
  329. extern int t1_init_hw_modules(adapter_t *adapter);
  330. extern int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi);
  331. extern void t1_free_sw_modules(adapter_t *adapter);
  332. extern void t1_fatal_err(adapter_t *adapter);
  333. extern void t1_link_changed(adapter_t *adapter, int port_id);
  334. extern void t1_link_negotiated(adapter_t *adapter, int port_id, int link_stat,
  335. int speed, int duplex, int pause);
  336. #endif /* _CXGB_COMMON_H_ */