em28xx-core.c 28 KB

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  1. /*
  2. em28xx-core.c - driver for Empia EM2800/EM2820/2840 USB video capture devices
  3. Copyright (C) 2005 Ludovico Cavedon <cavedon@sssup.it>
  4. Markus Rechberger <mrechberger@gmail.com>
  5. Mauro Carvalho Chehab <mchehab@infradead.org>
  6. Sascha Sommer <saschasommer@freenet.de>
  7. This program is free software; you can redistribute it and/or modify
  8. it under the terms of the GNU General Public License as published by
  9. the Free Software Foundation; either version 2 of the License, or
  10. (at your option) any later version.
  11. This program is distributed in the hope that it will be useful,
  12. but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program; if not, write to the Free Software
  17. Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. #include <linux/init.h>
  20. #include <linux/list.h>
  21. #include <linux/module.h>
  22. #include <linux/usb.h>
  23. #include <linux/vmalloc.h>
  24. #include <media/v4l2-common.h>
  25. #include "em28xx.h"
  26. /* #define ENABLE_DEBUG_ISOC_FRAMES */
  27. static unsigned int core_debug;
  28. module_param(core_debug, int, 0644);
  29. MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
  30. #define em28xx_coredbg(fmt, arg...) do {\
  31. if (core_debug) \
  32. printk(KERN_INFO "%s %s :"fmt, \
  33. dev->name, __func__ , ##arg); } while (0)
  34. static unsigned int reg_debug;
  35. module_param(reg_debug, int, 0644);
  36. MODULE_PARM_DESC(reg_debug, "enable debug messages [URB reg]");
  37. #define em28xx_regdbg(fmt, arg...) do {\
  38. if (reg_debug) \
  39. printk(KERN_INFO "%s %s :"fmt, \
  40. dev->name, __func__ , ##arg); } while (0)
  41. static int alt = EM28XX_PINOUT;
  42. module_param(alt, int, 0644);
  43. MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
  44. /* FIXME */
  45. #define em28xx_isocdbg(fmt, arg...) do {\
  46. if (core_debug) \
  47. printk(KERN_INFO "%s %s :"fmt, \
  48. dev->name, __func__ , ##arg); } while (0)
  49. /*
  50. * em28xx_read_reg_req()
  51. * reads data from the usb device specifying bRequest
  52. */
  53. int em28xx_read_reg_req_len(struct em28xx *dev, u8 req, u16 reg,
  54. char *buf, int len)
  55. {
  56. int ret;
  57. int pipe = usb_rcvctrlpipe(dev->udev, 0);
  58. if (dev->state & DEV_DISCONNECTED)
  59. return -ENODEV;
  60. if (len > URB_MAX_CTRL_SIZE)
  61. return -EINVAL;
  62. if (reg_debug) {
  63. printk(KERN_DEBUG "(pipe 0x%08x): "
  64. "IN: %02x %02x %02x %02x %02x %02x %02x %02x ",
  65. pipe,
  66. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  67. req, 0, 0,
  68. reg & 0xff, reg >> 8,
  69. len & 0xff, len >> 8);
  70. }
  71. mutex_lock(&dev->ctrl_urb_lock);
  72. ret = usb_control_msg(dev->udev, pipe, req,
  73. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  74. 0x0000, reg, dev->urb_buf, len, HZ);
  75. if (ret < 0) {
  76. if (reg_debug)
  77. printk(" failed!\n");
  78. mutex_unlock(&dev->ctrl_urb_lock);
  79. return ret;
  80. }
  81. if (len)
  82. memcpy(buf, dev->urb_buf, len);
  83. mutex_unlock(&dev->ctrl_urb_lock);
  84. if (reg_debug) {
  85. int byte;
  86. printk("<<<");
  87. for (byte = 0; byte < len; byte++)
  88. printk(" %02x", (unsigned char)buf[byte]);
  89. printk("\n");
  90. }
  91. return ret;
  92. }
  93. /*
  94. * em28xx_read_reg_req()
  95. * reads data from the usb device specifying bRequest
  96. */
  97. int em28xx_read_reg_req(struct em28xx *dev, u8 req, u16 reg)
  98. {
  99. int ret;
  100. u8 val;
  101. ret = em28xx_read_reg_req_len(dev, req, reg, &val, 1);
  102. if (ret < 0)
  103. return ret;
  104. return val;
  105. }
  106. int em28xx_read_reg(struct em28xx *dev, u16 reg)
  107. {
  108. return em28xx_read_reg_req(dev, USB_REQ_GET_STATUS, reg);
  109. }
  110. /*
  111. * em28xx_write_regs_req()
  112. * sends data to the usb device, specifying bRequest
  113. */
  114. int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
  115. int len)
  116. {
  117. int ret;
  118. int pipe = usb_sndctrlpipe(dev->udev, 0);
  119. if (dev->state & DEV_DISCONNECTED)
  120. return -ENODEV;
  121. if ((len < 1) || (len > URB_MAX_CTRL_SIZE))
  122. return -EINVAL;
  123. if (reg_debug) {
  124. int byte;
  125. printk(KERN_DEBUG "(pipe 0x%08x): "
  126. "OUT: %02x %02x %02x %02x %02x %02x %02x %02x >>>",
  127. pipe,
  128. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  129. req, 0, 0,
  130. reg & 0xff, reg >> 8,
  131. len & 0xff, len >> 8);
  132. for (byte = 0; byte < len; byte++)
  133. printk(" %02x", (unsigned char)buf[byte]);
  134. printk("\n");
  135. }
  136. mutex_lock(&dev->ctrl_urb_lock);
  137. memcpy(dev->urb_buf, buf, len);
  138. ret = usb_control_msg(dev->udev, pipe, req,
  139. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  140. 0x0000, reg, dev->urb_buf, len, HZ);
  141. mutex_unlock(&dev->ctrl_urb_lock);
  142. if (dev->wait_after_write)
  143. msleep(dev->wait_after_write);
  144. return ret;
  145. }
  146. int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len)
  147. {
  148. int rc;
  149. rc = em28xx_write_regs_req(dev, USB_REQ_GET_STATUS, reg, buf, len);
  150. /* Stores GPO/GPIO values at the cache, if changed
  151. Only write values should be stored, since input on a GPIO
  152. register will return the input bits.
  153. Not sure what happens on reading GPO register.
  154. */
  155. if (rc >= 0) {
  156. if (reg == dev->reg_gpo_num)
  157. dev->reg_gpo = buf[0];
  158. else if (reg == dev->reg_gpio_num)
  159. dev->reg_gpio = buf[0];
  160. }
  161. return rc;
  162. }
  163. /* Write a single register */
  164. int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
  165. {
  166. return em28xx_write_regs(dev, reg, &val, 1);
  167. }
  168. /*
  169. * em28xx_write_reg_bits()
  170. * sets only some bits (specified by bitmask) of a register, by first reading
  171. * the actual value
  172. */
  173. static int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
  174. u8 bitmask)
  175. {
  176. int oldval;
  177. u8 newval;
  178. /* Uses cache for gpo/gpio registers */
  179. if (reg == dev->reg_gpo_num)
  180. oldval = dev->reg_gpo;
  181. else if (reg == dev->reg_gpio_num)
  182. oldval = dev->reg_gpio;
  183. else
  184. oldval = em28xx_read_reg(dev, reg);
  185. if (oldval < 0)
  186. return oldval;
  187. newval = (((u8) oldval) & ~bitmask) | (val & bitmask);
  188. return em28xx_write_regs(dev, reg, &newval, 1);
  189. }
  190. /*
  191. * em28xx_is_ac97_ready()
  192. * Checks if ac97 is ready
  193. */
  194. static int em28xx_is_ac97_ready(struct em28xx *dev)
  195. {
  196. int ret, i;
  197. /* Wait up to 50 ms for AC97 command to complete */
  198. for (i = 0; i < 10; i++, msleep(5)) {
  199. ret = em28xx_read_reg(dev, EM28XX_R43_AC97BUSY);
  200. if (ret < 0)
  201. return ret;
  202. if (!(ret & 0x01))
  203. return 0;
  204. }
  205. em28xx_warn("AC97 command still being executed: not handled properly!\n");
  206. return -EBUSY;
  207. }
  208. /*
  209. * em28xx_read_ac97()
  210. * write a 16 bit value to the specified AC97 address (LSB first!)
  211. */
  212. int em28xx_read_ac97(struct em28xx *dev, u8 reg)
  213. {
  214. int ret;
  215. u8 addr = (reg & 0x7f) | 0x80;
  216. u16 val;
  217. ret = em28xx_is_ac97_ready(dev);
  218. if (ret < 0)
  219. return ret;
  220. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  221. if (ret < 0)
  222. return ret;
  223. ret = dev->em28xx_read_reg_req_len(dev, 0, EM28XX_R40_AC97LSB,
  224. (u8 *)&val, sizeof(val));
  225. if (ret < 0)
  226. return ret;
  227. return le16_to_cpu(val);
  228. }
  229. /*
  230. * em28xx_write_ac97()
  231. * write a 16 bit value to the specified AC97 address (LSB first!)
  232. */
  233. int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val)
  234. {
  235. int ret;
  236. u8 addr = reg & 0x7f;
  237. __le16 value;
  238. value = cpu_to_le16(val);
  239. ret = em28xx_is_ac97_ready(dev);
  240. if (ret < 0)
  241. return ret;
  242. ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *) &value, 2);
  243. if (ret < 0)
  244. return ret;
  245. ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
  246. if (ret < 0)
  247. return ret;
  248. return 0;
  249. }
  250. struct em28xx_vol_table {
  251. enum em28xx_amux mux;
  252. u8 reg;
  253. };
  254. static struct em28xx_vol_table inputs[] = {
  255. { EM28XX_AMUX_VIDEO, AC97_VIDEO_VOL },
  256. { EM28XX_AMUX_LINE_IN, AC97_LINEIN_VOL },
  257. { EM28XX_AMUX_PHONE, AC97_PHONE_VOL },
  258. { EM28XX_AMUX_MIC, AC97_MIC_VOL },
  259. { EM28XX_AMUX_CD, AC97_CD_VOL },
  260. { EM28XX_AMUX_AUX, AC97_AUX_VOL },
  261. { EM28XX_AMUX_PCM_OUT, AC97_PCM_OUT_VOL },
  262. };
  263. static int set_ac97_input(struct em28xx *dev)
  264. {
  265. int ret, i;
  266. enum em28xx_amux amux = dev->ctl_ainput;
  267. /* EM28XX_AMUX_VIDEO2 is a special case used to indicate that
  268. em28xx should point to LINE IN, while AC97 should use VIDEO
  269. */
  270. if (amux == EM28XX_AMUX_VIDEO2)
  271. amux = EM28XX_AMUX_VIDEO;
  272. /* Mute all entres but the one that were selected */
  273. for (i = 0; i < ARRAY_SIZE(inputs); i++) {
  274. if (amux == inputs[i].mux)
  275. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x0808);
  276. else
  277. ret = em28xx_write_ac97(dev, inputs[i].reg, 0x8000);
  278. if (ret < 0)
  279. em28xx_warn("couldn't setup AC97 register %d\n",
  280. inputs[i].reg);
  281. }
  282. return 0;
  283. }
  284. static int em28xx_set_audio_source(struct em28xx *dev)
  285. {
  286. int ret;
  287. u8 input;
  288. if (dev->board.is_em2800) {
  289. if (dev->ctl_ainput == EM28XX_AMUX_VIDEO)
  290. input = EM2800_AUDIO_SRC_TUNER;
  291. else
  292. input = EM2800_AUDIO_SRC_LINE;
  293. ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
  294. if (ret < 0)
  295. return ret;
  296. }
  297. if (dev->board.has_msp34xx)
  298. input = EM28XX_AUDIO_SRC_TUNER;
  299. else {
  300. switch (dev->ctl_ainput) {
  301. case EM28XX_AMUX_VIDEO:
  302. input = EM28XX_AUDIO_SRC_TUNER;
  303. break;
  304. default:
  305. input = EM28XX_AUDIO_SRC_LINE;
  306. break;
  307. }
  308. }
  309. if (dev->board.mute_gpio && dev->mute)
  310. em28xx_gpio_set(dev, dev->board.mute_gpio);
  311. else
  312. em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
  313. ret = em28xx_write_reg_bits(dev, EM28XX_R0E_AUDIOSRC, input, 0xc0);
  314. if (ret < 0)
  315. return ret;
  316. msleep(5);
  317. switch (dev->audio_mode.ac97) {
  318. case EM28XX_NO_AC97:
  319. break;
  320. default:
  321. ret = set_ac97_input(dev);
  322. }
  323. return ret;
  324. }
  325. static const struct em28xx_vol_table outputs[] = {
  326. { EM28XX_AOUT_MASTER, AC97_MASTER_VOL },
  327. { EM28XX_AOUT_LINE, AC97_LINE_LEVEL_VOL },
  328. { EM28XX_AOUT_MONO, AC97_MASTER_MONO_VOL },
  329. { EM28XX_AOUT_LFE, AC97_LFE_MASTER_VOL },
  330. { EM28XX_AOUT_SURR, AC97_SURR_MASTER_VOL },
  331. };
  332. int em28xx_audio_analog_set(struct em28xx *dev)
  333. {
  334. int ret, i;
  335. u8 xclk;
  336. if (!dev->audio_mode.has_audio)
  337. return 0;
  338. /* It is assumed that all devices use master volume for output.
  339. It would be possible to use also line output.
  340. */
  341. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  342. /* Mute all outputs */
  343. for (i = 0; i < ARRAY_SIZE(outputs); i++) {
  344. ret = em28xx_write_ac97(dev, outputs[i].reg, 0x8000);
  345. if (ret < 0)
  346. em28xx_warn("couldn't setup AC97 register %d\n",
  347. outputs[i].reg);
  348. }
  349. }
  350. xclk = dev->board.xclk & 0x7f;
  351. if (!dev->mute)
  352. xclk |= EM28XX_XCLK_AUDIO_UNMUTE;
  353. ret = em28xx_write_reg(dev, EM28XX_R0F_XCLK, xclk);
  354. if (ret < 0)
  355. return ret;
  356. msleep(10);
  357. /* Selects the proper audio input */
  358. ret = em28xx_set_audio_source(dev);
  359. /* Sets volume */
  360. if (dev->audio_mode.ac97 != EM28XX_NO_AC97) {
  361. int vol;
  362. em28xx_write_ac97(dev, AC97_POWER_DOWN_CTRL, 0x4200);
  363. em28xx_write_ac97(dev, AC97_EXT_AUD_CTRL, 0x0031);
  364. em28xx_write_ac97(dev, AC97_PCM_IN_SRATE, 0xbb80);
  365. /* LSB: left channel - both channels with the same level */
  366. vol = (0x1f - dev->volume) | ((0x1f - dev->volume) << 8);
  367. /* Mute device, if needed */
  368. if (dev->mute)
  369. vol |= 0x8000;
  370. /* Sets volume */
  371. for (i = 0; i < ARRAY_SIZE(outputs); i++) {
  372. if (dev->ctl_aoutput & outputs[i].mux)
  373. ret = em28xx_write_ac97(dev, outputs[i].reg,
  374. vol);
  375. if (ret < 0)
  376. em28xx_warn("couldn't setup AC97 register %d\n",
  377. outputs[i].reg);
  378. }
  379. if (dev->ctl_aoutput & EM28XX_AOUT_PCM_IN) {
  380. int sel = ac97_return_record_select(dev->ctl_aoutput);
  381. /* Use the same input for both left and right
  382. channels */
  383. sel |= (sel << 8);
  384. em28xx_write_ac97(dev, AC97_RECORD_SELECT, sel);
  385. }
  386. }
  387. return ret;
  388. }
  389. EXPORT_SYMBOL_GPL(em28xx_audio_analog_set);
  390. int em28xx_audio_setup(struct em28xx *dev)
  391. {
  392. int vid1, vid2, feat, cfg;
  393. u32 vid;
  394. if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874) {
  395. /* Digital only device - don't load any alsa module */
  396. dev->audio_mode.has_audio = 0;
  397. dev->has_audio_class = 0;
  398. dev->has_alsa_audio = 0;
  399. return 0;
  400. }
  401. /* If device doesn't support Usb Audio Class, use vendor class */
  402. if (!dev->has_audio_class)
  403. dev->has_alsa_audio = 1;
  404. dev->audio_mode.has_audio = 1;
  405. /* See how this device is configured */
  406. cfg = em28xx_read_reg(dev, EM28XX_R00_CHIPCFG);
  407. if (cfg < 0)
  408. cfg = EM28XX_CHIPCFG_AC97; /* Be conservative */
  409. else
  410. em28xx_info("Config register raw data: 0x%02x\n", cfg);
  411. if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  412. EM28XX_CHIPCFG_I2S_3_SAMPRATES) {
  413. em28xx_info("I2S Audio (3 sample rates)\n");
  414. dev->audio_mode.i2s_3rates = 1;
  415. }
  416. if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) ==
  417. EM28XX_CHIPCFG_I2S_5_SAMPRATES) {
  418. em28xx_info("I2S Audio (5 sample rates)\n");
  419. dev->audio_mode.i2s_5rates = 1;
  420. }
  421. if ((cfg & EM28XX_CHIPCFG_AUDIOMASK) != EM28XX_CHIPCFG_AC97) {
  422. /* Skip the code that does AC97 vendor detection */
  423. dev->audio_mode.ac97 = EM28XX_NO_AC97;
  424. goto init_audio;
  425. }
  426. dev->audio_mode.ac97 = EM28XX_AC97_OTHER;
  427. vid1 = em28xx_read_ac97(dev, AC97_VENDOR_ID1);
  428. if (vid1 < 0) {
  429. /* Device likely doesn't support AC97 */
  430. em28xx_warn("AC97 chip type couldn't be determined\n");
  431. goto init_audio;
  432. }
  433. vid2 = em28xx_read_ac97(dev, AC97_VENDOR_ID2);
  434. if (vid2 < 0)
  435. goto init_audio;
  436. vid = vid1 << 16 | vid2;
  437. dev->audio_mode.ac97_vendor_id = vid;
  438. em28xx_warn("AC97 vendor ID = 0x%08x\n", vid);
  439. feat = em28xx_read_ac97(dev, AC97_RESET);
  440. if (feat < 0)
  441. goto init_audio;
  442. dev->audio_mode.ac97_feat = feat;
  443. em28xx_warn("AC97 features = 0x%04x\n", feat);
  444. /* Try to identify what audio processor we have */
  445. if ((vid == 0xffffffff) && (feat == 0x6a90))
  446. dev->audio_mode.ac97 = EM28XX_AC97_EM202;
  447. else if ((vid >> 8) == 0x838476)
  448. dev->audio_mode.ac97 = EM28XX_AC97_SIGMATEL;
  449. init_audio:
  450. /* Reports detected AC97 processor */
  451. switch (dev->audio_mode.ac97) {
  452. case EM28XX_NO_AC97:
  453. em28xx_info("No AC97 audio processor\n");
  454. break;
  455. case EM28XX_AC97_EM202:
  456. em28xx_info("Empia 202 AC97 audio processor detected\n");
  457. break;
  458. case EM28XX_AC97_SIGMATEL:
  459. em28xx_info("Sigmatel audio processor detected(stac 97%02x)\n",
  460. dev->audio_mode.ac97_vendor_id & 0xff);
  461. break;
  462. case EM28XX_AC97_OTHER:
  463. em28xx_warn("Unknown AC97 audio processor detected!\n");
  464. break;
  465. default:
  466. break;
  467. }
  468. return em28xx_audio_analog_set(dev);
  469. }
  470. EXPORT_SYMBOL_GPL(em28xx_audio_setup);
  471. int em28xx_colorlevels_set_default(struct em28xx *dev)
  472. {
  473. em28xx_write_reg(dev, EM28XX_R20_YGAIN, 0x10); /* contrast */
  474. em28xx_write_reg(dev, EM28XX_R21_YOFFSET, 0x00); /* brightness */
  475. em28xx_write_reg(dev, EM28XX_R22_UVGAIN, 0x10); /* saturation */
  476. em28xx_write_reg(dev, EM28XX_R23_UOFFSET, 0x00);
  477. em28xx_write_reg(dev, EM28XX_R24_VOFFSET, 0x00);
  478. em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, 0x00);
  479. em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
  480. em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
  481. em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
  482. em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
  483. em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
  484. em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
  485. return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
  486. }
  487. int em28xx_capture_start(struct em28xx *dev, int start)
  488. {
  489. int rc;
  490. if (dev->chip_id == CHIP_ID_EM2874) {
  491. /* The Transport Stream Enable Register moved in em2874 */
  492. if (!start) {
  493. rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
  494. 0x00,
  495. EM2874_TS1_CAPTURE_ENABLE);
  496. return rc;
  497. }
  498. /* Enable Transport Stream */
  499. rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
  500. EM2874_TS1_CAPTURE_ENABLE,
  501. EM2874_TS1_CAPTURE_ENABLE);
  502. return rc;
  503. }
  504. /* FIXME: which is the best order? */
  505. /* video registers are sampled by VREF */
  506. rc = em28xx_write_reg_bits(dev, EM28XX_R0C_USBSUSP,
  507. start ? 0x10 : 0x00, 0x10);
  508. if (rc < 0)
  509. return rc;
  510. if (!start) {
  511. /* disable video capture */
  512. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x27);
  513. return rc;
  514. }
  515. /* enable video capture */
  516. rc = em28xx_write_reg(dev, 0x48, 0x00);
  517. if (dev->mode == EM28XX_ANALOG_MODE)
  518. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
  519. else
  520. rc = em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
  521. msleep(6);
  522. return rc;
  523. }
  524. int em28xx_set_outfmt(struct em28xx *dev)
  525. {
  526. int ret;
  527. ret = em28xx_write_reg_bits(dev, EM28XX_R27_OUTFMT,
  528. dev->format->reg | 0x20, 0x3f);
  529. if (ret < 0)
  530. return ret;
  531. ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, 0x10);
  532. if (ret < 0)
  533. return ret;
  534. return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, 0x11);
  535. }
  536. static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
  537. u8 ymin, u8 ymax)
  538. {
  539. em28xx_coredbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
  540. xmin, ymin, xmax, ymax);
  541. em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
  542. em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
  543. em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
  544. return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
  545. }
  546. static int em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
  547. u16 width, u16 height)
  548. {
  549. u8 cwidth = width;
  550. u8 cheight = height;
  551. u8 overflow = (height >> 7 & 0x02) | (width >> 8 & 0x01);
  552. em28xx_coredbg("em28xx Area Set: (%d,%d)\n",
  553. (width | (overflow & 2) << 7),
  554. (height | (overflow & 1) << 8));
  555. em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
  556. em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
  557. em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
  558. em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
  559. return em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
  560. }
  561. static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
  562. {
  563. u8 mode;
  564. /* the em2800 scaler only supports scaling down to 50% */
  565. if (dev->board.is_em2800)
  566. mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
  567. else {
  568. u8 buf[2];
  569. buf[0] = h;
  570. buf[1] = h >> 8;
  571. em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
  572. buf[0] = v;
  573. buf[1] = v >> 8;
  574. em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
  575. /* it seems that both H and V scalers must be active
  576. to work correctly */
  577. mode = (h || v) ? 0x30 : 0x00;
  578. }
  579. return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
  580. }
  581. /* FIXME: this only function read values from dev */
  582. int em28xx_resolution_set(struct em28xx *dev)
  583. {
  584. int width, height;
  585. width = norm_maxw(dev);
  586. height = norm_maxh(dev) >> 1;
  587. em28xx_set_outfmt(dev);
  588. em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
  589. em28xx_capture_area_set(dev, 0, 0, width >> 2, height >> 2);
  590. return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
  591. }
  592. int em28xx_set_alternate(struct em28xx *dev)
  593. {
  594. int errCode, prev_alt = dev->alt;
  595. int i;
  596. unsigned int min_pkt_size = dev->width * 2 + 4;
  597. /* When image size is bigger than a certain value,
  598. the frame size should be increased, otherwise, only
  599. green screen will be received.
  600. */
  601. if (dev->width * 2 * dev->height > 720 * 240 * 2)
  602. min_pkt_size *= 2;
  603. for (i = 0; i < dev->num_alt; i++) {
  604. /* stop when the selected alt setting offers enough bandwidth */
  605. if (dev->alt_max_pkt_size[i] >= min_pkt_size) {
  606. dev->alt = i;
  607. break;
  608. /* otherwise make sure that we end up with the maximum bandwidth
  609. because the min_pkt_size equation might be wrong...
  610. */
  611. } else if (dev->alt_max_pkt_size[i] >
  612. dev->alt_max_pkt_size[dev->alt])
  613. dev->alt = i;
  614. }
  615. if (dev->alt != prev_alt) {
  616. em28xx_coredbg("minimum isoc packet size: %u (alt=%d)\n",
  617. min_pkt_size, dev->alt);
  618. dev->max_pkt_size = dev->alt_max_pkt_size[dev->alt];
  619. em28xx_coredbg("setting alternate %d with wMaxPacketSize=%u\n",
  620. dev->alt, dev->max_pkt_size);
  621. errCode = usb_set_interface(dev->udev, 0, dev->alt);
  622. if (errCode < 0) {
  623. em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
  624. dev->alt, errCode);
  625. return errCode;
  626. }
  627. }
  628. return 0;
  629. }
  630. int em28xx_gpio_set(struct em28xx *dev, struct em28xx_reg_seq *gpio)
  631. {
  632. int rc = 0;
  633. if (!gpio)
  634. return rc;
  635. if (dev->mode != EM28XX_SUSPEND) {
  636. em28xx_write_reg(dev, 0x48, 0x00);
  637. if (dev->mode == EM28XX_ANALOG_MODE)
  638. em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x67);
  639. else
  640. em28xx_write_reg(dev, EM28XX_R12_VINENABLE, 0x37);
  641. msleep(6);
  642. }
  643. /* Send GPIO reset sequences specified at board entry */
  644. while (gpio->sleep >= 0) {
  645. if (gpio->reg >= 0) {
  646. rc = em28xx_write_reg_bits(dev,
  647. gpio->reg,
  648. gpio->val,
  649. gpio->mask);
  650. if (rc < 0)
  651. return rc;
  652. }
  653. if (gpio->sleep > 0)
  654. msleep(gpio->sleep);
  655. gpio++;
  656. }
  657. return rc;
  658. }
  659. int em28xx_set_mode(struct em28xx *dev, enum em28xx_mode set_mode)
  660. {
  661. if (dev->mode == set_mode)
  662. return 0;
  663. if (set_mode == EM28XX_SUSPEND) {
  664. dev->mode = set_mode;
  665. /* FIXME: add suspend support for ac97 */
  666. return em28xx_gpio_set(dev, dev->board.suspend_gpio);
  667. }
  668. dev->mode = set_mode;
  669. if (dev->mode == EM28XX_DIGITAL_MODE)
  670. return em28xx_gpio_set(dev, dev->board.dvb_gpio);
  671. else
  672. return em28xx_gpio_set(dev, INPUT(dev->ctl_input)->gpio);
  673. }
  674. EXPORT_SYMBOL_GPL(em28xx_set_mode);
  675. /* ------------------------------------------------------------------
  676. URB control
  677. ------------------------------------------------------------------*/
  678. /*
  679. * IRQ callback, called by URB callback
  680. */
  681. static void em28xx_irq_callback(struct urb *urb)
  682. {
  683. struct em28xx_dmaqueue *dma_q = urb->context;
  684. struct em28xx *dev = container_of(dma_q, struct em28xx, vidq);
  685. int rc, i;
  686. switch (urb->status) {
  687. case 0: /* success */
  688. case -ETIMEDOUT: /* NAK */
  689. break;
  690. case -ECONNRESET: /* kill */
  691. case -ENOENT:
  692. case -ESHUTDOWN:
  693. return;
  694. default: /* error */
  695. em28xx_isocdbg("urb completition error %d.\n", urb->status);
  696. break;
  697. }
  698. /* Copy data from URB */
  699. spin_lock(&dev->slock);
  700. rc = dev->isoc_ctl.isoc_copy(dev, urb);
  701. spin_unlock(&dev->slock);
  702. /* Reset urb buffers */
  703. for (i = 0; i < urb->number_of_packets; i++) {
  704. urb->iso_frame_desc[i].status = 0;
  705. urb->iso_frame_desc[i].actual_length = 0;
  706. }
  707. urb->status = 0;
  708. urb->status = usb_submit_urb(urb, GFP_ATOMIC);
  709. if (urb->status) {
  710. em28xx_isocdbg("urb resubmit failed (error=%i)\n",
  711. urb->status);
  712. }
  713. }
  714. /*
  715. * Stop and Deallocate URBs
  716. */
  717. void em28xx_uninit_isoc(struct em28xx *dev)
  718. {
  719. struct urb *urb;
  720. int i;
  721. em28xx_isocdbg("em28xx: called em28xx_uninit_isoc\n");
  722. dev->isoc_ctl.nfields = -1;
  723. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  724. urb = dev->isoc_ctl.urb[i];
  725. if (urb) {
  726. if (!irqs_disabled())
  727. usb_kill_urb(urb);
  728. else
  729. usb_unlink_urb(urb);
  730. if (dev->isoc_ctl.transfer_buffer[i]) {
  731. usb_buffer_free(dev->udev,
  732. urb->transfer_buffer_length,
  733. dev->isoc_ctl.transfer_buffer[i],
  734. urb->transfer_dma);
  735. }
  736. usb_free_urb(urb);
  737. dev->isoc_ctl.urb[i] = NULL;
  738. }
  739. dev->isoc_ctl.transfer_buffer[i] = NULL;
  740. }
  741. kfree(dev->isoc_ctl.urb);
  742. kfree(dev->isoc_ctl.transfer_buffer);
  743. dev->isoc_ctl.urb = NULL;
  744. dev->isoc_ctl.transfer_buffer = NULL;
  745. dev->isoc_ctl.num_bufs = 0;
  746. em28xx_capture_start(dev, 0);
  747. }
  748. EXPORT_SYMBOL_GPL(em28xx_uninit_isoc);
  749. /*
  750. * Allocate URBs and start IRQ
  751. */
  752. int em28xx_init_isoc(struct em28xx *dev, int max_packets,
  753. int num_bufs, int max_pkt_size,
  754. int (*isoc_copy) (struct em28xx *dev, struct urb *urb))
  755. {
  756. struct em28xx_dmaqueue *dma_q = &dev->vidq;
  757. int i;
  758. int sb_size, pipe;
  759. struct urb *urb;
  760. int j, k;
  761. int rc;
  762. em28xx_isocdbg("em28xx: called em28xx_prepare_isoc\n");
  763. /* De-allocates all pending stuff */
  764. em28xx_uninit_isoc(dev);
  765. dev->isoc_ctl.isoc_copy = isoc_copy;
  766. dev->isoc_ctl.num_bufs = num_bufs;
  767. dev->isoc_ctl.urb = kzalloc(sizeof(void *)*num_bufs, GFP_KERNEL);
  768. if (!dev->isoc_ctl.urb) {
  769. em28xx_errdev("cannot alloc memory for usb buffers\n");
  770. return -ENOMEM;
  771. }
  772. dev->isoc_ctl.transfer_buffer = kzalloc(sizeof(void *)*num_bufs,
  773. GFP_KERNEL);
  774. if (!dev->isoc_ctl.transfer_buffer) {
  775. em28xx_errdev("cannot allocate memory for usbtransfer\n");
  776. kfree(dev->isoc_ctl.urb);
  777. return -ENOMEM;
  778. }
  779. dev->isoc_ctl.max_pkt_size = max_pkt_size;
  780. dev->isoc_ctl.buf = NULL;
  781. sb_size = max_packets * dev->isoc_ctl.max_pkt_size;
  782. /* allocate urbs and transfer buffers */
  783. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  784. urb = usb_alloc_urb(max_packets, GFP_KERNEL);
  785. if (!urb) {
  786. em28xx_err("cannot alloc isoc_ctl.urb %i\n", i);
  787. em28xx_uninit_isoc(dev);
  788. return -ENOMEM;
  789. }
  790. dev->isoc_ctl.urb[i] = urb;
  791. dev->isoc_ctl.transfer_buffer[i] = usb_buffer_alloc(dev->udev,
  792. sb_size, GFP_KERNEL, &urb->transfer_dma);
  793. if (!dev->isoc_ctl.transfer_buffer[i]) {
  794. em28xx_err("unable to allocate %i bytes for transfer"
  795. " buffer %i%s\n",
  796. sb_size, i,
  797. in_interrupt() ? " while in int" : "");
  798. em28xx_uninit_isoc(dev);
  799. return -ENOMEM;
  800. }
  801. memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size);
  802. /* FIXME: this is a hack - should be
  803. 'desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK'
  804. should also be using 'desc.bInterval'
  805. */
  806. pipe = usb_rcvisocpipe(dev->udev,
  807. dev->mode == EM28XX_ANALOG_MODE ? 0x82 : 0x84);
  808. usb_fill_int_urb(urb, dev->udev, pipe,
  809. dev->isoc_ctl.transfer_buffer[i], sb_size,
  810. em28xx_irq_callback, dma_q, 1);
  811. urb->number_of_packets = max_packets;
  812. urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
  813. k = 0;
  814. for (j = 0; j < max_packets; j++) {
  815. urb->iso_frame_desc[j].offset = k;
  816. urb->iso_frame_desc[j].length =
  817. dev->isoc_ctl.max_pkt_size;
  818. k += dev->isoc_ctl.max_pkt_size;
  819. }
  820. }
  821. init_waitqueue_head(&dma_q->wq);
  822. em28xx_capture_start(dev, 1);
  823. /* submit urbs and enables IRQ */
  824. for (i = 0; i < dev->isoc_ctl.num_bufs; i++) {
  825. rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_ATOMIC);
  826. if (rc) {
  827. em28xx_err("submit of urb %i failed (error=%i)\n", i,
  828. rc);
  829. em28xx_uninit_isoc(dev);
  830. return rc;
  831. }
  832. }
  833. return 0;
  834. }
  835. EXPORT_SYMBOL_GPL(em28xx_init_isoc);
  836. /*
  837. * em28xx_wake_i2c()
  838. * configure i2c attached devices
  839. */
  840. void em28xx_wake_i2c(struct em28xx *dev)
  841. {
  842. v4l2_device_call_all(&dev->v4l2_dev, 0, core, reset, 0);
  843. v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_routing,
  844. INPUT(dev->ctl_input)->vmux, 0, 0);
  845. v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_stream, 0);
  846. }
  847. /*
  848. * Device control list
  849. */
  850. static LIST_HEAD(em28xx_devlist);
  851. static DEFINE_MUTEX(em28xx_devlist_mutex);
  852. struct em28xx *em28xx_get_device(int minor,
  853. enum v4l2_buf_type *fh_type,
  854. int *has_radio)
  855. {
  856. struct em28xx *h, *dev = NULL;
  857. *fh_type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  858. *has_radio = 0;
  859. mutex_lock(&em28xx_devlist_mutex);
  860. list_for_each_entry(h, &em28xx_devlist, devlist) {
  861. if (h->vdev->minor == minor)
  862. dev = h;
  863. if (h->vbi_dev->minor == minor) {
  864. dev = h;
  865. *fh_type = V4L2_BUF_TYPE_VBI_CAPTURE;
  866. }
  867. if (h->radio_dev &&
  868. h->radio_dev->minor == minor) {
  869. dev = h;
  870. *has_radio = 1;
  871. }
  872. }
  873. mutex_unlock(&em28xx_devlist_mutex);
  874. return dev;
  875. }
  876. /*
  877. * em28xx_realease_resources()
  878. * unregisters the v4l2,i2c and usb devices
  879. * called when the device gets disconected or at module unload
  880. */
  881. void em28xx_remove_from_devlist(struct em28xx *dev)
  882. {
  883. mutex_lock(&em28xx_devlist_mutex);
  884. list_del(&dev->devlist);
  885. mutex_unlock(&em28xx_devlist_mutex);
  886. };
  887. void em28xx_add_into_devlist(struct em28xx *dev)
  888. {
  889. mutex_lock(&em28xx_devlist_mutex);
  890. list_add_tail(&dev->devlist, &em28xx_devlist);
  891. mutex_unlock(&em28xx_devlist_mutex);
  892. };
  893. /*
  894. * Extension interface
  895. */
  896. static LIST_HEAD(em28xx_extension_devlist);
  897. static DEFINE_MUTEX(em28xx_extension_devlist_lock);
  898. int em28xx_register_extension(struct em28xx_ops *ops)
  899. {
  900. struct em28xx *dev = NULL;
  901. mutex_lock(&em28xx_devlist_mutex);
  902. mutex_lock(&em28xx_extension_devlist_lock);
  903. list_add_tail(&ops->next, &em28xx_extension_devlist);
  904. list_for_each_entry(dev, &em28xx_devlist, devlist) {
  905. if (dev)
  906. ops->init(dev);
  907. }
  908. printk(KERN_INFO "Em28xx: Initialized (%s) extension\n", ops->name);
  909. mutex_unlock(&em28xx_extension_devlist_lock);
  910. mutex_unlock(&em28xx_devlist_mutex);
  911. return 0;
  912. }
  913. EXPORT_SYMBOL(em28xx_register_extension);
  914. void em28xx_unregister_extension(struct em28xx_ops *ops)
  915. {
  916. struct em28xx *dev = NULL;
  917. mutex_lock(&em28xx_devlist_mutex);
  918. list_for_each_entry(dev, &em28xx_devlist, devlist) {
  919. if (dev)
  920. ops->fini(dev);
  921. }
  922. mutex_lock(&em28xx_extension_devlist_lock);
  923. printk(KERN_INFO "Em28xx: Removed (%s) extension\n", ops->name);
  924. list_del(&ops->next);
  925. mutex_unlock(&em28xx_extension_devlist_lock);
  926. mutex_unlock(&em28xx_devlist_mutex);
  927. }
  928. EXPORT_SYMBOL(em28xx_unregister_extension);
  929. void em28xx_init_extension(struct em28xx *dev)
  930. {
  931. struct em28xx_ops *ops = NULL;
  932. mutex_lock(&em28xx_extension_devlist_lock);
  933. if (!list_empty(&em28xx_extension_devlist)) {
  934. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  935. if (ops->init)
  936. ops->init(dev);
  937. }
  938. }
  939. mutex_unlock(&em28xx_extension_devlist_lock);
  940. }
  941. void em28xx_close_extension(struct em28xx *dev)
  942. {
  943. struct em28xx_ops *ops = NULL;
  944. mutex_lock(&em28xx_extension_devlist_lock);
  945. if (!list_empty(&em28xx_extension_devlist)) {
  946. list_for_each_entry(ops, &em28xx_extension_devlist, next) {
  947. if (ops->fini)
  948. ops->fini(dev);
  949. }
  950. }
  951. mutex_unlock(&em28xx_extension_devlist_lock);
  952. }