lis3lv02d.h 4.9 KB

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  1. /*
  2. * lis3lv02d.h - ST LIS3LV02DL accelerometer driver
  3. *
  4. * Copyright (C) 2007-2008 Yan Burman
  5. * Copyright (C) 2008 Eric Piel
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. /*
  22. * The actual chip is STMicroelectronics LIS3LV02DL or LIS3LV02DQ that seems to
  23. * be connected via SPI. There exists also several similar chips (such as LIS302DL or
  24. * LIS3L02DQ) and they have slightly different registers, but we can provide a
  25. * common interface for all of them.
  26. * They can also be connected via I²C.
  27. */
  28. /* 2-byte registers */
  29. #define LIS_DOUBLE_ID 0x3A /* LIS3LV02D[LQ] */
  30. /* 1-byte registers */
  31. #define LIS_SINGLE_ID 0x3B /* LIS[32]02DL and others */
  32. enum lis3lv02d_reg {
  33. WHO_AM_I = 0x0F,
  34. OFFSET_X = 0x16,
  35. OFFSET_Y = 0x17,
  36. OFFSET_Z = 0x18,
  37. GAIN_X = 0x19,
  38. GAIN_Y = 0x1A,
  39. GAIN_Z = 0x1B,
  40. CTRL_REG1 = 0x20,
  41. CTRL_REG2 = 0x21,
  42. CTRL_REG3 = 0x22,
  43. HP_FILTER_RESET = 0x23,
  44. STATUS_REG = 0x27,
  45. OUTX_L = 0x28,
  46. OUTX_H = 0x29,
  47. OUTX = 0x29,
  48. OUTY_L = 0x2A,
  49. OUTY_H = 0x2B,
  50. OUTY = 0x2B,
  51. OUTZ_L = 0x2C,
  52. OUTZ_H = 0x2D,
  53. OUTZ = 0x2D,
  54. FF_WU_CFG = 0x30,
  55. FF_WU_SRC = 0x31,
  56. FF_WU_ACK = 0x32,
  57. FF_WU_THS_L = 0x34,
  58. FF_WU_THS_H = 0x35,
  59. FF_WU_DURATION = 0x36,
  60. DD_CFG = 0x38,
  61. DD_SRC = 0x39,
  62. DD_ACK = 0x3A,
  63. DD_THSI_L = 0x3C,
  64. DD_THSI_H = 0x3D,
  65. DD_THSE_L = 0x3E,
  66. DD_THSE_H = 0x3F,
  67. };
  68. enum lis3lv02d_ctrl1 {
  69. CTRL1_Xen = 0x01,
  70. CTRL1_Yen = 0x02,
  71. CTRL1_Zen = 0x04,
  72. CTRL1_ST = 0x08,
  73. CTRL1_DF0 = 0x10,
  74. CTRL1_DF1 = 0x20,
  75. CTRL1_PD0 = 0x40,
  76. CTRL1_PD1 = 0x80,
  77. };
  78. enum lis3lv02d_ctrl2 {
  79. CTRL2_DAS = 0x01,
  80. CTRL2_SIM = 0x02,
  81. CTRL2_DRDY = 0x04,
  82. CTRL2_IEN = 0x08,
  83. CTRL2_BOOT = 0x10,
  84. CTRL2_BLE = 0x20,
  85. CTRL2_BDU = 0x40, /* Block Data Update */
  86. CTRL2_FS = 0x80, /* Full Scale selection */
  87. };
  88. enum lis3lv02d_ctrl3 {
  89. CTRL3_CFS0 = 0x01,
  90. CTRL3_CFS1 = 0x02,
  91. CTRL3_FDS = 0x10,
  92. CTRL3_HPFF = 0x20,
  93. CTRL3_HPDD = 0x40,
  94. CTRL3_ECK = 0x80,
  95. };
  96. enum lis3lv02d_status_reg {
  97. STATUS_XDA = 0x01,
  98. STATUS_YDA = 0x02,
  99. STATUS_ZDA = 0x04,
  100. STATUS_XYZDA = 0x08,
  101. STATUS_XOR = 0x10,
  102. STATUS_YOR = 0x20,
  103. STATUS_ZOR = 0x40,
  104. STATUS_XYZOR = 0x80,
  105. };
  106. enum lis3lv02d_ff_wu_cfg {
  107. FF_WU_CFG_XLIE = 0x01,
  108. FF_WU_CFG_XHIE = 0x02,
  109. FF_WU_CFG_YLIE = 0x04,
  110. FF_WU_CFG_YHIE = 0x08,
  111. FF_WU_CFG_ZLIE = 0x10,
  112. FF_WU_CFG_ZHIE = 0x20,
  113. FF_WU_CFG_LIR = 0x40,
  114. FF_WU_CFG_AOI = 0x80,
  115. };
  116. enum lis3lv02d_ff_wu_src {
  117. FF_WU_SRC_XL = 0x01,
  118. FF_WU_SRC_XH = 0x02,
  119. FF_WU_SRC_YL = 0x04,
  120. FF_WU_SRC_YH = 0x08,
  121. FF_WU_SRC_ZL = 0x10,
  122. FF_WU_SRC_ZH = 0x20,
  123. FF_WU_SRC_IA = 0x40,
  124. };
  125. enum lis3lv02d_dd_cfg {
  126. DD_CFG_XLIE = 0x01,
  127. DD_CFG_XHIE = 0x02,
  128. DD_CFG_YLIE = 0x04,
  129. DD_CFG_YHIE = 0x08,
  130. DD_CFG_ZLIE = 0x10,
  131. DD_CFG_ZHIE = 0x20,
  132. DD_CFG_LIR = 0x40,
  133. DD_CFG_IEND = 0x80,
  134. };
  135. enum lis3lv02d_dd_src {
  136. DD_SRC_XL = 0x01,
  137. DD_SRC_XH = 0x02,
  138. DD_SRC_YL = 0x04,
  139. DD_SRC_YH = 0x08,
  140. DD_SRC_ZL = 0x10,
  141. DD_SRC_ZH = 0x20,
  142. DD_SRC_IA = 0x40,
  143. };
  144. struct axis_conversion {
  145. s8 x;
  146. s8 y;
  147. s8 z;
  148. };
  149. struct lis3lv02d {
  150. void *bus_priv; /* used by the bus layer only */
  151. int (*init) (struct lis3lv02d *lis3);
  152. int (*write) (struct lis3lv02d *lis3, int reg, u8 val);
  153. int (*read) (struct lis3lv02d *lis3, int reg, u8 *ret);
  154. u8 whoami; /* 3Ah: 2-byte registries, 3Bh: 1-byte registries */
  155. s16 (*read_data) (struct lis3lv02d *lis3, int reg);
  156. int mdps_max_val;
  157. struct input_dev *idev; /* input device */
  158. struct task_struct *kthread; /* kthread for input */
  159. struct mutex lock;
  160. struct platform_device *pdev; /* platform device */
  161. atomic_t count; /* interrupt count after last read */
  162. int xcalib; /* calibrated null value for x */
  163. int ycalib; /* calibrated null value for y */
  164. int zcalib; /* calibrated null value for z */
  165. unsigned char is_on; /* whether the device is on or off */
  166. unsigned char usage; /* usage counter */
  167. struct axis_conversion ac; /* hw -> logical axis */
  168. u32 irq; /* IRQ number */
  169. struct fasync_struct *async_queue; /* queue for the misc device */
  170. wait_queue_head_t misc_wait; /* Wait queue for the misc device */
  171. unsigned long misc_opened; /* bit0: whether the device is open */
  172. };
  173. int lis3lv02d_init_device(struct lis3lv02d *lis3);
  174. int lis3lv02d_joystick_enable(void);
  175. void lis3lv02d_joystick_disable(void);
  176. void lis3lv02d_poweroff(struct lis3lv02d *lis3);
  177. void lis3lv02d_poweron(struct lis3lv02d *lis3);
  178. int lis3lv02d_remove_fs(void);
  179. extern struct lis3lv02d lis3_dev;