state.c 2.0 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182
  1. #include <linux/mm.h>
  2. #include <linux/init.h>
  3. #include <asm/io.h>
  4. #include <asm/mtrr.h>
  5. #include <asm/msr.h>
  6. #include <asm/processor-cyrix.h>
  7. #include <asm/processor-flags.h>
  8. #include "mtrr.h"
  9. /* Put the processor into a state where MTRRs can be safely set */
  10. void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
  11. {
  12. unsigned int cr0;
  13. /* Disable interrupts locally */
  14. local_irq_save(ctxt->flags);
  15. if (use_intel() || is_cpu(CYRIX)) {
  16. /* Save value of CR4 and clear Page Global Enable (bit 7) */
  17. if (cpu_has_pge) {
  18. ctxt->cr4val = read_cr4();
  19. write_cr4(ctxt->cr4val & ~X86_CR4_PGE);
  20. }
  21. /*
  22. * Disable and flush caches. Note that wbinvd flushes the TLBs
  23. * as a side-effect
  24. */
  25. cr0 = read_cr0() | X86_CR0_CD;
  26. wbinvd();
  27. write_cr0(cr0);
  28. wbinvd();
  29. if (use_intel())
  30. /* Save MTRR state */
  31. rdmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
  32. else
  33. /* Cyrix ARRs - everything else were excluded at the top */
  34. ctxt->ccr3 = getCx86(CX86_CCR3);
  35. }
  36. }
  37. void set_mtrr_cache_disable(struct set_mtrr_context *ctxt)
  38. {
  39. if (use_intel())
  40. /* Disable MTRRs, and set the default type to uncached */
  41. mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo & 0xf300UL,
  42. ctxt->deftype_hi);
  43. else if (is_cpu(CYRIX))
  44. /* Cyrix ARRs - everything else were excluded at the top */
  45. setCx86(CX86_CCR3, (ctxt->ccr3 & 0x0f) | 0x10);
  46. }
  47. /* Restore the processor after a set_mtrr_prepare */
  48. void set_mtrr_done(struct set_mtrr_context *ctxt)
  49. {
  50. if (use_intel() || is_cpu(CYRIX)) {
  51. /* Flush caches and TLBs */
  52. wbinvd();
  53. /* Restore MTRRdefType */
  54. if (use_intel())
  55. /* Intel (P6) standard MTRRs */
  56. mtrr_wrmsr(MTRRdefType_MSR, ctxt->deftype_lo, ctxt->deftype_hi);
  57. else
  58. /* Cyrix ARRs - everything else was excluded at the top */
  59. setCx86(CX86_CCR3, ctxt->ccr3);
  60. /* Enable caches */
  61. write_cr0(read_cr0() & 0xbfffffff);
  62. /* Restore value of CR4 */
  63. if (cpu_has_pge)
  64. write_cr4(ctxt->cr4val);
  65. }
  66. /* Re-enable interrupts locally (if enabled previously) */
  67. local_irq_restore(ctxt->flags);
  68. }