mpspec.h 4.6 KB

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  1. #ifndef _ASM_X86_MPSPEC_H
  2. #define _ASM_X86_MPSPEC_H
  3. #include <linux/init.h>
  4. #include <asm/mpspec_def.h>
  5. extern int apic_version[MAX_APICS];
  6. extern int pic_mode;
  7. #ifdef CONFIG_X86_32
  8. /*
  9. * Summit or generic (i.e. installer) kernels need lots of bus entries.
  10. * Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets.
  11. */
  12. #if CONFIG_BASE_SMALL == 0
  13. # define MAX_MP_BUSSES 260
  14. #else
  15. # define MAX_MP_BUSSES 32
  16. #endif
  17. #define MAX_IRQ_SOURCES 256
  18. extern unsigned int def_to_bigsmp;
  19. extern u8 apicid_2_node[];
  20. #ifdef CONFIG_X86_NUMAQ
  21. extern int mp_bus_id_to_node[MAX_MP_BUSSES];
  22. extern int mp_bus_id_to_local[MAX_MP_BUSSES];
  23. extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
  24. #endif
  25. #define MAX_APICID 256
  26. #else /* CONFIG_X86_64: */
  27. #define MAX_MP_BUSSES 256
  28. /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
  29. #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
  30. #endif /* CONFIG_X86_64 */
  31. extern void early_find_smp_config(void);
  32. extern void early_get_smp_config(void);
  33. #if defined(CONFIG_MCA) || defined(CONFIG_EISA)
  34. extern int mp_bus_id_to_type[MAX_MP_BUSSES];
  35. #endif
  36. extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
  37. extern unsigned int boot_cpu_physical_apicid;
  38. extern unsigned int max_physical_apicid;
  39. extern int smp_found_config;
  40. extern int mpc_default_type;
  41. extern unsigned long mp_lapic_addr;
  42. extern void get_smp_config(void);
  43. #ifdef CONFIG_X86_MPPARSE
  44. extern void find_smp_config(void);
  45. extern void early_reserve_e820_mpc_new(void);
  46. #else
  47. static inline void find_smp_config(void) { }
  48. static inline void early_reserve_e820_mpc_new(void) { }
  49. #endif
  50. void __cpuinit generic_processor_info(int apicid, int version);
  51. #ifdef CONFIG_ACPI
  52. extern void mp_register_ioapic(int id, u32 address, u32 gsi_base);
  53. extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
  54. u32 gsi);
  55. extern void mp_config_acpi_legacy_irqs(void);
  56. extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low);
  57. extern int acpi_probe_gsi(void);
  58. #ifdef CONFIG_X86_IO_APIC
  59. extern int mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin,
  60. u32 gsi, int triggering, int polarity);
  61. extern int mp_find_ioapic(int gsi);
  62. extern int mp_find_ioapic_pin(int ioapic, int gsi);
  63. #else
  64. static inline int
  65. mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin,
  66. u32 gsi, int triggering, int polarity)
  67. {
  68. return 0;
  69. }
  70. #endif
  71. #else /* !CONFIG_ACPI: */
  72. static inline int acpi_probe_gsi(void)
  73. {
  74. return 0;
  75. }
  76. #endif /* CONFIG_ACPI */
  77. #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
  78. struct physid_mask {
  79. unsigned long mask[PHYSID_ARRAY_SIZE];
  80. };
  81. typedef struct physid_mask physid_mask_t;
  82. #define physid_set(physid, map) set_bit(physid, (map).mask)
  83. #define physid_clear(physid, map) clear_bit(physid, (map).mask)
  84. #define physid_isset(physid, map) test_bit(physid, (map).mask)
  85. #define physid_test_and_set(physid, map) \
  86. test_and_set_bit(physid, (map).mask)
  87. #define physids_and(dst, src1, src2) \
  88. bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
  89. #define physids_or(dst, src1, src2) \
  90. bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
  91. #define physids_clear(map) \
  92. bitmap_zero((map).mask, MAX_APICS)
  93. #define physids_complement(dst, src) \
  94. bitmap_complement((dst).mask, (src).mask, MAX_APICS)
  95. #define physids_empty(map) \
  96. bitmap_empty((map).mask, MAX_APICS)
  97. #define physids_equal(map1, map2) \
  98. bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
  99. #define physids_weight(map) \
  100. bitmap_weight((map).mask, MAX_APICS)
  101. #define physids_shift_right(d, s, n) \
  102. bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
  103. #define physids_shift_left(d, s, n) \
  104. bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
  105. #define physids_coerce(map) ((map).mask[0])
  106. #define physids_promote(physids) \
  107. ({ \
  108. physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
  109. __physid_mask.mask[0] = physids; \
  110. __physid_mask; \
  111. })
  112. /* Note: will create very large stack frames if physid_mask_t is big */
  113. #define physid_mask_of_physid(physid) \
  114. ({ \
  115. physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
  116. physid_set(physid, __physid_mask); \
  117. __physid_mask; \
  118. })
  119. static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
  120. {
  121. physids_clear(*map);
  122. physid_set(physid, *map);
  123. }
  124. #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
  125. #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
  126. extern physid_mask_t phys_cpu_present_map;
  127. extern int generic_mps_oem_check(struct mpc_table *, char *, char *);
  128. extern int default_acpi_madt_oem_check(char *, char *);
  129. #endif /* _ASM_X86_MPSPEC_H */