Kconfig.cpu 16 KB

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  1. # Put here option for CPU selection and depending optimization
  2. if !X86_ELAN
  3. choice
  4. prompt "Processor family"
  5. default M686 if X86_32
  6. default GENERIC_CPU if X86_64
  7. config M386
  8. bool "386"
  9. depends on X86_32 && !UML
  10. ---help---
  11. This is the processor type of your CPU. This information is used for
  12. optimizing purposes. In order to compile a kernel that can run on
  13. all x86 CPU types (albeit not optimally fast), you can specify
  14. "386" here.
  15. The kernel will not necessarily run on earlier architectures than
  16. the one you have chosen, e.g. a Pentium optimized kernel will run on
  17. a PPro, but not necessarily on a i486.
  18. Here are the settings recommended for greatest speed:
  19. - "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI
  20. 486DLC/DLC2, and UMC 486SX-S. Only "386" kernels will run on a 386
  21. class machine.
  22. - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
  23. SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
  24. - "586" for generic Pentium CPUs lacking the TSC
  25. (time stamp counter) register.
  26. - "Pentium-Classic" for the Intel Pentium.
  27. - "Pentium-MMX" for the Intel Pentium MMX.
  28. - "Pentium-Pro" for the Intel Pentium Pro.
  29. - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron.
  30. - "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
  31. - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron.
  32. - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
  33. - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
  34. - "Crusoe" for the Transmeta Crusoe series.
  35. - "Efficeon" for the Transmeta Efficeon series.
  36. - "Winchip-C6" for original IDT Winchip.
  37. - "Winchip-2" for IDT Winchips with 3dNow! capabilities.
  38. - "GeodeGX1" for Geode GX1 (Cyrix MediaGX).
  39. - "Geode GX/LX" For AMD Geode GX and LX processors.
  40. - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
  41. - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above).
  42. - "VIA C7" for VIA C7.
  43. If you don't know what to do, choose "386".
  44. config M486
  45. bool "486"
  46. depends on X86_32
  47. ---help---
  48. Select this for a 486 series processor, either Intel or one of the
  49. compatible processors from AMD, Cyrix, IBM, or Intel. Includes DX,
  50. DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or
  51. U5S.
  52. config M586
  53. bool "586/K5/5x86/6x86/6x86MX"
  54. depends on X86_32
  55. ---help---
  56. Select this for an 586 or 686 series processor such as the AMD K5,
  57. the Cyrix 5x86, 6x86 and 6x86MX. This choice does not
  58. assume the RDTSC (Read Time Stamp Counter) instruction.
  59. config M586TSC
  60. bool "Pentium-Classic"
  61. depends on X86_32
  62. ---help---
  63. Select this for a Pentium Classic processor with the RDTSC (Read
  64. Time Stamp Counter) instruction for benchmarking.
  65. config M586MMX
  66. bool "Pentium-MMX"
  67. depends on X86_32
  68. ---help---
  69. Select this for a Pentium with the MMX graphics/multimedia
  70. extended instructions.
  71. config M686
  72. bool "Pentium-Pro"
  73. depends on X86_32
  74. ---help---
  75. Select this for Intel Pentium Pro chips. This enables the use of
  76. Pentium Pro extended instructions, and disables the init-time guard
  77. against the f00f bug found in earlier Pentiums.
  78. config MPENTIUMII
  79. bool "Pentium-II/Celeron(pre-Coppermine)"
  80. depends on X86_32
  81. ---help---
  82. Select this for Intel chips based on the Pentium-II and
  83. pre-Coppermine Celeron core. This option enables an unaligned
  84. copy optimization, compiles the kernel with optimization flags
  85. tailored for the chip, and applies any applicable Pentium Pro
  86. optimizations.
  87. config MPENTIUMIII
  88. bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
  89. depends on X86_32
  90. ---help---
  91. Select this for Intel chips based on the Pentium-III and
  92. Celeron-Coppermine core. This option enables use of some
  93. extended prefetch instructions in addition to the Pentium II
  94. extensions.
  95. config MPENTIUMM
  96. bool "Pentium M"
  97. depends on X86_32
  98. ---help---
  99. Select this for Intel Pentium M (not Pentium-4 M)
  100. notebook chips.
  101. config MPENTIUM4
  102. bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
  103. depends on X86_32
  104. ---help---
  105. Select this for Intel Pentium 4 chips. This includes the
  106. Pentium 4, Pentium D, P4-based Celeron and Xeon, and
  107. Pentium-4 M (not Pentium M) chips. This option enables compile
  108. flags optimized for the chip, uses the correct cache line size, and
  109. applies any applicable optimizations.
  110. CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 )
  111. Select this for:
  112. Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename:
  113. -Willamette
  114. -Northwood
  115. -Mobile Pentium 4
  116. -Mobile Pentium 4 M
  117. -Extreme Edition (Gallatin)
  118. -Prescott
  119. -Prescott 2M
  120. -Cedar Mill
  121. -Presler
  122. -Smithfiled
  123. Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename:
  124. -Foster
  125. -Prestonia
  126. -Gallatin
  127. -Nocona
  128. -Irwindale
  129. -Cranford
  130. -Potomac
  131. -Paxville
  132. -Dempsey
  133. config MK6
  134. bool "K6/K6-II/K6-III"
  135. depends on X86_32
  136. ---help---
  137. Select this for an AMD K6-family processor. Enables use of
  138. some extended instructions, and passes appropriate optimization
  139. flags to GCC.
  140. config MK7
  141. bool "Athlon/Duron/K7"
  142. depends on X86_32
  143. ---help---
  144. Select this for an AMD Athlon K7-family processor. Enables use of
  145. some extended instructions, and passes appropriate optimization
  146. flags to GCC.
  147. config MK8
  148. bool "Opteron/Athlon64/Hammer/K8"
  149. ---help---
  150. Select this for an AMD Opteron or Athlon64 Hammer-family processor.
  151. Enables use of some extended instructions, and passes appropriate
  152. optimization flags to GCC.
  153. config MCRUSOE
  154. bool "Crusoe"
  155. depends on X86_32
  156. ---help---
  157. Select this for a Transmeta Crusoe processor. Treats the processor
  158. like a 586 with TSC, and sets some GCC optimization flags (like a
  159. Pentium Pro with no alignment requirements).
  160. config MEFFICEON
  161. bool "Efficeon"
  162. depends on X86_32
  163. ---help---
  164. Select this for a Transmeta Efficeon processor.
  165. config MWINCHIPC6
  166. bool "Winchip-C6"
  167. depends on X86_32
  168. ---help---
  169. Select this for an IDT Winchip C6 chip. Linux and GCC
  170. treat this chip as a 586TSC with some extended instructions
  171. and alignment requirements.
  172. config MWINCHIP3D
  173. bool "Winchip-2/Winchip-2A/Winchip-3"
  174. depends on X86_32
  175. ---help---
  176. Select this for an IDT Winchip-2, 2A or 3. Linux and GCC
  177. treat this chip as a 586TSC with some extended instructions
  178. and alignment requirements. Also enable out of order memory
  179. stores for this CPU, which can increase performance of some
  180. operations.
  181. config MGEODEGX1
  182. bool "GeodeGX1"
  183. depends on X86_32
  184. ---help---
  185. Select this for a Geode GX1 (Cyrix MediaGX) chip.
  186. config MGEODE_LX
  187. bool "Geode GX/LX"
  188. depends on X86_32
  189. ---help---
  190. Select this for AMD Geode GX and LX processors.
  191. config MCYRIXIII
  192. bool "CyrixIII/VIA-C3"
  193. depends on X86_32
  194. ---help---
  195. Select this for a Cyrix III or C3 chip. Presently Linux and GCC
  196. treat this chip as a generic 586. Whilst the CPU is 686 class,
  197. it lacks the cmov extension which gcc assumes is present when
  198. generating 686 code.
  199. Note that Nehemiah (Model 9) and above will not boot with this
  200. kernel due to them lacking the 3DNow! instructions used in earlier
  201. incarnations of the CPU.
  202. config MVIAC3_2
  203. bool "VIA C3-2 (Nehemiah)"
  204. depends on X86_32
  205. ---help---
  206. Select this for a VIA C3 "Nehemiah". Selecting this enables usage
  207. of SSE and tells gcc to treat the CPU as a 686.
  208. Note, this kernel will not boot on older (pre model 9) C3s.
  209. config MVIAC7
  210. bool "VIA C7"
  211. depends on X86_32
  212. ---help---
  213. Select this for a VIA C7. Selecting this uses the correct cache
  214. shift and tells gcc to treat the CPU as a 686.
  215. config MPSC
  216. bool "Intel P4 / older Netburst based Xeon"
  217. depends on X86_64
  218. ---help---
  219. Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
  220. Xeon CPUs with Intel 64bit which is compatible with x86-64.
  221. Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the
  222. Netburst core and shouldn't use this option. You can distinguish them
  223. using the cpu family field
  224. in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
  225. config MCORE2
  226. bool "Core 2/newer Xeon"
  227. ---help---
  228. Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
  229. 53xx) CPUs. You can distinguish newer from older Xeons by the CPU
  230. family in /proc/cpuinfo. Newer ones have 6 and older ones 15
  231. (not a typo)
  232. config GENERIC_CPU
  233. bool "Generic-x86-64"
  234. depends on X86_64
  235. ---help---
  236. Generic x86-64 CPU.
  237. Run equally well on all x86-64 CPUs.
  238. endchoice
  239. config X86_GENERIC
  240. bool "Generic x86 support"
  241. depends on X86_32
  242. ---help---
  243. Instead of just including optimizations for the selected
  244. x86 variant (e.g. PII, Crusoe or Athlon), include some more
  245. generic optimizations as well. This will make the kernel
  246. perform better on x86 CPUs other than that selected.
  247. This is really intended for distributors who need more
  248. generic optimizations.
  249. endif
  250. config X86_CPU
  251. def_bool y
  252. select GENERIC_FIND_FIRST_BIT
  253. select GENERIC_FIND_NEXT_BIT
  254. #
  255. # Define implied options from the CPU selection here
  256. config X86_L1_CACHE_BYTES
  257. int
  258. default "128" if MPSC
  259. default "64" if GENERIC_CPU || MK8 || MCORE2 || X86_32
  260. config X86_INTERNODE_CACHE_BYTES
  261. int
  262. default "4096" if X86_VSMP
  263. default X86_L1_CACHE_BYTES if !X86_VSMP
  264. config X86_CMPXCHG
  265. def_bool X86_64 || (X86_32 && !M386)
  266. config X86_L1_CACHE_SHIFT
  267. int
  268. default "7" if MPENTIUM4 || MPSC
  269. default "4" if X86_ELAN || M486 || M386 || MGEODEGX1
  270. default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
  271. default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MVIAC7 || X86_GENERIC || GENERIC_CPU
  272. config X86_XADD
  273. def_bool y
  274. depends on X86_32 && !M386
  275. config X86_PPRO_FENCE
  276. bool "PentiumPro memory ordering errata workaround"
  277. depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1
  278. ---help---
  279. Old PentiumPro multiprocessor systems had errata that could cause
  280. memory operations to violate the x86 ordering standard in rare cases.
  281. Enabling this option will attempt to work around some (but not all)
  282. occurances of this problem, at the cost of much heavier spinlock and
  283. memory barrier operations.
  284. If unsure, say n here. Even distro kernels should think twice before
  285. enabling this: there are few systems, and an unlikely bug.
  286. config X86_F00F_BUG
  287. def_bool y
  288. depends on M586MMX || M586TSC || M586 || M486 || M386
  289. config X86_WP_WORKS_OK
  290. def_bool y
  291. depends on !M386
  292. config X86_INVLPG
  293. def_bool y
  294. depends on X86_32 && !M386
  295. config X86_BSWAP
  296. def_bool y
  297. depends on X86_32 && !M386
  298. config X86_POPAD_OK
  299. def_bool y
  300. depends on X86_32 && !M386
  301. config X86_ALIGNMENT_16
  302. def_bool y
  303. depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1
  304. config X86_INTEL_USERCOPY
  305. def_bool y
  306. depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2
  307. config X86_USE_PPRO_CHECKSUM
  308. def_bool y
  309. depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON || MGEODE_LX || MCORE2
  310. config X86_USE_3DNOW
  311. def_bool y
  312. depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML
  313. config X86_OOSTORE
  314. def_bool y
  315. depends on (MWINCHIP3D || MWINCHIPC6) && MTRR
  316. #
  317. # P6_NOPs are a relatively minor optimization that require a family >=
  318. # 6 processor, except that it is broken on certain VIA chips.
  319. # Furthermore, AMD chips prefer a totally different sequence of NOPs
  320. # (which work on all CPUs). In addition, it looks like Virtual PC
  321. # does not understand them.
  322. #
  323. # As a result, disallow these if we're not compiling for X86_64 (these
  324. # NOPs do work on all x86-64 capable chips); the list of processors in
  325. # the right-hand clause are the cores that benefit from this optimization.
  326. #
  327. config X86_P6_NOP
  328. def_bool y
  329. depends on X86_64
  330. depends on (MCORE2 || MPENTIUM4 || MPSC)
  331. config X86_TSC
  332. def_bool y
  333. depends on ((MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2) && !X86_NUMAQ) || X86_64
  334. config X86_CMPXCHG64
  335. def_bool y
  336. depends on X86_PAE || X86_64
  337. # this should be set for all -march=.. options where the compiler
  338. # generates cmov.
  339. config X86_CMOV
  340. def_bool y
  341. depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64)
  342. config X86_MINIMUM_CPU_FAMILY
  343. int
  344. default "64" if X86_64
  345. default "6" if X86_32 && X86_P6_NOP
  346. default "4" if X86_32 && (X86_XADD || X86_CMPXCHG || X86_BSWAP || X86_WP_WORKS_OK)
  347. default "3"
  348. config X86_DEBUGCTLMSR
  349. def_bool y
  350. depends on !(MK6 || MWINCHIPC6 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486 || M386) && !UML
  351. menuconfig PROCESSOR_SELECT
  352. bool "Supported processor vendors" if EMBEDDED
  353. ---help---
  354. This lets you choose what x86 vendor support code your kernel
  355. will include.
  356. config CPU_SUP_INTEL
  357. default y
  358. bool "Support Intel processors" if PROCESSOR_SELECT
  359. ---help---
  360. This enables detection, tunings and quirks for Intel processors
  361. You need this enabled if you want your kernel to run on an
  362. Intel CPU. Disabling this option on other types of CPUs
  363. makes the kernel a tiny bit smaller. Disabling it on an Intel
  364. CPU might render the kernel unbootable.
  365. If unsure, say N.
  366. config CPU_SUP_CYRIX_32
  367. default y
  368. bool "Support Cyrix processors" if PROCESSOR_SELECT
  369. depends on !64BIT
  370. ---help---
  371. This enables detection, tunings and quirks for Cyrix processors
  372. You need this enabled if you want your kernel to run on a
  373. Cyrix CPU. Disabling this option on other types of CPUs
  374. makes the kernel a tiny bit smaller. Disabling it on a Cyrix
  375. CPU might render the kernel unbootable.
  376. If unsure, say N.
  377. config CPU_SUP_AMD
  378. default y
  379. bool "Support AMD processors" if PROCESSOR_SELECT
  380. ---help---
  381. This enables detection, tunings and quirks for AMD processors
  382. You need this enabled if you want your kernel to run on an
  383. AMD CPU. Disabling this option on other types of CPUs
  384. makes the kernel a tiny bit smaller. Disabling it on an AMD
  385. CPU might render the kernel unbootable.
  386. If unsure, say N.
  387. config CPU_SUP_CENTAUR
  388. default y
  389. bool "Support Centaur processors" if PROCESSOR_SELECT
  390. ---help---
  391. This enables detection, tunings and quirks for Centaur processors
  392. You need this enabled if you want your kernel to run on a
  393. Centaur CPU. Disabling this option on other types of CPUs
  394. makes the kernel a tiny bit smaller. Disabling it on a Centaur
  395. CPU might render the kernel unbootable.
  396. If unsure, say N.
  397. config CPU_SUP_TRANSMETA_32
  398. default y
  399. bool "Support Transmeta processors" if PROCESSOR_SELECT
  400. depends on !64BIT
  401. ---help---
  402. This enables detection, tunings and quirks for Transmeta processors
  403. You need this enabled if you want your kernel to run on a
  404. Transmeta CPU. Disabling this option on other types of CPUs
  405. makes the kernel a tiny bit smaller. Disabling it on a Transmeta
  406. CPU might render the kernel unbootable.
  407. If unsure, say N.
  408. config CPU_SUP_UMC_32
  409. default y
  410. bool "Support UMC processors" if PROCESSOR_SELECT
  411. depends on !64BIT
  412. ---help---
  413. This enables detection, tunings and quirks for UMC processors
  414. You need this enabled if you want your kernel to run on a
  415. UMC CPU. Disabling this option on other types of CPUs
  416. makes the kernel a tiny bit smaller. Disabling it on a UMC
  417. CPU might render the kernel unbootable.
  418. If unsure, say N.
  419. config X86_DS
  420. def_bool X86_PTRACE_BTS
  421. depends on X86_DEBUGCTLMSR
  422. select HAVE_HW_BRANCH_TRACER
  423. config X86_PTRACE_BTS
  424. bool "Branch Trace Store"
  425. default y
  426. depends on X86_DEBUGCTLMSR
  427. ---help---
  428. This adds a ptrace interface to the hardware's branch trace store.
  429. Debuggers may use it to collect an execution trace of the debugged
  430. application in order to answer the question 'how did I get here?'.
  431. Debuggers may trace user mode as well as kernel mode.
  432. Say Y unless there is no application development on this machine
  433. and you want to save a small amount of code size.