mpc885ads_setup.c 6.7 KB

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  1. /*
  2. * Platform setup for the Freescale mpc885ads board
  3. *
  4. * Vitaly Bordug <vbordug@ru.mvista.com>
  5. *
  6. * Copyright 2005 MontaVista Software Inc.
  7. *
  8. * Heavily modified by Scott Wood <scottwood@freescale.com>
  9. * Copyright 2007 Freescale Semiconductor, Inc.
  10. *
  11. * This file is licensed under the terms of the GNU General Public License
  12. * version 2. This program is licensed "as is" without any warranty of any
  13. * kind, whether express or implied.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <linux/param.h>
  18. #include <linux/string.h>
  19. #include <linux/ioport.h>
  20. #include <linux/device.h>
  21. #include <linux/delay.h>
  22. #include <linux/fs_enet_pd.h>
  23. #include <linux/fs_uart_pd.h>
  24. #include <linux/fsl_devices.h>
  25. #include <linux/mii.h>
  26. #include <linux/of_platform.h>
  27. #include <asm/delay.h>
  28. #include <asm/io.h>
  29. #include <asm/machdep.h>
  30. #include <asm/page.h>
  31. #include <asm/processor.h>
  32. #include <asm/system.h>
  33. #include <asm/time.h>
  34. #include <asm/mpc8xx.h>
  35. #include <asm/8xx_immap.h>
  36. #include <asm/cpm1.h>
  37. #include <asm/fs_pd.h>
  38. #include <asm/udbg.h>
  39. #include "mpc885ads.h"
  40. #include "mpc8xx.h"
  41. static u32 __iomem *bcsr, *bcsr5;
  42. #ifdef CONFIG_PCMCIA_M8XX
  43. static void pcmcia_hw_setup(int slot, int enable)
  44. {
  45. if (enable)
  46. clrbits32(&bcsr[1], BCSR1_PCCEN);
  47. else
  48. setbits32(&bcsr[1], BCSR1_PCCEN);
  49. }
  50. static int pcmcia_set_voltage(int slot, int vcc, int vpp)
  51. {
  52. u32 reg = 0;
  53. switch (vcc) {
  54. case 0:
  55. break;
  56. case 33:
  57. reg |= BCSR1_PCCVCC0;
  58. break;
  59. case 50:
  60. reg |= BCSR1_PCCVCC1;
  61. break;
  62. default:
  63. return 1;
  64. }
  65. switch (vpp) {
  66. case 0:
  67. break;
  68. case 33:
  69. case 50:
  70. if (vcc == vpp)
  71. reg |= BCSR1_PCCVPP1;
  72. else
  73. return 1;
  74. break;
  75. case 120:
  76. if ((vcc == 33) || (vcc == 50))
  77. reg |= BCSR1_PCCVPP0;
  78. else
  79. return 1;
  80. default:
  81. return 1;
  82. }
  83. /* first, turn off all power */
  84. clrbits32(&bcsr[1], 0x00610000);
  85. /* enable new powersettings */
  86. setbits32(&bcsr[1], reg);
  87. return 0;
  88. }
  89. #endif
  90. struct cpm_pin {
  91. int port, pin, flags;
  92. };
  93. static struct cpm_pin mpc885ads_pins[] = {
  94. /* SMC1 */
  95. {CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
  96. {CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
  97. /* SMC2 */
  98. #ifndef CONFIG_MPC8xx_SECOND_ETH_FEC2
  99. {CPM_PORTE, 21, CPM_PIN_INPUT}, /* RX */
  100. {CPM_PORTE, 20, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
  101. #endif
  102. /* SCC3 */
  103. {CPM_PORTA, 9, CPM_PIN_INPUT}, /* RX */
  104. {CPM_PORTA, 8, CPM_PIN_INPUT}, /* TX */
  105. {CPM_PORTC, 4, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* RENA */
  106. {CPM_PORTC, 5, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CLSN */
  107. {CPM_PORTE, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
  108. {CPM_PORTE, 17, CPM_PIN_INPUT}, /* CLK5 */
  109. {CPM_PORTE, 16, CPM_PIN_INPUT}, /* CLK6 */
  110. /* MII1 */
  111. {CPM_PORTA, 0, CPM_PIN_INPUT},
  112. {CPM_PORTA, 1, CPM_PIN_INPUT},
  113. {CPM_PORTA, 2, CPM_PIN_INPUT},
  114. {CPM_PORTA, 3, CPM_PIN_INPUT},
  115. {CPM_PORTA, 4, CPM_PIN_OUTPUT},
  116. {CPM_PORTA, 10, CPM_PIN_OUTPUT},
  117. {CPM_PORTA, 11, CPM_PIN_OUTPUT},
  118. {CPM_PORTB, 19, CPM_PIN_INPUT},
  119. {CPM_PORTB, 31, CPM_PIN_INPUT},
  120. {CPM_PORTC, 12, CPM_PIN_INPUT},
  121. {CPM_PORTC, 13, CPM_PIN_INPUT},
  122. {CPM_PORTE, 30, CPM_PIN_OUTPUT},
  123. {CPM_PORTE, 31, CPM_PIN_OUTPUT},
  124. /* MII2 */
  125. #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
  126. {CPM_PORTE, 14, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  127. {CPM_PORTE, 15, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  128. {CPM_PORTE, 16, CPM_PIN_OUTPUT},
  129. {CPM_PORTE, 17, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  130. {CPM_PORTE, 18, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  131. {CPM_PORTE, 19, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  132. {CPM_PORTE, 20, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
  133. {CPM_PORTE, 21, CPM_PIN_OUTPUT},
  134. {CPM_PORTE, 22, CPM_PIN_OUTPUT},
  135. {CPM_PORTE, 23, CPM_PIN_OUTPUT},
  136. {CPM_PORTE, 24, CPM_PIN_OUTPUT},
  137. {CPM_PORTE, 25, CPM_PIN_OUTPUT},
  138. {CPM_PORTE, 26, CPM_PIN_OUTPUT},
  139. {CPM_PORTE, 27, CPM_PIN_OUTPUT},
  140. {CPM_PORTE, 28, CPM_PIN_OUTPUT},
  141. {CPM_PORTE, 29, CPM_PIN_OUTPUT},
  142. #endif
  143. /* I2C */
  144. {CPM_PORTB, 26, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
  145. {CPM_PORTB, 27, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
  146. };
  147. static void __init init_ioports(void)
  148. {
  149. int i;
  150. for (i = 0; i < ARRAY_SIZE(mpc885ads_pins); i++) {
  151. struct cpm_pin *pin = &mpc885ads_pins[i];
  152. cpm1_set_pin(pin->port, pin->pin, pin->flags);
  153. }
  154. cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
  155. cpm1_clk_setup(CPM_CLK_SMC2, CPM_BRG2, CPM_CLK_RTX);
  156. cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK5, CPM_CLK_TX);
  157. cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_RX);
  158. /* Set FEC1 and FEC2 to MII mode */
  159. clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
  160. }
  161. static void __init mpc885ads_setup_arch(void)
  162. {
  163. struct device_node *np;
  164. cpm_reset();
  165. init_ioports();
  166. np = of_find_compatible_node(NULL, NULL, "fsl,mpc885ads-bcsr");
  167. if (!np) {
  168. printk(KERN_CRIT "Could not find fsl,mpc885ads-bcsr node\n");
  169. return;
  170. }
  171. bcsr = of_iomap(np, 0);
  172. bcsr5 = of_iomap(np, 1);
  173. of_node_put(np);
  174. if (!bcsr || !bcsr5) {
  175. printk(KERN_CRIT "Could not remap BCSR\n");
  176. return;
  177. }
  178. clrbits32(&bcsr[1], BCSR1_RS232EN_1);
  179. #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
  180. setbits32(&bcsr[1], BCSR1_RS232EN_2);
  181. #else
  182. clrbits32(&bcsr[1], BCSR1_RS232EN_2);
  183. #endif
  184. clrbits32(bcsr5, BCSR5_MII1_EN);
  185. setbits32(bcsr5, BCSR5_MII1_RST);
  186. udelay(1000);
  187. clrbits32(bcsr5, BCSR5_MII1_RST);
  188. #ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
  189. clrbits32(bcsr5, BCSR5_MII2_EN);
  190. setbits32(bcsr5, BCSR5_MII2_RST);
  191. udelay(1000);
  192. clrbits32(bcsr5, BCSR5_MII2_RST);
  193. #else
  194. setbits32(bcsr5, BCSR5_MII2_EN);
  195. #endif
  196. #ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
  197. clrbits32(&bcsr[4], BCSR4_ETH10_RST);
  198. udelay(1000);
  199. setbits32(&bcsr[4], BCSR4_ETH10_RST);
  200. setbits32(&bcsr[1], BCSR1_ETHEN);
  201. np = of_find_node_by_path("/soc@ff000000/cpm@9c0/serial@a80");
  202. #else
  203. np = of_find_node_by_path("/soc@ff000000/cpm@9c0/ethernet@a40");
  204. #endif
  205. /* The SCC3 enet registers overlap the SMC1 registers, so
  206. * one of the two must be removed from the device tree.
  207. */
  208. if (np) {
  209. of_detach_node(np);
  210. of_node_put(np);
  211. }
  212. #ifdef CONFIG_PCMCIA_M8XX
  213. /* Set up board specific hook-ups.*/
  214. m8xx_pcmcia_ops.hw_ctrl = pcmcia_hw_setup;
  215. m8xx_pcmcia_ops.voltage_set = pcmcia_set_voltage;
  216. #endif
  217. }
  218. static int __init mpc885ads_probe(void)
  219. {
  220. unsigned long root = of_get_flat_dt_root();
  221. return of_flat_dt_is_compatible(root, "fsl,mpc885ads");
  222. }
  223. static struct of_device_id __initdata of_bus_ids[] = {
  224. { .name = "soc", },
  225. { .name = "cpm", },
  226. { .name = "localbus", },
  227. {},
  228. };
  229. static int __init declare_of_platform_devices(void)
  230. {
  231. /* Publish the QE devices */
  232. of_platform_bus_probe(NULL, of_bus_ids, NULL);
  233. return 0;
  234. }
  235. machine_device_initcall(mpc885_ads, declare_of_platform_devices);
  236. define_machine(mpc885_ads) {
  237. .name = "Freescale MPC885 ADS",
  238. .probe = mpc885ads_probe,
  239. .setup_arch = mpc885ads_setup_arch,
  240. .init_IRQ = mpc8xx_pics_init,
  241. .get_irq = mpc8xx_get_irq,
  242. .restart = mpc8xx_restart,
  243. .calibrate_decr = mpc8xx_calibrate_decr,
  244. .set_rtc_time = mpc8xx_set_rtc_time,
  245. .get_rtc_time = mpc8xx_get_rtc_time,
  246. .progress = udbg_progress,
  247. };