mpc832x_mds.c 3.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170
  1. /*
  2. * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
  3. *
  4. * Description:
  5. * MPC832xE MDS board specific routines.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. */
  12. #include <linux/stddef.h>
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/errno.h>
  16. #include <linux/reboot.h>
  17. #include <linux/pci.h>
  18. #include <linux/kdev_t.h>
  19. #include <linux/major.h>
  20. #include <linux/console.h>
  21. #include <linux/delay.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/root_dev.h>
  24. #include <linux/initrd.h>
  25. #include <linux/of_platform.h>
  26. #include <linux/of_device.h>
  27. #include <asm/system.h>
  28. #include <asm/atomic.h>
  29. #include <asm/time.h>
  30. #include <asm/io.h>
  31. #include <asm/machdep.h>
  32. #include <asm/ipic.h>
  33. #include <asm/irq.h>
  34. #include <asm/prom.h>
  35. #include <asm/udbg.h>
  36. #include <sysdev/fsl_soc.h>
  37. #include <sysdev/fsl_pci.h>
  38. #include <asm/qe.h>
  39. #include <asm/qe_ic.h>
  40. #include "mpc83xx.h"
  41. #undef DEBUG
  42. #ifdef DEBUG
  43. #define DBG(fmt...) udbg_printf(fmt)
  44. #else
  45. #define DBG(fmt...)
  46. #endif
  47. /* ************************************************************************
  48. *
  49. * Setup the architecture
  50. *
  51. */
  52. static void __init mpc832x_sys_setup_arch(void)
  53. {
  54. struct device_node *np;
  55. u8 __iomem *bcsr_regs = NULL;
  56. if (ppc_md.progress)
  57. ppc_md.progress("mpc832x_sys_setup_arch()", 0);
  58. /* Map BCSR area */
  59. np = of_find_node_by_name(NULL, "bcsr");
  60. if (np) {
  61. struct resource res;
  62. of_address_to_resource(np, 0, &res);
  63. bcsr_regs = ioremap(res.start, res.end - res.start +1);
  64. of_node_put(np);
  65. }
  66. #ifdef CONFIG_PCI
  67. for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
  68. mpc83xx_add_bridge(np);
  69. #endif
  70. #ifdef CONFIG_QUICC_ENGINE
  71. qe_reset();
  72. if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
  73. par_io_init(np);
  74. of_node_put(np);
  75. for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
  76. par_io_of_config(np);
  77. }
  78. if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
  79. != NULL){
  80. /* Reset the Ethernet PHYs */
  81. #define BCSR8_FETH_RST 0x50
  82. clrbits8(&bcsr_regs[8], BCSR8_FETH_RST);
  83. udelay(1000);
  84. setbits8(&bcsr_regs[8], BCSR8_FETH_RST);
  85. iounmap(bcsr_regs);
  86. of_node_put(np);
  87. }
  88. #endif /* CONFIG_QUICC_ENGINE */
  89. }
  90. static struct of_device_id mpc832x_ids[] = {
  91. { .type = "soc", },
  92. { .compatible = "soc", },
  93. { .compatible = "simple-bus", },
  94. { .type = "qe", },
  95. { .compatible = "fsl,qe", },
  96. {},
  97. };
  98. static int __init mpc832x_declare_of_platform_devices(void)
  99. {
  100. /* Publish the QE devices */
  101. of_platform_bus_probe(NULL, mpc832x_ids, NULL);
  102. return 0;
  103. }
  104. machine_device_initcall(mpc832x_mds, mpc832x_declare_of_platform_devices);
  105. static void __init mpc832x_sys_init_IRQ(void)
  106. {
  107. struct device_node *np;
  108. np = of_find_node_by_type(NULL, "ipic");
  109. if (!np)
  110. return;
  111. ipic_init(np, 0);
  112. /* Initialize the default interrupt mapping priorities,
  113. * in case the boot rom changed something on us.
  114. */
  115. ipic_set_default_priority();
  116. of_node_put(np);
  117. #ifdef CONFIG_QUICC_ENGINE
  118. np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
  119. if (!np) {
  120. np = of_find_node_by_type(NULL, "qeic");
  121. if (!np)
  122. return;
  123. }
  124. qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
  125. of_node_put(np);
  126. #endif /* CONFIG_QUICC_ENGINE */
  127. }
  128. /*
  129. * Called very early, MMU is off, device-tree isn't unflattened
  130. */
  131. static int __init mpc832x_sys_probe(void)
  132. {
  133. unsigned long root = of_get_flat_dt_root();
  134. return of_flat_dt_is_compatible(root, "MPC832xMDS");
  135. }
  136. define_machine(mpc832x_mds) {
  137. .name = "MPC832x MDS",
  138. .probe = mpc832x_sys_probe,
  139. .setup_arch = mpc832x_sys_setup_arch,
  140. .init_IRQ = mpc832x_sys_init_IRQ,
  141. .get_irq = ipic_get_irq,
  142. .restart = mpc83xx_restart,
  143. .time_init = mpc83xx_time_init,
  144. .calibrate_decr = generic_calibrate_decr,
  145. .progress = udbg_progress,
  146. };