dma-mapping.h 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433
  1. /*
  2. * Copyright (C) 2004 IBM
  3. *
  4. * Implements the generic device dma API for powerpc.
  5. * the pci and vio busses
  6. */
  7. #ifndef _ASM_DMA_MAPPING_H
  8. #define _ASM_DMA_MAPPING_H
  9. #ifdef __KERNEL__
  10. #include <linux/types.h>
  11. #include <linux/cache.h>
  12. /* need struct page definitions */
  13. #include <linux/mm.h>
  14. #include <linux/scatterlist.h>
  15. #include <linux/dma-attrs.h>
  16. #include <asm/io.h>
  17. #define DMA_ERROR_CODE (~(dma_addr_t)0x0)
  18. #ifdef CONFIG_NOT_COHERENT_CACHE
  19. /*
  20. * DMA-consistent mapping functions for PowerPCs that don't support
  21. * cache snooping. These allocate/free a region of uncached mapped
  22. * memory space for use with DMA devices. Alternatively, you could
  23. * allocate the space "normally" and use the cache management functions
  24. * to ensure it is consistent.
  25. */
  26. extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, gfp_t gfp);
  27. extern void __dma_free_coherent(size_t size, void *vaddr);
  28. extern void __dma_sync(void *vaddr, size_t size, int direction);
  29. extern void __dma_sync_page(struct page *page, unsigned long offset,
  30. size_t size, int direction);
  31. #else /* ! CONFIG_NOT_COHERENT_CACHE */
  32. /*
  33. * Cache coherent cores.
  34. */
  35. #define __dma_alloc_coherent(gfp, size, handle) NULL
  36. #define __dma_free_coherent(size, addr) ((void)0)
  37. #define __dma_sync(addr, size, rw) ((void)0)
  38. #define __dma_sync_page(pg, off, sz, rw) ((void)0)
  39. #endif /* ! CONFIG_NOT_COHERENT_CACHE */
  40. static inline unsigned long device_to_mask(struct device *dev)
  41. {
  42. if (dev->dma_mask && *dev->dma_mask)
  43. return *dev->dma_mask;
  44. /* Assume devices without mask can take 32 bit addresses */
  45. return 0xfffffffful;
  46. }
  47. /*
  48. * DMA operations are abstracted for G5 vs. i/pSeries, PCI vs. VIO
  49. */
  50. struct dma_mapping_ops {
  51. void * (*alloc_coherent)(struct device *dev, size_t size,
  52. dma_addr_t *dma_handle, gfp_t flag);
  53. void (*free_coherent)(struct device *dev, size_t size,
  54. void *vaddr, dma_addr_t dma_handle);
  55. int (*map_sg)(struct device *dev, struct scatterlist *sg,
  56. int nents, enum dma_data_direction direction,
  57. struct dma_attrs *attrs);
  58. void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
  59. int nents, enum dma_data_direction direction,
  60. struct dma_attrs *attrs);
  61. int (*dma_supported)(struct device *dev, u64 mask);
  62. int (*set_dma_mask)(struct device *dev, u64 dma_mask);
  63. dma_addr_t (*map_page)(struct device *dev, struct page *page,
  64. unsigned long offset, size_t size,
  65. enum dma_data_direction direction,
  66. struct dma_attrs *attrs);
  67. void (*unmap_page)(struct device *dev,
  68. dma_addr_t dma_address, size_t size,
  69. enum dma_data_direction direction,
  70. struct dma_attrs *attrs);
  71. #ifdef CONFIG_PPC_NEED_DMA_SYNC_OPS
  72. void (*sync_single_range_for_cpu)(struct device *hwdev,
  73. dma_addr_t dma_handle, unsigned long offset,
  74. size_t size,
  75. enum dma_data_direction direction);
  76. void (*sync_single_range_for_device)(struct device *hwdev,
  77. dma_addr_t dma_handle, unsigned long offset,
  78. size_t size,
  79. enum dma_data_direction direction);
  80. void (*sync_sg_for_cpu)(struct device *hwdev,
  81. struct scatterlist *sg, int nelems,
  82. enum dma_data_direction direction);
  83. void (*sync_sg_for_device)(struct device *hwdev,
  84. struct scatterlist *sg, int nelems,
  85. enum dma_data_direction direction);
  86. #endif
  87. };
  88. /*
  89. * Available generic sets of operations
  90. */
  91. #ifdef CONFIG_PPC64
  92. extern struct dma_mapping_ops dma_iommu_ops;
  93. #endif
  94. extern struct dma_mapping_ops dma_direct_ops;
  95. static inline struct dma_mapping_ops *get_dma_ops(struct device *dev)
  96. {
  97. /* We don't handle the NULL dev case for ISA for now. We could
  98. * do it via an out of line call but it is not needed for now. The
  99. * only ISA DMA device we support is the floppy and we have a hack
  100. * in the floppy driver directly to get a device for us.
  101. */
  102. if (unlikely(dev == NULL))
  103. return NULL;
  104. return dev->archdata.dma_ops;
  105. }
  106. static inline void set_dma_ops(struct device *dev, struct dma_mapping_ops *ops)
  107. {
  108. dev->archdata.dma_ops = ops;
  109. }
  110. static inline int dma_supported(struct device *dev, u64 mask)
  111. {
  112. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  113. if (unlikely(dma_ops == NULL))
  114. return 0;
  115. if (dma_ops->dma_supported == NULL)
  116. return 1;
  117. return dma_ops->dma_supported(dev, mask);
  118. }
  119. /* We have our own implementation of pci_set_dma_mask() */
  120. #define HAVE_ARCH_PCI_SET_DMA_MASK
  121. static inline int dma_set_mask(struct device *dev, u64 dma_mask)
  122. {
  123. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  124. if (unlikely(dma_ops == NULL))
  125. return -EIO;
  126. if (dma_ops->set_dma_mask != NULL)
  127. return dma_ops->set_dma_mask(dev, dma_mask);
  128. if (!dev->dma_mask || !dma_supported(dev, dma_mask))
  129. return -EIO;
  130. *dev->dma_mask = dma_mask;
  131. return 0;
  132. }
  133. /*
  134. * map_/unmap_single actually call through to map/unmap_page now that all the
  135. * dma_mapping_ops have been converted over. We just have to get the page and
  136. * offset to pass through to map_page
  137. */
  138. static inline dma_addr_t dma_map_single_attrs(struct device *dev,
  139. void *cpu_addr,
  140. size_t size,
  141. enum dma_data_direction direction,
  142. struct dma_attrs *attrs)
  143. {
  144. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  145. BUG_ON(!dma_ops);
  146. return dma_ops->map_page(dev, virt_to_page(cpu_addr),
  147. (unsigned long)cpu_addr % PAGE_SIZE, size,
  148. direction, attrs);
  149. }
  150. static inline void dma_unmap_single_attrs(struct device *dev,
  151. dma_addr_t dma_addr,
  152. size_t size,
  153. enum dma_data_direction direction,
  154. struct dma_attrs *attrs)
  155. {
  156. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  157. BUG_ON(!dma_ops);
  158. dma_ops->unmap_page(dev, dma_addr, size, direction, attrs);
  159. }
  160. static inline dma_addr_t dma_map_page_attrs(struct device *dev,
  161. struct page *page,
  162. unsigned long offset, size_t size,
  163. enum dma_data_direction direction,
  164. struct dma_attrs *attrs)
  165. {
  166. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  167. BUG_ON(!dma_ops);
  168. return dma_ops->map_page(dev, page, offset, size, direction, attrs);
  169. }
  170. static inline void dma_unmap_page_attrs(struct device *dev,
  171. dma_addr_t dma_address,
  172. size_t size,
  173. enum dma_data_direction direction,
  174. struct dma_attrs *attrs)
  175. {
  176. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  177. BUG_ON(!dma_ops);
  178. dma_ops->unmap_page(dev, dma_address, size, direction, attrs);
  179. }
  180. static inline int dma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
  181. int nents, enum dma_data_direction direction,
  182. struct dma_attrs *attrs)
  183. {
  184. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  185. BUG_ON(!dma_ops);
  186. return dma_ops->map_sg(dev, sg, nents, direction, attrs);
  187. }
  188. static inline void dma_unmap_sg_attrs(struct device *dev,
  189. struct scatterlist *sg,
  190. int nhwentries,
  191. enum dma_data_direction direction,
  192. struct dma_attrs *attrs)
  193. {
  194. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  195. BUG_ON(!dma_ops);
  196. dma_ops->unmap_sg(dev, sg, nhwentries, direction, attrs);
  197. }
  198. static inline void *dma_alloc_coherent(struct device *dev, size_t size,
  199. dma_addr_t *dma_handle, gfp_t flag)
  200. {
  201. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  202. BUG_ON(!dma_ops);
  203. return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
  204. }
  205. static inline void dma_free_coherent(struct device *dev, size_t size,
  206. void *cpu_addr, dma_addr_t dma_handle)
  207. {
  208. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  209. BUG_ON(!dma_ops);
  210. dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
  211. }
  212. static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
  213. size_t size,
  214. enum dma_data_direction direction)
  215. {
  216. return dma_map_single_attrs(dev, cpu_addr, size, direction, NULL);
  217. }
  218. static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
  219. size_t size,
  220. enum dma_data_direction direction)
  221. {
  222. dma_unmap_single_attrs(dev, dma_addr, size, direction, NULL);
  223. }
  224. static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
  225. unsigned long offset, size_t size,
  226. enum dma_data_direction direction)
  227. {
  228. return dma_map_page_attrs(dev, page, offset, size, direction, NULL);
  229. }
  230. static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
  231. size_t size,
  232. enum dma_data_direction direction)
  233. {
  234. dma_unmap_page_attrs(dev, dma_address, size, direction, NULL);
  235. }
  236. static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
  237. int nents, enum dma_data_direction direction)
  238. {
  239. return dma_map_sg_attrs(dev, sg, nents, direction, NULL);
  240. }
  241. static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
  242. int nhwentries,
  243. enum dma_data_direction direction)
  244. {
  245. dma_unmap_sg_attrs(dev, sg, nhwentries, direction, NULL);
  246. }
  247. #ifdef CONFIG_PPC_NEED_DMA_SYNC_OPS
  248. static inline void dma_sync_single_for_cpu(struct device *dev,
  249. dma_addr_t dma_handle, size_t size,
  250. enum dma_data_direction direction)
  251. {
  252. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  253. BUG_ON(!dma_ops);
  254. dma_ops->sync_single_range_for_cpu(dev, dma_handle, 0,
  255. size, direction);
  256. }
  257. static inline void dma_sync_single_for_device(struct device *dev,
  258. dma_addr_t dma_handle, size_t size,
  259. enum dma_data_direction direction)
  260. {
  261. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  262. BUG_ON(!dma_ops);
  263. dma_ops->sync_single_range_for_device(dev, dma_handle,
  264. 0, size, direction);
  265. }
  266. static inline void dma_sync_sg_for_cpu(struct device *dev,
  267. struct scatterlist *sgl, int nents,
  268. enum dma_data_direction direction)
  269. {
  270. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  271. BUG_ON(!dma_ops);
  272. dma_ops->sync_sg_for_cpu(dev, sgl, nents, direction);
  273. }
  274. static inline void dma_sync_sg_for_device(struct device *dev,
  275. struct scatterlist *sgl, int nents,
  276. enum dma_data_direction direction)
  277. {
  278. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  279. BUG_ON(!dma_ops);
  280. dma_ops->sync_sg_for_device(dev, sgl, nents, direction);
  281. }
  282. static inline void dma_sync_single_range_for_cpu(struct device *dev,
  283. dma_addr_t dma_handle, unsigned long offset, size_t size,
  284. enum dma_data_direction direction)
  285. {
  286. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  287. BUG_ON(!dma_ops);
  288. dma_ops->sync_single_range_for_cpu(dev, dma_handle,
  289. offset, size, direction);
  290. }
  291. static inline void dma_sync_single_range_for_device(struct device *dev,
  292. dma_addr_t dma_handle, unsigned long offset, size_t size,
  293. enum dma_data_direction direction)
  294. {
  295. struct dma_mapping_ops *dma_ops = get_dma_ops(dev);
  296. BUG_ON(!dma_ops);
  297. dma_ops->sync_single_range_for_device(dev, dma_handle, offset,
  298. size, direction);
  299. }
  300. #else /* CONFIG_PPC_NEED_DMA_SYNC_OPS */
  301. static inline void dma_sync_single_for_cpu(struct device *dev,
  302. dma_addr_t dma_handle, size_t size,
  303. enum dma_data_direction direction)
  304. {
  305. }
  306. static inline void dma_sync_single_for_device(struct device *dev,
  307. dma_addr_t dma_handle, size_t size,
  308. enum dma_data_direction direction)
  309. {
  310. }
  311. static inline void dma_sync_sg_for_cpu(struct device *dev,
  312. struct scatterlist *sgl, int nents,
  313. enum dma_data_direction direction)
  314. {
  315. }
  316. static inline void dma_sync_sg_for_device(struct device *dev,
  317. struct scatterlist *sgl, int nents,
  318. enum dma_data_direction direction)
  319. {
  320. }
  321. static inline void dma_sync_single_range_for_cpu(struct device *dev,
  322. dma_addr_t dma_handle, unsigned long offset, size_t size,
  323. enum dma_data_direction direction)
  324. {
  325. }
  326. static inline void dma_sync_single_range_for_device(struct device *dev,
  327. dma_addr_t dma_handle, unsigned long offset, size_t size,
  328. enum dma_data_direction direction)
  329. {
  330. }
  331. #endif
  332. static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
  333. {
  334. #ifdef CONFIG_PPC64
  335. return (dma_addr == DMA_ERROR_CODE);
  336. #else
  337. return 0;
  338. #endif
  339. }
  340. #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
  341. #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
  342. #ifdef CONFIG_NOT_COHERENT_CACHE
  343. #define dma_is_consistent(d, h) (0)
  344. #else
  345. #define dma_is_consistent(d, h) (1)
  346. #endif
  347. static inline int dma_get_cache_alignment(void)
  348. {
  349. #ifdef CONFIG_PPC64
  350. /* no easy way to get cache size on all processors, so return
  351. * the maximum possible, to be safe */
  352. return (1 << INTERNODE_CACHE_SHIFT);
  353. #else
  354. /*
  355. * Each processor family will define its own L1_CACHE_SHIFT,
  356. * L1_CACHE_BYTES wraps to this, so this is always safe.
  357. */
  358. return L1_CACHE_BYTES;
  359. #endif
  360. }
  361. static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
  362. enum dma_data_direction direction)
  363. {
  364. BUG_ON(direction == DMA_NONE);
  365. __dma_sync(vaddr, size, (int)direction);
  366. }
  367. #endif /* __KERNEL__ */
  368. #endif /* _ASM_DMA_MAPPING_H */